8-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT µPD7894

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8-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT µPD7894

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µPD789405, 789406, 789407
8-BIT SINGLE-CHIP MICROCONTROLLER
INTEGRATED CIRCUIT
µPD789405, µPD789406, µPD789407 µPD789407 sub-series products (LCD drivers) 78K/0S series. These microcontrollers feature 8-bit CPU, controller/driver, ports, timers, serial interface, converters, interrupt control circuits. instruction µPD789405, µPD789406, µPD789407 subset 78K/0 series standard instruction set. addition, flash memory product (µPD78F9418) that operate within same voltage range mask models, range related development tools being developed. functions these microcontrollers described following user's manual. Refer this manual when designing system based these microcontrollers. µPD789407 µPD789417 Sub-Series User's Manual: Under development
FEATURES
sizes
Item Program memory (ROM) Kbytes Kbytes Kbytes bits bits 80-pin plastic 80-pin plastic TQFP (fine pitch) Data memory Internal high-speed data Package
Product name
µPD789405 µPD789406 µPD789407
Variable instruction execution time: From high-speed (0.4 with main system clock running MHz) ultra-low speed (122 with subsystem clock running 32.768 kHz) ports Serial interface channel: Switchable between three-wire serial UART modes controller/driver: segment signal outputs common signal outputs Bias switchable between Seven converters with 8-bit resolution timers: 16-bit timer/counter 8-bit timer/event counters 8-bit timer/counter Clock timer Watchdog timer Power supply voltage VDD:
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production.
Document U12240EJ1V0PM00 (1st edition) Date Published 1997 Printed Japan
1997
µPD789405, 789406, 789407
APPLICATIONS
compact cameras manometers
ORDERING INFORMATION
Part number Package 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch)
Remark
indicates code number.
µPD789405, 789406, 789407
78K/0S SERIES DEVELOPMENT
ASSP
driver devices
µPD789806Y sub-series
monitor ROM: Package: 42-pin SDIP Built-in function synchronizing separation circuit
PD789417 sub-series PD789407 sub-series
ROM: Package: 80-pin TQFP Built-in converter UART ROM: Device developed enhancing function PD789407
Devices small-scale, general-purpose applications
µPD789026 sub-series µPD789014 sub-series
Minimum instruction execution time: ROM: Package: 28-pin SDIP Built-in UART Enhanced timer ROM: Package: 42-pin SDIP 44-pin
ASSP: Application Specific Standard Product Universal Serial
Under development
µPD789405, 789406, 789407
following table lists major differences functions between sub-series.
Function size Sub-series driving ASSP 8-bit K-32 K-24 16-bit Clock Timer
8-bit
10-bit
8-bit
Serial interface (UART:
Minimum value
External expansion
µPD789417 µPD789407
ports
µPD789806Y
K-16
(UART:
ports ports ports
Small µPD789026 scale general µPD789014 purpose
µPD789405, 789406, 789407
78K/0 SERIES DEVELOPMENT
78K/0 series products shown below. sub-series names indicated frames.
production Under development sub-series products compatible with bus.
Used control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B PD78078 µPD78070A µPD780058 PD78058F PD78054 PD780034 µPD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
µPD78075BY PD78078Y µPD78070AY µPD780058YNote PD78058FY PD78054Y PD780034Y µPD780024Y PD78018FY PD78014Y PD78002Y
PD780018Note µPD780018YNote
noise version µPD78078 Device with enhanced external interface, developed adding timer µPD78054 ROM-less version µPD78078 Device developed enhancing serial µPD78078 limiting functions noise version µPD78054, developed enhancing serial noise version µPD78054 Device developed adding UART functions µPD78014 enhancing Device developed enhancing function µPD780024 noise version µPD78018F, developed enhancing serial noise version µPD78018F Low-voltage (1.8 version µPD78014, with enhanced variations Device developed adding 16-bit timer functions µPD78002 Device developed adding functions µPD78002 Basic series control With built-in UART capable low-voltage (1.8 operation
inverter control 64-pin 64-pin
PD780964 PD780924
Device developed enhancing function µPD780924 Built-in inverter control circuit UART bus. noise version.
78K/0 series
driving FIP100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
Device developed enhancing functions µPD78044F, with total display outputs Device developed enhancing functions µPD78044H, with total display outputs Device developed adding N-channel, open-drain input/output ports, with total display outputs. Basic sub-series driving, with total display outputs
driving 100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
µPD780308Y PD78064Y
Device developed enhancing µPD78064, with expanded noise version µPD78064 Basic sub-series driving, with built-in UART
Device supporting IEBus80-pin
PD78098
Device developed adding IEBus controller µPD78054
Note Device planning stage
µPD789405, 789406, 789407
following table lists major functional differences between sub-series.
Function size Sub-series control 8-bit K-40 K-60 K-60 (3-wire time-division: 16-bit Clock Timer
8-bit
10-bit
8-bit
Serial interface (UART:
Minimum value
External expansion
µPD78075B µPD78078 µPD78070A µPD780018
ports
ports ports
µPD780058
K-60
(UART time-division:
ports
µPD78058F µPD78054 µPD780034
K-60 K-60 K-32
(UART:
ports
(UART ports 3-wire time division:
µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F
µPD780308 driving K-60 K-60 K-48 K-40 K-60 K-60 K-32 K-16
ports
(UART: ports ports ports
inverter control driving
K-32
Note
(UART:
ports
ports ports ports
(UART time division: ports
µPD78064B µPD78064
µPD78098 supporting IEBus
K-32 K-60
(UART: (UART: ports
Note 10-bit timer
µPD789405, 789406, 789407
FUNCTIONS
Item Built-in memory High-speed data Instruction cycle
µPD789405
Kbytes bytes bytes
µPD789406
Kbytes
µPD789407
Kbytes
Built-in function changing instruction execution time 0.4/1.6 (operation with main system clock running MHz) (operation with subsystem clock running 32.768 kHz). bits registers 16-bit operations manipulations (such set, reset, test)
General-purpose registers Instruction
ports
Total ports CMOS input ports CMOS input/output ports N-channel open-drain ports (dielectric strength
converters Comparator Serial interface controller/driver
Seven channels with 8-bit resolution With timer output control function Switchable between three-wire serial UART modes segment signal outputs common signal outputs Bias switchable between 16-bit timer/counter 8-bit timer/counter 8-bit timer/event counters Clock timer Watchdog timer
Timers
Timer output Vector interrupt sources Power supply voltage Operating ambient temperature Package Maskable Non-maskable
outputs internal external interrupts Internal interrupt 80-pin plastic 80-pin plastic TQFP (fine pitch)
µPD789405, 789406, 789407
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
Port Pins Non-Port Pins. Input/Output Circuits Handling Unused Pins.
ARCHITECTURE
Memory Space Data Memory Addressing Processor Registers
PERIPHERAL HARDWARE FUNCTIONS.
Ports. Clock Generator. 16-Bit Timer/Counter 8-Bit Timer/Event Counter Clock Timer. Watchdog Timer. 8-Bit Converter. Comparator Serial Interface Channel
5.10 Controller/Driver
INTERRUPT FUNCTIONS.
Interrupt Function Types Interrupt Sources Configuration Interrupt Function Control Registers.
STANDBY FUNCTION
Standby Function. Standby Function Control Register
RESET FUNCTIONS MASK OPTIONS
INSTRUCTION OVERVIEW.
10.1 Legend 10.2 Operations
µPD789405, 789406, 789407
ELECTRICAL CHARACTERISTICS (TARGET VALUES). PACKAGE DIMENSIONS. APPENDIX DEVELOPMENT TOOLS. APPENDIX RELATED DOCUMENTS
µPD789405, 789406, 789407
CONFIGURATION (TOP VIEW)
80-pin plastic 80-pin plastic TQFP (fine pitch)(12
P40/KR0 P41/KR1 P42/KR2 P43/KR3 P44/KR4 P45/KR5
RESET
VDD0
VSS0
VDD1 BIAS VLC0 VLC1 VLC2 VSS1 COM0 COM1 COM2 COM3 P20/SCK/ASCK P21/SO/TxD P22/SI/RxD P23/CMPTOUT0/TO2 P24/INTP0/TI0 P25/INTP1/TI1 P26/INTP2/TO5 P27/INTP3/CPT5 AVSS P60/ANI0/CMPIN0 P61/ANI1/CMPREF0 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6
P93/S16
P92/S17
P91/S18
P90/S19
P87/S20
P86/S21
P85/S22
P84/S23
P83/S24
P82/S25
P81/S26
P80/S27
Cautions Connect (internally connected) directly VSS0 VSS1. Connect AVDD VDD0. Connect AVSS VSS0.
AVREF
AVDD
µPD789405, 789406, 789407
ANI0-ANI6 ASCK AVDD AVREF AVSS BIAS CMPIN0 CMPREF0
Analog Input Asynchronous Serial Input Analog Power Supply Analog Reference Voltage Analog Ground Power Supply Bias Control Comparator Input Comparator Reference
P60-P66 Port P80-P87 Port P90-P93 Port RESET S0-S27 TI0, Reset Receive Data Segment Output Serial Clock Serial Input Serial Output Timer Input Transmit Data
CMPTOUT0 Comparator Output COM0-COM3: Common Output CPT5 KR0-KR5 P00-P03 P20-P27 P40-P47 P50-P53 Capture Trigger Input Internally Connected Return Port Port Port Port
TO2, Timer Output VDD0, VDD1 Power Supply VLC0-VLC2 Power Supply VSS0, VSS1 Ground Crystal (Main System Clock) XT1, Crystal (Subsystem Clock)
INTP0-INTP3 Interrupt from Peripherals
µPD789405, 789406, 789407
BLOCK DIAGRAM
TI0/INTP0/P24 8-bit TIMER EVENT/COUNTER 8-bit TIMER EVENT/COUNTER 8-bit TIMER COUNTER 16-bit TIMER COUNTER PORT0 P00-P03
TI1/INTP1/P25
PORT2
P20-P27
TO2/CMPTOUT0 /P23 TO5/INTP2/P26 CPT5/INTP3/P27
PORT4
P40-P47
PORT5
P50-P53
WATCH TIMER
78K/0S CORE
PORT6
P60-P66
WATCHDOG TIMER
PORT8
P80-P87
SCK/ASCK/P20 SO/TxD/P21 SI/RxD/P22 ANI0/CMPIN0/P60 ANI1/CMPREF0/P61 ANI2/P62ANI6/P66 AVDD AVSS AVREF S0-S15 S15/P93-S19/P90 S20/P87-S27/P80 COM0-COM3 VLC0-VLC2 BIAS
SERIAL INTERFACE
PORT9
P90-P93
SYSTEM CONTROL CONVERTER
RESET INTP0/TI0/P24 INTP1/TI1/P25 INTP2/TO5/P26 INTP3/CPT5/P27 KR0/P40-KR5/P45 CMPTOUT0/TO2/P23 CMPIN0/ANI0/P60 CMPREF0/ANI1/P61
INTERRUPT CONTROL CONTROLLER/ COMPARATOR DRIVER
VDD0 VDD1 VSS0 VSS1
Remark
size built-in varies depending model.
µPD789405, 789406, 789407
FUNCTIONS Port Pins
name P00-P03 Port 4-bit input/output port either input output 1-bit units When used input port, whether built-in pull-up resistor used specified software. P40-P45 P46, Port 8-bit input/output port either input output 1-bit units When used input port, whether built-in pull-up resistor used specified software. P50-P53 Port 4-bit N-channel open-drain input/output port either input output 1-bit units Whether pull-up resistor incorporated specified mask option. P62-P66 P80-P87 Port 8-bit input/output port either input output 1-bit units When used input port, whether built-in pull-up resistor used specified software. P90-P93 Port 4-bit input/output port either input output 1-bit units When used input port, whether built-in pull-up resistor used specified software. Input S19-S16 Input Input Port 7-bit input-only port Input ANI0/CMPIN0 ANI1/CMPREF0 ANI2-ANI6 S27-S20 Input Input Port 8-bit input/output port either input output 1-bit units When used input port, whether built-in pull-up resistor used specified software. Input SCK/ASCK SO/TxD SI/RxD CMPTOUT0/TO2 INTP0/TI0 INTP1/TI1 INTP2/TO5 INTP3/CPT5 KR0-KR5 Function When reset Input Also used
µPD789405, 789406, 789407
Non-Port Pins
name INTP0 INTP1 INTP2 INTP3 KR0-KR5 ASCK CPT5 CMPTOUT0 CMPIN0 CMPREF0 ANI0 ANI1 ANI2-ANI6 AVREF AVSS AVDD S0-S15 S16-S19 S20-S27 COM0-COM3 VLC0-VLC2 BIAS RESET VDD0 VDD1 VSS0 VSS1 Output Input Input Input System reset input Positive supply voltage ports Positive supply voltage circuits other than ports Port section ground potential Ground potential circuits other than ports Internally connected directly VSS0 VSS1 Connected crystal subsystem clock oscillation controller/driver common signal output driving voltage Supply voltage driving Connected crystal main system clock oscillation Output Input Output converter reference voltage converter ground potential converter analog power supply controller/driver segment signal output Output Input Input Input Output Input Input Input Output Input Input Output Output Input Output Input Input Input return signal detection Serial data input serial interface Serial data output from serial interface Serial clock input serial interface Serial clock input asynchronous serial interface Serial data input asynchronous serial interface Serial data output from asynchronous serial interface External count clock input 8-bit timer (TM0) External count clock input 8-bit timer (TM1) 8-bit timer (TM2) output 16-bit timer (TM5) output Capture edge input Comparator output Comparator input Comparator reference voltage input converter analog input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function External interrupt input which effective edges (rising and/or falling edges) specified When reset Input Also used P24/TI0 P25/TI1 P26/TO5 P27/CPT5 P40-P45 P22/RxD P21/TxD P20/ASCK P20/SCK P22/SI P21/SO P24/INTP0 P25/INTP1 P23/CMPTOUT0 P26/INTP2 P27/INTP3 P23/TO2 P60/ANI0 P61/ANI1 P60/CMPIN0 P61/CMPREF0 P62-P66 P93-P90 P87-P80
µPD789405, 789406, 789407
Input/Output Circuits Handling Unused Pins
Table lists types input/output circuits each explains unused pins handled. Figure shows configuration each type input/output circuit. Table 3-1. Type Input/Output Circuit Each Handling Unused Pins
name P00-P03 P20/SCK/ASCK P21/SO/TxD P22/SI/RxD P23/CMPTOUT0/TO2 P24/INTP0/TI0 P25/INTP1/TI1 P26/INTP2/TO5 P27/INTP3/CPT5 P40/KR0-P45/KR5 P46, P50-P53 P60/ANI0/CMPIN0 P61/ANI1/CMPREF0 P62/ANI2-P66/ANI6 P80/S27-P87/S20 P90/S19-P93/S16 S0-S15 COM0-COM3 VLC0-VLC2 BIAS 17-B 18-A Open (alternatively, connected VSS0 VSS1 resistor independently other pins, when none VLC0 VLC2 used, however) RESET Input Input Connected VSS0 VSS1, resistor, independently other pins Open Connected directly VSS0 VSS1 Output Open 17-F 13-Q Input 10-B circuit type Recommended connection unused pins Separately connected VDD0, VDD1, VSS0, VSS1 respective resistors
µPD789405, 789406, 789407
Figure 3-1. Input/Output Circuits (1/2)
Type Type
P-ch N-ch AVSS
Comparator
VREF (Threshold voltage)
Schmitt trigger input with hysteresis
Input enable
Type
VDD0
Type 10-B VDD0
Pullup enable VDD0 Data P-ch
P-ch
Pullup enable VDD0 Data IN/OUT P-ch
P-ch
Output disable
IN/OUT N-ch VSS0 Open drain Output disable VSS0 N-ch
Input enable Type VDD0 Type 13-Q VDD0 Pullup enable VDD0 Data P-ch IN/OUT Output disable N-ch VSS0 Input enable Buffer with medium dielectric strength Output data Output disable N-ch P-ch Pullup resistor (mask option) IN/OUT
VSS0
Type
Type 17-B VLC0
P-ch N-ch AVSS
VLC1
P-ch N-ch P-ch
VREF (Threshold voltage)
data P-ch N-ch N-ch
Input enable Comparator
VLC2
VSS1
µPD789405, 789406, 789407
Figure 3-1. Input/Output Circuits (2/2)
Type 17-F Type 18-A VLC0 Pullup enable Data P-ch VDD0 P-ch IN/OUT Output disable N-ch VSS0 VLC2 data P-ch N-ch N-ch P-ch VLC1 P-ch N-ch P-ch N-ch
VDD0
Input enable
VSS1
VLC0 P-ch VLC1 data output disable VLC2 N-ch VSS1
P-ch
N-ch
µPD789405, 789406, 789407
ARCHITECTURE Memory Space
µPD789405, µPD789406, µPD789407 each access Kbytes memory space. Figure shows memory map. Figure 4-1. Memory
FFFFH Special function register bits FFFFH FEFFH Built-in high-speed bits FD00H FCFFH
Unusable
space data bits Data memory space F9FFH nnnnH+1 nnnnH nnnnH Unusable
Program area
Program memory space
Built-in ROMNote
0080H 007FH CALLT table area 0040H 003FH 0024H 0023H Program area Vector table area 0000H
0000H
Note size built-in varies depending model. (See following table.)
Last address built-in nnnnH 2FFFH 3FFFH 5FFFH
Product name
µPD789405 µPD789406 µPD789407
µPD789405, 789406, 789407
Data Memory Addressing
Each µPD789405, µPD789406, µPD789407 provided with wide range addressing modes make memory manipulation efficient possible. data memory area (FD00H FFFFH) accessed using unique addressing mode according use, such special function register (SFR). illustrates data memory addressing modes. Figure 4-2. Data Memory Addressing Modes
FFFFH Special function register (SFR) bits FF20H FF1FH FF00H FEFFH addressing
Figure
Built-in high-speed bits
Short direct addressing
FE20H FE1FH FD00H FCFFH Unusable FA1BH
Direct addressing Register indirect addressing Based addressing
space data bits
FA00H F9FFH nnnnH+1 nnnnH Unusable
Built-in ROMNote
0000H
Note size built-in varies depending model. (See following table.)
Last address built-in nnnnH 2FFFH 3FFFH 5FFFH
Product name
µPD789405 µPD789406 µPD789407
µPD789405, 789406, 789407
Processor Registers
4.3.1 Controller registers Program counter (PC) 16-bit register holding address information that indicates next program executed. Figure 4-3. Program Counter Configuration
Program status word (PSW) 8-bit register holding status according results instruction execution. Figure 4-4. Program Status Word Configuration
Interrupt enable flag (IE) used control whether interrupt requests accepted CPU. Zero flag result operation zero. Otherwise, reset (0). Auxiliary carry flag (AC) result operation carry from borrow Otherwise, reset (0). Carry flag (CY) used indicate whether overflow underflow occurred during execution subtract instruction. Stack pointer (SP) 16-bit register holding start address stack area. stack area specified only area (FD00H FEFFH) built-in high-speed RAM. Figure 4-5. Stack Pointer Configuration
Caution RESET input makes content undefined. initialize
Before executing instruction, always
µPD789405, 789406, 789407
4.3.2 General-purpose registers Each device eight 8-bit general-purpose registers These registers used 16-bit registers (two 8-bit registers used pairs like well ordinary 8-bit registers. These registers identified using functional register names absolute register names RP3). Figure 4-6. General Register Configuration Absolute register names
16-bit processing 8-bit processing
Functional register names
16-bit processing 8-bit processing
µPD789405, 789406, 789407
4.3.3 Special function registers (SFRs) SFRs used peripheral hardware mode registers control registers. They mapped 256-byte space, from FF00H FFFFH. Table 4-1. Special Function Registers (1/2)
Number bits manipulated simultaneously FF00H FF02H FF04H FF05H FF06H FF08H FF09H FF10H Port Port Port Port Port Port Port Transmission shift register Reception buffer register FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF22H FF24H FF25H FF28H FF29H FF42H FF48H FF4AH FF4EH FF50H FF51H FF53H FF54H FF55H Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Timer clock selection register 16-bit timer mode control register Clock timer mode control register Comparator mode register 8-bit compare register 8-bit timer register 8-bit timer mode control register 8-bit compare register 8-bit timer register TCL2 TMC5 WCMPRM0
Address
Special function register (SFR) name
Symbol
SIO0
When reset
bits
bits Undefined
8-bit conversion result register 16-bit compare register
ADCRH
CR50L CR50H
Note
CR50
FFFFH
16-bit timer register
Note
0000H
16-bit capture register
TCP5
Note
Undefined
CR00 TMC0 CR10
Undefined
Undefined
Note R50, TM5, TCP5 designed 16-bit access. They also accessed 8-bit mode, however. 8-bit access mode, direct addressing.
µPD789405, 789406, 789407
Table 4-1. Special Function Registers (2/2)
Number bits manipulated simultaneously FF57H FF58H FF59H FF5BH FF70H 8-bit timer mode control register 8-bit compare register 8-bit timer register 8-bit timer mode control register Asynchronous serial interface mode register FF71H Asynchronous serial interface status register FF72H FF73H FF80H FF84H FFB0H FFB1H FFB2H FFE0H FFE1H FFE4H FFE5H FFECH FFEDH FFF0H Serial operation mode register Baud rate generator control register converter mode register input selection register display mode register port selector clock control register Interrupt request flag register Interrupt request flag register Interrupt mask flag register Interrupt mask flag register External interrupt mode register External interrupt mode register Subsystem clock oscillation mode register FFF2H FFF3H FFF4H FFF5H FFF7H FFF9H FFFAH Subclock control register Pull-up resistor option register Pull-up resistor option register return mode register Pull-up resistor option register Watchdog timer mode register Oscillation settling time selection register FFFBH Processor clock control register WDOSTS CSIM0 BRGC LCDM LCDC INTM0 INTM1 SCKM ASIS TMC1 CR20 TMC2 ASIM bits bits Undefined
Address
Special function register (SFR) name
Symbol
When reset
µPD789405, 789406, 789407
PERIPHERAL HARDWARE FUNCTIONS Ports
5.1.1 Port functions µPD789405, µPD789406, µPD789407 provided with ports shown Figure 5-1. These ports used enable several types control. Table lists functions each port. These ports, while originally designed digital input/output ports, also used other functions, summarized Chapter Figure 5-1. Port Types
Port
Port
Port
Port
Port Port
Port
µPD789405, 789406, 789407
Table 5-1. Port Functions
Port name Port name P00-P03 Description Input/output port. Each port separately specified being input output. port used input connected internal pull-up resistor means software specification. Port P20-P27 Input/output port. Each port separately specified being input output. port used input connected internal pull-up resistor means software specification. Port P40-P47 Input/output port. Each port separately specified being input output. port used input connected internal pull-up resistor means software specification. Port P50-P53 N-channel open-drain input/output port. Each port separately specified being input output. Whether port itself contain pull-up resistor specified with mask option. Port Port P60-P66 P80-P87 Input-only port Input/output port. Each port separately specified being input output. port used input connected internal pull-up resistor means software specification. Port P90-P93 Input/output port. Each port separately specified being input output. port used input connected internal pull-up resistor means software specification.
µPD789405, 789406, 789407
5.1.2 Port configuration hardware configuration ports follows. Table 5-2. Port Configuration
Item Control register Configuration Port mode register (PMm, where Pull-up resistor option register (PU0 PU2) Ports Pull-up resistors Total: input/output input-only ports) Total: (internal pull-up resistors used specified software, whether port itself contain pull-up resistors specified with mask option)
Figure 5-2. Basic Port Configuration
WRPU
P-ch
Internal
WRPORT Output latch (Pmn)
WRPM
PMmn
Caution Figure shows basic configuration input/output ports. configuration differs depending functions assigned dual-function pins. Remark pull-up resistor option register (PU), where PMmn port mode register where port Port read signal Port write signal
µPD789405, 789406, 789407
5.1.3 Port function control registers following types registers used control ports. Port mode registers (PM0, PM2, PM4, PM5, PM8, PM9) Pull-up resistor option registers (PU0 PU2)
Port mode registers (PM0, PM2, PM4, PM5, PM8, PM9) port mode registers separately specify each port being input output. Each port mode register manipulated using 1-bit 8-bit memory manipulation instruction. RESET input writes into port mode registers. When port pins used secondary functions, corresponding port mode register output latch must reset described Table 5-3. Caution When port acting output port, output level changed, interrupt request flag set, because this port also used input external interrupt. port output mode, therefore, interrupt mask flag must advance.
µPD789405, 789406, 789407
Table 5-3. Port Mode Register Output Latch Settings Using Secondary Functions
Secondary function name Name CMPTOUT0 INTP0 INTP1 INTP2 INTP3 CPT5 P40-P45
Note
Input/output Output Output Input Input Input Input Input Output Input Input Input Input Input Input Input Input Output Output
KR0-KR5 ANI0 CMPIN0
ANI1 CMPREF0
P62-P66 P80-P87 P90-P93
ANI2-ANI6 S27-S20 S19-S16
Note secondary functions, return mode register (KRM) (See Section 6.3.) Caution When port being used serial interface, necessary specify whether port input output port, output latch accordingly. Table 5-13 explanation make this specification. Remark Don't care Port output latch
Port mode register
µPD789405, 789406, 789407
Figure 5-3. Port Mode Register Format
Symbol Address FF20H When reset
PM03 PM02 PM01 PM00
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FF22H
PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
FF24H
PM53 PM52 PM51 PM50
FF25H
PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
FF28H
PM93 PM92 PM91 PM90
FF29H
PMmn
input/output mode selection
Output mode (output buffer Input mode (output buffer OFF)
Pull-up resistor option registers (PU0 PU2) These registers used specify whether internal pull-up resistor used each port. internal pull-up resistor used only port that input mode which internal pull-up resistor selected using corresponding pull-up resistor option register. port output mode, internal pull-up resistor used with even internal pull-up resistor been specified using corresponding option register. function. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. same applies when port used secondary
µPD789405, 789406, 789407
Figure 5-4. Format Pull-Up Resistor Option Register
PU04 PU00 Address FFF7H When reset
PU0m
internal pull-up resistor selectionNote
Internal pull-up resistor used Internal pull-up resistor used
Note selects whether internal pull-up resistors used 8-bit units, except port which internal pull-up resistors used with only four bits (P00 P03). Caution Bits must fixed Figure 5-5. Format Pull-Up Resistor Option Register
Address FFF3H When reset
PU127 PU126 PU125 PU124 PU123 PU122 PU121 PU120
PU12m Internal pull-up resistor used Internal pull-up resistor used
internal pull-up resistor selectionNote
Note selects whether internal pull-up resistors used 1-bit units. Figure 5-6. Format Pull-Up Resistor Option Register
Address FFF4H When reset
PU292 PU290 PU286 PU284 PU282 PU280
PU2mn
internal pull-up resistor selectionNote
Internal pull-up resistor used Internal pull-up resistor used
Note selects whether internal pull-up resistors used 2-bit units (bit n+1). Caution Bits must fixed
µPD789405, 789406, 789407
Clock Generator
5.2.1 Clock generator functions clock generator generates clock pulse supplied peripheral hardware. There types system clock oscillators: Main system clock oscillator This circuit generates frequency MHz. Oscillation stopped executing STOP instruction using processor clock control register. Subsystem clock oscillator This circuit generates 32.768 kHz. Oscillation stopped using suboscillation mode register. 5.2.2 Clock generator configuration clock generator consists following hardware. Table 5-4. Clock Generator Configuration
Item Control register Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Oscillators Main system clock oscillator Subsystem clock oscillator Configuration
µPD789405, 789406, 789407
Figure 5-7. Clock Generator Block Diagram
Internal
Suboscillation mode register
Subsystem clock oscillation
8-bit timer Clock timer clock Prescaler
Mainsystem clock oscillation
Prescaler
Clock peripheral hardware
Selector
Standby controller
Wait controller
clock (fCPU)
STOP Processor clock control register
PCC1
CSS0 Subclock control register
Internal
µPD789405, 789406, 789407
5.2.3 Clock generator control registers clock generator controlled using following registers. Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS)
Processor clock control register (PCC) selects clock specifies corresponding frequency division ratio. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input loads into PCC. Figure 5-8. Processor Clock Control Register Format
Symbol PCC1 Address FFFBH When reset
Operation enabled Operation disabled
Control main system clock oscillator operation
CSS0 PCC1
clock (fCPU) selectionNote (0.2
fX/2 (0.8 fXT/2
Note clock selected combination PCC1 flag processor clock control register (PCC) CSS0 flag subclock control register (CSS). (See Section 5.2.3.) Caution bits must fixed Remarks Main system clock oscillation frequency Subsystem clock oscillation frequency parenthesized values apply operation with 32.768 kHz. Minimum instruction execution time: fCPU fCPU fCPU fCPU
µPD789405, 789406, 789407
Suboscillation mode register (SCKM) SCKM selects feedback resistor subsystem clock, controls oscillation clock. subsystem clock manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears SCKM 00H. Figure 5-9. Suboscillation Mode Register Format
Symbol SCKM Address FFF0H When reset
Internal feedback resistor used Internal feedback resistor used
Feedback resistor selection
Operation enabled Operation disabled
Control subsystem clock oscillator operation
Caution Bits must fixed
µPD789405, 789406, 789407
Subclock control register (CSS) specifies whether main system subsystem clock oscillator selected. also specifies clock operates. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. Figure 5-10. Subclock Control Register Format
Address FFF2H When reset
CSS0
clock operation status Operation based output divided main system clock Operation based subsystem clock
CSS0
Selection main system subsystem clock oscillator Divided output from main system clock oscillator Output form subsystem clock oscillator
Caution Bits must fixed
µPD789405, 789406, 789407
16-Bit Timer/Counter
5.3.1 16-Bit timer/counter functions 16-bit timer/counter (TM5) following functions. Timer interrupt interrupt generated count matches comparison value. Timer output timer output controlled count matches comparison value. Count capture count captured into capture register synchronization with capture trigger. 5.3.2 16-bit timer/counter configuration 16-bit timer/counter (TM5) consists following hardware. Table 5-5. 16-Bit Timer/Counter Configuration
Item Timer register Register Timer output Control register bits (TM5) Compare register bits (CR50) Capture register bits (TCP5) (TO5) 16-bit timer mode control register (TMC5) Port mode register (PM2) Configuration
Figure 5-11. 16-Bit Timer/Counter Block Diagram
Internal 16-bit timer mode control register TOF5 CPT51CPT50 TOC5 TCL51TCL50 TOE5 output latch PM26
16-bit compare register (CR50) Match
Selector
TOD5 16-bit timer mode control register
TO5/INTP2 /P26
INTTM5 fX/2 CPT5/P27 /INTP3
16-bit timer register (TM5)
Edge detection circuit
16-bit capture register (TCP5)
16-bit counter read butter
Internal
µPD789405, 789406, 789407
16-bit compare register (CR50) value specified CR50 compared with count 16-bit timer register (TM5). they match, interrupt request (INTTM5) issued. CR50 using 8-bit 16-bit memory manipulation instruction. value from 0000H FFFFH set. RESET input loads FFFFH into CR50. Cautions CR50 designed manipulated using 16-bit memory manipulation instruction. also manipulated using 8-bit memory manipulation instructions, however. When 8-bit memory manipulation instruction used CR50, must direct addressing access mode. re-set CR50 during count operation, necessary disable interrupts advance, using interrupt mask flag register (MK1). also necessary disable inversion timer output data, using 16-bit timer mode control register (TMC5). 16-bit timer register (TM5) used count number pulses. contents read using 8-bit 16-bit memory manipulation instruction. RESET input clears 0000H. Cautions count becomes undefined when STOP mode deselected, because count operation performed before oscillation settles. designed manipulated using 16-bit memory manipulation instruction. also manipulated using 8-bit memory manipulation instructions, however. When 8-bit memory instruction used manipulate TM5, must direct addressing access mode. When 8-bit memory manipulation instruction used manipulate TM5, lower upper bytes must read pair, this order. 16-bit capture register (TCP5) TCP5 captures contents 16-bit timer (TM5). using 8-bit 16-bit memory manipulation instruction. RESET input makes TCP5 undefined. Caution TCP5 designed manipulated using 16-bit memory manipulation instruction. also manipulated using 8-bit memory manipulation instructions, however. When 8-bit memory manipulation instruction used manipulate TCP5, must direct addressing access mode. 16-bit counter read buffer This buffer used latch hold count 16-bit timer (TM5).
µPD789405, 789406, 789407
5.3.3 16-bit timer/counter control registers 16-bit timer/counter (TM5) controlled following registers. 16-bit timer mode control register (TMC5) Port mode register (PM2)
16-bit timer mode control register (TMC5) TMC5 controls count clock capture edge settings. TMC5 using 1-bit 8-bit memory manipulation instruction. RESET input clears TMC5 00H.
µPD789405, 789406, 789407
Figure 5-12. 16-Bit Timer Mode Control Register Format
Symbol TMC5 Address FF48H When reset R/WNote
TOD5 TOF5 CPT51 CPT50 TOC5 TCL51 TCL50 TOE5
TOD5 Causes 16-bit timer output data held.
TOF5 Reset cleared software when 16-bit timer overflows
Overflow flag control
CPT51 CPT50 Capture operation disabled
Capture edge selection
Captured rising edge CPT5 Captured falling edge CPT5 Captured both rising falling edges CPT5
TOC5 Inversion disabled Inversion enabled
Timer output data inversion control
TCL51 TCL50 fX/25 (5.0 MHz)Note
16-bit timer register count clock selection
(156.3 kHz)Note
Other settings
specified
TOE5 Output disabled (port mode) Output enabled
16-bit timer/counter output control
Notes read-only. count clock (TCL51 TCL50 capture function cannot used. read timer output, clock must main system clock high-speed mode (PCC1 CSS0 (See Figure 5-8.) read timer output, clock must main system clock (PCC1 CSS0 PCC1 CSS0 (See Figure 5-8.) Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
Port mode register (PM2) specifies whether each port used input output. P26/INTP2/TO5 timer output, PM26 output latches must reset using 1-bit 8-bit memory manipulation instruction. RESET input loads into PM2. Figure 5-13. Port Mode Register Format
Symbol Address FF22H When reset
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM26 Output mode (output buffer Input mode (output buffer OFF)
input/output mode selection
µPD789405, 789406, 789407
8-Bit Timer/Event Counter
5.4.1 8-bit timer/event counter functions Devices µPD789407 subseries have timer/event counters (TM0 TM1) timer counter (TM2). counter." 8-bit timer/event counters (TM0, TM1, TM2) have following functions. 8-bit interval timer This timer causes interrupts issued specified intervals. External event counter (TM0 TM1) This counter used count number pulses input from external source. Square wave output (TM2 only) square wave frequency output. Table 5-6. 8-Bit Timer/Event Counter Types Functions
Type Interval timer External event counter Function Timer output Interrupt request channel channel channel
Readers seeking description should read term "timer/event counter" "timer
5.4.2 8-bit timer/event counter configuration 8-bit timer/event counter consists following hardware. Table 5-7. 8-Bit Timer/Event Counter Configuration
Item Timer register Register Timer output Control register bits (TM0, TM1, TM2) Compare registers: bits (CR00, CR10, CR20) (TO2) 8-bit timer mode control registers (TMC0, TMC1, TMC2) Port mode register (PM2) Configuration
µPD789405, 789406, 789407
Figure 5-14. 8-Bit Timer/Event Counters (TM0 TM1) Block Diagram
Internal
8-bit compare register (CRn0) Match INTTMn
Selector
Count clockNote
8-bit timer register (TMn) Clear Selector
TCEn TCLn1 TCLn0
8-bit timer mode control register Internal
Note fX/26, fX/29, TI0/P24/INTP0 fX/2 fX/2 TI1/P25/INTP1 Remark
µPD789405, 789406, 789407
Figure 5-15. 8-Bit Timer Counter (TM2) Block Diagram
Internal
8-bit compare register (CR20) Match
output latch
PM23
INTTM2 fX/23
Selector
fX/27
8-bit timer register (TM2) Clear Selector
Selector
ComparatorNote
TO2/CMPTOUT0/
TCE2 TCL21 TCL20 TOE2
8-bit timer mode control register Internal Internal
Note Section details comparator. 8-bit compare register (CRn0) value specified CRn0 compared with count 8-bit timer register (TMn). they match, interrupt request (INTTMn) issued. CRn0 using 8-bit memory manipulation instruction. value from set. RESET input makes CRn0 undefined. Remark
8-bit timer register (TMn) used count number pulses. contents read using 8-bit memory manipulation instruction. RESET input clears 00H. Remark
µPD789405, 789406, 789407
5.4.3 8-bit timer/event counter control registers 8-bit timer/event counter controlled following registers. 8-bit timer mode control registers (TMC0, TMC1, TMC2) Port mode register (PM2) 8-bit timer mode control register (TMC0) TMC0 determines whether enable disable 8-bit timer register (TM0) specifies count clock TM0. TMC0 using 1-bit 8-bit memory manipulation instruction. RESET input clears TMC0 00H. Figure 5-16. 8-Bit Timer Mode Control Register Format
Symbol TMC0 TCE0 Address FF53H When reset
TCL01 TCL00
TCE0
8-bit timer register operation control Operation disabled (TM0 cleared Operation enabled
TCL01 TCL00 fX/26 (78.1 kHz) fX/29 (9.77 kHz) Rising edge Falling edge
8-bit timer register count clock selection
Caution Always stop timer before setting TMC0. Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
8-bit timer mode control register (TMC1) TMC1 determines whether enable disable 8-bit timer register (TM1) specifies count clock TM1. TMC1 using 1-bit 8-bit memory manipulation instruction. RESET input clears TMC1 00H. Figure 5-17. 8-Bit Timer Mode Control Register Format
Symbol TMC1 TCE1 Address FF57H When reset
TCL11 TCL10
TCE1
8-bit timer register operation control Operation disabled (TM1 cleared Operation enabled
TCL11 TCL10 fX/24 (312.5 kHz) fX/28 (19.5 kHz) Rising edge Falling edge
8-bit timer register count clock selection
Caution Always stop timer before setting TMC1. Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
8-bit timer mode control register (TMC2) TMC2 determines whether enable disable 8-bit timer register (TM2) specifies count clock TM2. also controls operation output control circuit 8-bit timer counter TMC2 using 1-bit 8-bit memory manipulation instruction. RESET input clears TMC2 00H. Figure 5-18. 8-Bit Timer Mode Control Register Format
Symbol TMC2 TCE2 Address FF5BH When reset
TCL21 TCL20 TOE2
TOE2 Output disabled (port mode) Output enabled
8-bit timer counter output control
TCL21 TCL20 fX/23 (625 kHz) fX/27 (39.1 kHz) specified
8-bit timer register count clock selection
TCE2
8-bit timer register operation control Operation disabled (TM2 cleared Operation enabled
Caution Always stop timer before setting TMC2. Remarks Main system clock oscillation frequency Subsystem clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
Port mode register (PM2) specifies whether each port used input output. P23/CMPTOUT0/TO2 timer output, PM23 output latches must reset using 1-bit 8-bit memory manipulation instruction. RESET input loads into PM2. Figure 5-19. Port Mode Register Format
Symbol Address FF22H When reset
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM23 Output mode (output buffer Input mode (output buffer OFF)
input/output mode selection
µPD789405, 789406, 789407
Clock Timer
5.5.1 Clock timer functions clock timer following functions. Clock timer Interval timer
clock interval timers used same time. Figure 5-20 block diagram clock timer. Figure 5-20. Clock Timer Block Diagram
Clear Selecter fX/2
9-bit prescaler Selecter
5-bit counter Clear
INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4 Clock timer mode control register (WTM) Internal
WTM1 WTM0
µPD789405, 789406, 789407
Clock timer main system subsystem clock used issue interrupt request (INTWT) 0.5-second intervals. Caution When main system clock operating MHz, cannot used generate 0.5-second interval. this case, subsystem clock, which operates 32.768 kHz, should used instead. Interval timer interval timer used generate interrupt request (INTWT) specified intervals. Table 5-8. Interval Generated Using Interval Timer
Interval 1/fX
Operation 409.6 819.2 1.64 3.28 6.55 13.1
Operation 4.19 1.96 3.91 7.82 15.6
Operation 32.768 1.95 3.91 7.81 15.6
1/fX
1/fX 1/fX
1/fX
1/fX
Remark
Main system clock oscillation frequency Subsystem clock oscillation frequency
5.5.2 Clock timer configuration clock timer consists following hardware. Table 5-9. Clock Timer Configuration
Item Counter Prescaler Control register bits bits Clock timer mode control register (WTM) Configuration
µPD789405, 789406, 789407
5.5.3 Register controlling clock timer clock timer mode control register (WTM) used control clock timer. Clock timer mode control register (WTM) Wselects count clock clock timer specifies whether enable clocking timer. also specifies prescaler interval 5-bit counter controlled. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. Figure 5-21. Clock Timer Mode Control Register Format
Symbol Address FF4AH When reset
WWTM7 WTM6 WTM5 WTM4
WTM1 WTM0
WTM7 fX/27 (39.1 kHz) (32.768 kHz)
Clock timer count clock selection
WTM6 WTM5 WTM4 24/fW (488 25/fW (977 26/fW (1.95 27/fW (3.91 28/fW (7.81 29/fW (15.6
Prescaler interval selection
Other settings
WTM1 Cleared after stop Started
Control 5-bit counter operation
WTM0
Clock timer operation Operation disabled (both prescaler timer cleared) Operation enabled
Remarks Clock timer clock frequency (fX/27 fXT) Main system clock oscillation frequency Subsystem clock oscillation frequency parenthesized values apply operation 32.768 kHz.
µPD789405, 789406, 789407
Watchdog Timer
5.6.1 Watchdog timer functions watchdog timer following functions. Watchdog timer watchdog timer used detect unintended program loops. unintended program loop detected, nonmaskable interrupt RESET signal generated. Interval timer interval timer used generate interrupts specified intervals. 5.6.2 Watchdog timer configuration watchdog timer consists following hardware. Table 5-10. Watchdog Timer Configuration
Item Control register Timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Configuration
µPD789405, 789406, 789407
Figure 5-22. Watchdog Timer Block Diagram
Internal
Prescaler Clear TMIF4 Control circuit
TMMK4 INTWDT maskable interrupt request RESET INTWDT nonmaskable interrupt request
Selector
7-bit counter
TCL22 TCL21 TCL20 Timer clock selection register Internal
WDTM4 WDTM3 Watchdog timer mode register
µPD789405, 789406, 789407
5.6.3 Watchdog timer control registers watchdog timer controlled following registers. Timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Timer clock selection register (TCL2) TCL2 specifies count clock watchdog timer. TCL2 using 8-bit memory manipulation instruction. RESET input clears TCL2 00H. Figure 5-23. Timer Clock Selection Register Format
Symbol TCL2 Address FF42H When reset
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog timer count clock selection fX/24 (312.5 kHz) fX/26 (78.1 kHz) fX/28 (19.5 kHz) fX/210 (4.88 kHz) specified 211/fX (410 213/fX (1.64 215/fX (6.55 217/fX (26.2
Interval time
Other settings
Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
Watchdog timer mode register (WDTM) WDspecifies watchdog timer operation mode whether enable disable counting. WDis using 1-bit 8-bit memory manipulation instruction. RESET input clears WDto 00H. Figure 5-24. Watchdog Timer Mode Register Format
Symbol Address FFF9H When reset
WDTM4 WDTM3
Stops counting.
Watchdog timer operation selectionNote
Clears counter causes start.
WDTM4 WDTM3 Operation disabled
Watchdog timer operation mode selectionNote
Internal timer mode (When overflow occurs, maskable interrupt issued.)Note Watchdog timer mode (When overflow occurs, nonmaskable interrupt issued.) Watchdog timer mode (When overflow occurs, reset operation started.)
Notes Once been (1), impossible zero-clear software. once counting begins, cannot stopped means other than RESET input. Once WDTM3 WDTM4 have been (1), impossible zero-clear them software. interval timer starts operating when Cautions watchdog timer cleared, actual overflow time becomes (maximum) less than time specified timer clock selection register watchdog timer mode ensure that interrupt request flag (TMIF4) before setting WDTM4 TMIF4 selecting mode causes nonmaskable interrupt issued instant rewriting ends, while selecting mode causes reset operation started when rewriting ends.
µPD789405, 789406, 789407
8-Bit Converter
5.7.1 8-bit converter functions 8-bit converter converts input analog voltages digital signals with 8-bit resolution. control seven analog input channels (ANI0 ANI6). conversion started only software. analog inputs ANI0 ANI6 selected conversion. conversion performed repeatedly, with interrupt request (INTAD) being issued each time session completed. 5.7.2 Configuration 8-bit converter converter consists following hardware. Table 5-11. 8-Bit Converter Configuration
Item Analog input Register channels (ANI0 ANI6) Successive approximation register (SAR) conversion result register (ADCRH) Control register converter mode register (ADM) input selection register (ADS) Configuration
µPD789405, 789406, 789407
Figure 5-25. Converter Block Diagram
Voltage comparator
AVSS Successive approximation register (SAR)
selector
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6
Sample-and-hold circuit
Selector
AVDD AVREF
AVSS
Control circuit
INTAD
conversion result register (ADCRH)
ADS2 ADS1 ADS0
ADCS
input selection register Internal
conveter mode register
Successive approximation register (SAR) receives result comparing analog input voltage voltage voltage (comparison voltage), received from serial resistor string, starting from most significant (MSB). Upon receiving bits, down least significant (LSB), that upon completion conversion, sends contents conversion result register. conversion result register (ADCRH) ADCRH holds result conversion. Each time conversion ends, conversion result received from successive approximation register loaded into ADCRH. ADCRH manipulated using 8-bit memory manipulation instruction. RESET input clears ADCRH 00H. Sample-and-hold circuit sample-and-hold circuit samples consecutive analog inputs from input circuit, one, sends them voltage comparator. sampled analog input voltage held during conversion. Voltage comparator voltage comparator compares analog input with voltage output serial resistor string. Serial resistor string serial resistor string configured between AVREF AVSS. generates reference voltages against which analog inputs compared.
µPD789405, 789406, 789407
ANI0 ANI6 pins Pins ANI0 ANI6 analog input pins converter. They used receive analog signals subject conversion. Caution supply pins ANI0 ANI6 with voltages that fall outside rated range. voltage greater than AVDD less than AVSS (even within absolute maximum rating) supplied these pins, conversion value corresponding channel will undefined. Furthermore, conversion values other channels also affected. AVREF AVREF reference voltage converter. Signals received pins ANI0 ANI6 converted digital signals while referencing voltage across AVREF AVSS pins. AVSS AVSS ground potential converter. This must held same potential VSS0 pin, even while converter being used. AVDD AVDD analog power supply converter. This must held same potential VDD0 pin, even while converter being used.
µPD789405, 789406, 789407
5.7.3 8-bit converter control registers following registers used control 8-bit converter. converter mode register (ADM) input selection register (ADS)
converter mode register (ADM) specifies conversion time analog inputs. also specifies whether enable conversion. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. Figure 5-26. Converter Mode Register Format
Symbol ADCS Address FF80H When reset
ADCS Conversion disabled Conversion enabled
conversion control
144/fx 120/fx 96/fx 72/fx 60/fx 48/fx (28.8 (19.2 (14.4
conversion time selectionNote
(not setNote (not setNote
Other settings
Notes specifications FR2, FR1, must such that conversion time least These combinations must used, conversion time will fall below Caution result conversion performed immediately after (ADCS) undefined. Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
input selection register (ADS) register specifies port used input analog voltages converted digital signal. manipulated using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. Figure 5-27. Input Selection Register Format
Symbol Address FF84H When reset
ADS2 ADS1 ADS0
ADS2 ADS1 ADS0 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6
Analog input channel specification
µPD789405, 789406, 789407
Comparator
5.8.1 Comparator functions comparator following functions. Input voltage comparison comparator compares input voltage reference voltage input (CMPREF0) with input voltage comparator input (CMPIN0). instructions. Interrupt generation comparator output (selectable with rising and/or falling edge) used generate interrupt request signal (INTCMP). Clock output When CMPREF0 CMPIN0, output 8-bit timer counter (TM2) directed CMPTOUT0 pin. Open-drain output selection comparator mode register (CMPRM0) used specify port open-drain output. 5.8.2 Comparator configuration comparator consists following hardware. CMPIN0 This comparator input pin. CMPTOUT0 This comparator output pin. CMPREF0 This comparator reference voltage input pin. Figure 5-28 block diagram comparator. comparison result read using memory manipulation
µPD789405, 789406, 789407
Figure 5-28. Comparator Block Diagram
Internal
output latch
PM23
CMPIN0 CMPREF0
Timing control
Selector
8-bit timer (TM2) output
CMPTOUT0/P23 /TO2
INTCMP
CMPON
SELCMP
OPDR
CMPOUT
Comparator mode register Internal
µPD789405, 789406, 789407
5.8.3 Comparator control register comparator controlled following register. Comparator mode register (CMPRM0) CMPRM0 controls power supply output comparator. also selects open drain output comparator. CMPRM0 using 1-bit 8-bit memory manipulation instruction. RESET input clears CMPRM0 00H. Figure 5-29. Comparator Mode Register Format
Symbol CMPRM0 Address FF4EH When reset R/WNote
CMPON SELCMP OPDR CMPOUT
CMPON Comparator power supply Comparator power supply
Comparator power supply ON/OFF control
SELCMP 8-bit timer counter (TM2) output
Clock output control
8-bit timer counter (TM2) output CMPREF0 CMPIN0
OPDR CMOS output Open-drain output
Open-drain output selection
CMPOUT comparator output read.
Note read-only. Cautions Bits must fixed comparator enabled, noise induced. necessary generate interrupt request signal (INTCMP) from output comparator, enable comparator before enabling interrupts. Similarly, necessary direct output comparator port, enable comparator advance.
µPD789405, 789406, 789407
Serial Interface Channel
5.9.1 Functions serial interface channel Serial interface channel following three modes. Operation stopped mode Asynchronous serial interface (UART) mode Three-wire serial mode Operation stopped mode This mode used when serial transfer performed. Power consumption minimized this mode. Asynchronous serial interface (UART) mode This mode used send receive byte data that follows start bit. supports full-duplex communication. Serial interface channel contains dedicated UART baud rate generator, enabling communication over wide range baud rates. also possible define baud rates dividing frequency input clock pulse ASCK pin. Three-wire serial mode (switchable between MSB-first LSB-first transmission) This mode used transmit 8-bit data, using three lines: serial clock (SCK) line serial data lines SO). supports simultaneous transmission reception, three-wire serial mode requires less processing time data transmission than asynchronous serial interface mode. Because, three-wire serial mode, possible select whether 8-bit data transmission begins with LSB, channel connected device regardless whether that device designed MSBfirst LSB-first transmission. Three-wire serial mode useful connecting peripheral circuits display controllers having conventional clock synchronous serial interfaces, such those 75X/XL, 78K, series devices. 5.9.2 Serial interface channel configuration Serial interface channel consists following hardware. Table 5-12. Serial Interface Channel Configuration
Item Register Transmission shift register (TXS) Reception shift register (RXS) Reception buffer register (RXB) Control register Serial operation mode register (CSIM0) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Configuration
Figure 5-30. Serial Interface Channel Block Diagram
Internal Asynchronous serial interface status register Direction control circuit Asynchronous serial interface mode register Direction control circuit Transmission shift register (TXS/SIO0) Reception control circuit INTSR/INTCSI0 Transmission control circuit output control circuit INTST Note Baud rate generator fX/2-fX/28 CSIE0 CSIE0 DIR0 CSCK CSCK TPS3 TPS2 TPS1 TPS0 Baud rate generator control register Internal
Reception buffer register (RXB/SIO0)
RxD/SI/P22
Reception shift register (RXS)
TxD/SO/P21
PM21
PM20
ASCK/SCK/P20
Serial operation mode register
µPD789405, 789406, 789407
Note Figure 5-31 configuration baud rate generator.
Figure 5-31. Baud Rate Generator Block Diagram
Stop Prescaler fX/25 fX/2 CSIE0
BRGC write
Clear Clear
Selector
Transmission clock 3-bit counter
ASCK/SCK/P20
Selector
Reception clock
Selector
3-bit counter Clear
CSCK CSIE0
Clear
CSIE0
Start detection BRGC write TPS3 TPS2 TPS1 Baud rate generator control register Internal TPS0
µPD789405, 789406, 789407
µPD789405, 789406, 789407
Transmission shift register (TXS) register which transmission data prepared. transmission data output from bit-serially. When data length seven bits, bits data will transmission data. Writing data triggers transmission. write-accessed, using 8-bit memory manipulation instruction, cannot read-accessed. RESET input loads into TXS. Caution write during transmission. reception buffer register (RXB) mapped same address, such that attempt read from results value being read from RXB. Reception shift register (RXS) register which serial data, received pin, converted parallel data. Once entire byte been received, feeds reception data reception buffer register (RXB). cannot manipulated directly program. Reception buffer register (RXB) used hold reception data. Once received entire byte data, feeds that data into RXB. When data length seven bits, reception data sent bits RXB, which fixed read-accessed, using 8-bit memory manipulation instruction, cannot write-accessed. RESET input makes undefined. Caution transmission shift register (TXS) mapped same address, such that attempt write results value being written TXS. Transmission control circuit transmission control circuit controls transmission. example, adds start, parity, stop bits data transmission shift register (TXS), according setting asynchronous serial interface mode register (ASIM). Reception control circuit reception control circuit controls reception according setting asynchronous serial interface mode register (ASIM). also checks errors, such parity errors, during reception. error detected, asynchronous serial interface status register (ASIS) according status error.
µPD789405, 789406, 789407
5.9.3 Serial interface channel control registers Serial interface channel controlled following registers. Serial operation mode register (CSIM0) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Serial operation mode register (CSIM0) CSIM0 used make settings related three-wire serial mode. CSIM0 using 1-bit 8-bit memory manipulation instruction. RESET input clears CSIM0 00H. Figure 5-32. Serial Operation Mode Register Format
Symbol Address FF72H When reset
CSIM0 CSIE0
DIR0 CSCK
CSIE0 Operation disabled Operation enabled
Three-wire serial mode operation control
DIR0
First-bit specification
CSCK
Three-wire serial mode clock selection External clock pulse input SCK0 Output dedicated baud rate generator
Cautions bits must fixed CSIM0 must cleared 00H, UART mode selected.
µPD789405, 789406, 789407
Asynchronous serial interface mode register (ASIM) ASIM used make settings related asynchronous serial interface mode. ASIM using 1-bit 8-bit memory manipulation instruction. RESET input clears ASIM 00H. Figure 5-33. Asynchronous Serial Interface Mode Register Format
Symbol ASIM Address FF70H When reset
Transmission disabled Transmission enabled
Transmission control
Reception disabled Reception enabled
Reception control
parity
Parity specification
transmission, parity fixed reception, parity check made; parity error reported.
parity Even parity
bits bits
Character length specification
bits
Transmission data stop length
Cautions Bits must fixed three-wire serial mode selected, ASIM must cleared 00H. Before switching from mode another, stop both serial transmission reception.
µPD789405, 789406, 789407
Table 5-13. Serial Interface Channel Operation Mode Settings Operation stopped mode
ASIM
CSIM0
PM22 PM21 PM20
CSIE0 DIR0 CSCK
First
Shift clock
P22/SI/RxD function
P21/SO/TxD function
P20/SCK/ ASCK function
Note
Note
Note
Note
Note
Note
Other settings
specified
Three-wire serial mode
ASIM
CSIM0
PM22 PM21 PM20
CSIE0 DIR0 CSCK
First
Shift clock
P22/SI/RxD function
P21/SO/TxD function
P20/SCK/ ASCK function
1Note
External SI0Note2 clock
(CMOS output)
SCK0 input
Internal clock
SCK0 output SCK0 input SCK0 output
External clock
Internal clock
Other settings
specified
Asynchronous serial interface mode
ASIM
CSIM0
PM22 PM21 PM20
CSIE0 DIR0 CSCK
First
Shift clock
P22/SI/RxD function
P21/SO/TxD function
P20/SCK/ ASCK function
Note
Note
External clock
(CMOS output)
ASCK input
Note
Note
Note
Internal clock
Note
Note
External clock
ASCK input
Note
Internal clock
External clock
(CMOS output)
ASCK input
Note
Note
Internal clock
Other settings
specified
Notes
These pins used port functions. When only transmission used, these pins used (CMOS input/output).
Remark Don't care.
µPD789405, 789406, 789407
Asynchronous serial interface status register (ASIS) ASIS used display type reception error, occurs while asynchronous serial interface mode set. ASIS using 8-bit memory manipulation instruction. contents ASIS undefined three-wire serial mode. RESET input clears ASIS 00H. Figure 5-34. Asynchronous Serial Interface Status Register Format
Symbol ASIS Address FF71H When reset
parity error occurred.
Parity error flag
parity error occurred (parity mismatch transmission data).
framing error occurred.
Framing error flag
framing error occurred stop detected).Note
overrun error occurred.
Overrun error flag
overrun error occurred.Note (Before data read from reception buffer register, subsequent reception sequence completed.)
Notes
Even specified number stop bits (using (SL) ASIM), only stop detected reception. After overrun occurs, read-access reception buffer register (RXB). Otherwise, overrun error will recur each time data received.
µPD789405, 789406, 789407
Baud rate generator control register (BRGC) BRGC used specify serial clock serial interface channel BRGC using 8-bit memory manipulation instruction. RESET input clears BRGC 00H. Figure 5-35. Baud Rate Generator Control Register Format
Symbol BRGC Address FF73H When reset
TPS3 TPS2 TPS1 TPS0
TPS3 TPS2 TPS1 TPS0 fX/2 fX/22 (2.5 MHz) (1.25 MHz)
3-bit counter source clock selection
fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz)
fX/27 (39.1 kHz) fX/28 (19.5 kHz) External clock pulse input ASCK pinNote specified
Other settings
Note external clock used only UART mode. Cautions attempt write BRGC during communication adversely affects output baud rate generator, thus hampering normal operation. BRGC during communication. select during operation MHz, causes rated baud rate exceeded. Remarks Main system clock oscillation frequency Value specified TPS0 TPS3 parenthesized values apply operation MHz. Therefore, write
µPD789405, 789406, 789407
transmission reception clock pulses used generate baud rate obtained dividing frequency main system clock pulse signal input ASCK pin. Generating transmission reception clock pulses baud rates based main system clock frequency main system clock divided generate transmission reception clock pulses. baud rate generated based main system clock determined using following expression. [Baud rate] [Hz]
Main system clock oscillation frequency Value specified TPS0 TPS3 Table 5-14. Relationships between Main System Clock Frequencies Baud Rates (Example)
Baud rate (bps) Error BRGC setting 1.73 4.9152
µPD789405, 789406, 789407
Generating transmission reception clock pulses baud rates based external clock pulse received ASCK frequency external clock pulse received ASCK used generate transmission reception clock pulses. baud rate generated based external clock pulse received ASCK determined using following expression. [Baud rate] fASCK [Hz]
fASCK: Frequency clock pulse received ASCK Table 5-15. Relationships between ASCK Input Frequencies Baud Rates (When BRGC 80H)
Baud rate (bps) ASCK input frequency (kHz) 19.2 38.4 76.8 153.6 307.2 500.0 614.4
µPD789405, 789406, 789407
5.10 Controller/Driver
5.10.1 controller/driver functions functions controller/driver µPD789405, µPD789406, µPD789407 follows: Automatic output segment common signals based automatic display data memory read Five different display modes: Static duty (1/2 bias) duty (1/2 bias) duty (1/3 bias) duty (1/3 bias)
Four different frame frequencies, selectable each display mode segment signal outputs S27) four common signal outputs (COM0 COM3) these segment signal outputs, outputs switched input/output ports 2-output units (P80/S27 P87/S20 P90/S19 P93/S16). Voltage divider resistors (for drive voltage generation) that port itself contain specified with mask option Operation with subsystem clock Table 5-16 lists maximum number pixels that displayed each display mode. Table 5-16. Maximum Number Pixels
Common signals used COM0 (COM1-COM3) COM0, COM1 COM0-COM2 COM0-COM2 COM0-COM3 segment signals, common signals)
Note
Bias mode
Number time slices Static
Maximum number pixels segment signals, common signal)
Note Note Note
segment signals, common signals) segment signals, common signals)
Notes Three-digit panel, each digit having 8-segment Seven-digit panel, each digit having 4-segment Nine-digit panel, each digit having 3-segment Fourteen-digit panel, each digit having 2-segment
configuration. configuration. configuration. configuration.
µPD789405, 789406, 789407
5.10.2 controller/driver configuration controller/driver consists following hardware. Table 5-17. Controller/Driver Configuration
Item Display output Configuration segment signals dedicated segment signals segment input/output port signals) common signals (COM0 COM3) Control register display mode register (LCDM) port selector (LPS) clock control register (LCDC)
Selector
Figure 5-36. Controller/Driver Block Diagram
display mode register (LCDH) Display data memory 76543210 76543210 Output latch Output latch Internal port selector (LPS) Segment selector fLCD Timing controller LCDON 3210 Selector LCDON 3210 Selector LCDON 3210 Selector Common driver output buffer Segment driver output buffer Segment driver Segment driver
clock control register (LCDC)
LCDC3 LCDC2 LCDC1 LCDC0
LCDON VAON LEPS LIPS LCDM2 LCDM1 LCDM0 LPS5 LCS4 LPS3 LPS2 LPS1 LPS0
fX/27
Prescaler
fLCD
fLCD
fLCD
fLCD
clock selector
drive voltage controller
µPD789405, 789406, 789407
VLC2 VLC1 VLC0 BIAS COM0 COM1 COM2 COM3
µPD789405, 789406, 789407
5.10.3 controller/driver control registers following three types registers used control controller/driver. display mode register (LCDM) port selector (LPS) clock control register (LCDC)
display mode register (LCDM) LCDM specifies whether enable display operation. also specifies operation mode, drive power supply, display mode. LCDM manipulated using 1-bit 8-bit memory manipulation instruction. RESET clears LCDM 00H. Figure 5-37. Display Mode Register Format
Symbol LCDM LIPS Address FFB0H When reset
LCDON VAON
LCDM2 LCDM1 LCDM0
LCDON
Control display Display (All segment outputs deselected.) Display
VAON Normal operation Low-voltage operation
controller/driver operation modeNote
LIPS drive power supplied.
drive power supply selection
drive power supplied BIAS pin.
LCDM2 LCDM1 LCDM0
controller/driver display mode selection Number time slices Bias mode
Static
Other settings
Note When display panel used, VAON must fixed conserve power. Before manipulating VAON, turn display.
µPD789405, 789406, 789407
port selector (LPS) controls port segment signal output switching. manipulated using 1-bit 8-bit memory manipulation instruction. RESET clears 00H. Figure 5-38. Port Selector Format
Symbol Address FFB1H When reset
LPS5 LPS4 LPS3 LPS2 LPS1 LPS0
LPS5
LPS4
LPS3
LPS2
LPS1
LPS0
P93/S16, P92/S17 P91/S18, P90/S19 P87/S20, P86/S21 P85/S22, P84/S23 P83/S24, P82/S25 P81/S26, P80/S27 Used ports (Pmn) Used segments (Sx)
Remark
µPD789405, 789406, 789407
clock control register (LCDC) LCDC specifies clock frame frequency. LCDC manipulated using 1-bit 8-bit memory manipulation instruction. RESET clears LCDC 00H. Figure 5-39. Clock Control Register Format
Symbol LCDC Address FFB2H When reset
LCDC3 LCDC2 LCDC1 LCDC0
LCDC3 LCDC2 fX/27
clock (fLCD) selectionNote
LCDC1 LCDC0 fLCD/26 fLCD/27 fLCD/28 fLCD/29
frame frequency selection
Note Specify clock (fLCD) frequency least kHz. Table 5-18 lists frame frequencies used when (32.768 kHz) supplied clock (fLCD). Table 5-18. Frame Frequencies (Hz)
Frame frequency Display duty ratio Static fXT/2
fXT/2
fXT/2
fXT/2
(128
(256
(512
Remark
parenthesized values apply when (32.768 kHz) supplied clock (fLCD).
µPD789405, 789406, 789407
INTERRUPT FUNCTIONS
Interrupt Function Types
types interrupt function supported. Nonmaskable interrupt nonmaskable interrupt request accepted unconditionally, that even when interrupts disabled. nonmaskable interrupt takes precedence over other interrupts; subjected interrupt priority control. nonmaskable interrupt causes standby release signal generated. µPD789405, µPD789406, µPD789407 support nonmaskable interrupt namely, watchdog timer interrupt. Maskable interrupt Maskable interrupts those which subjected mask control. more maskable interrupts occur simultaneously, default priority listed Table applies. maskable interrupts cause standby release signal generated. maskable interrupts supported µPD789405, µPD789406, µPD789407 include external interrupts internal interrupts.
Interrupt Sources Configuration
µPD789405, µPD789406, µPD789407 each support total maskable nonmaskable interrupt sources. (See Table 6-1.)
µPD789405, 789406, 789407
Table 6-1. Interrupt Sources
Interrupt type
Default priority
Note
Interrupt source
Vector Internal/external table address Internal 0004H
Basic configuration typeNote
Name Nonmaskable interrupt INTWDT
Trigger Watchdog timer overflow (when watchdog timer mode selected)
Maskable
INTWDT
Watchdog timer overflow (when interval timer mode selected)
INTP0 INTP1 INTP2 INTP3 INTSR
input edge detection
External
0006H 0008H 000AH 000CH
UART reception serial interface channel
Internal
000EH
INTCSI0
three-wire transfer reception serial interface channel
INTST
UART transmission serial interface channel
0010H
INTWT INTWTI INTTM0
Clock timer interrupt Interval timer interrupt Generation match signal 8-bit timer/event counter
0012H 0014H 0016H
INTTM1
Generation match signal 8-bit timer/event counter
0018H
INTTM2
Generation match signal 8-bit timer counter
001AH
INTTM5
Generation match signal 16bit timer counter
001CH
INTKR INTAD INTCMP
return signal detection conversion completion signal Comparator signal
001EH 0020H 0022H
Notes default priority regulates which maskable interrupt higher, when more maskable interrupts requested simultaneously. Zero signifies highest priority, while lowest. Basic configuration types (A), (B), correspond (A), (B), Figure 6-1, respectively.
µPD789405, 789406, 789407
Figure 6-1. Basic Configuration Interrupt Functions Internal nonmaskable interrupt
Internal
Interrupt request
Vector table address generation circuit
Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Vector table address generation circuit
Standby release signal
External maskable interrupt
Internal
External interrupt mode register (INTM)
Interrupt request
Edge detection circuit
Vector table address generation circuit
Standby release signal
Interrupt request flag Interrupt enable flag Interrupt mask flag
µPD789405, 789406, 789407
Interrupt Function Control Registers
interrupt functions controlled following registers. Interrupt request flag registers (IF0 IF1) Interrupt mask flag registers (MK0 MK1) External interrupt mode registers (INTM0 INTM1) Program status word (PSW) return mode register (KRM) Table lists interrupt requests, corresponding interrupt request flags, interrupt mask flags. Table 6-2. Interrupt Request Signals Corresponding Flags
Interrupt request signal INTWDT INTP0 INTP1 INTP2 INTP3 INTSR/INTCSI0 INTST INTWT INTWTI INTTM0 INTTM1 INTTM2 INTTM5 INTKR INTAD INTCMP TMIF4 PIF0 PIF1 PIF2 PIF3 SRIF STIF WTIF WTIFI TMIF0 TMIF1 TMIF2 TMIF5 KRIF ADIF CMPIF Interrupt request flag TMMK4 PMK0 PMK1 PMK2 PMK3 SRMK STMK WTMK WTMKI TMMK0 TMMK1 TMMK2 TMMK5 KRMK ADMK CMPMK Interrupt mask flag
µPD789405, 789406, 789407
Interrupt request flag registers (IF0 IF1) interrupt request flag (1), when corresponding interrupt request issued, when related instruction executed. cleared (0), when interrupt request accepted, when RESET signal input, when related instruction executed. using 1-bit 8-bit memory manipulation instruction. RESET input clears 00H. Figure 6-2. Interrupt Request Flag Register Format
Symbol PIF3 PIF2 PIF1 Address FFE0H When reset
WTIF STIF SRIF
PIF0 TMIF4
CMPIF ADIF KRIF TMIF5 TMIF2 TMIF1 TMIF0 WTIFI
FFE1H
XXIFX
Interrupt request flag interrupt request signal been issued. interrupt request signal been issued; interrupt request been made.
Cautions TMIF4 flag read- write-accessed only when watchdog timer being used interval timer. watchdog timer mode When port being used output port, output level changed, interrupt request flag set, because this port also used external interrupt input. port output mode, therefore, interrupt mask flag must advance. must cleared watchdog timer used
µPD789405, 789406, 789407
Interrupt mask flag registers (MK0 MK1) interrupt mask flags used enable disable corresponding maskable interrupts. using 1-bit 8-bit memory manipulation instruction. RESET input loads into MK1. Figure 6-3. Interrupt Mask Flag Register Format
Symbol Address FFE4H When reset
WTMK STMK SRMK PMK3 PMK2 PMK1 PMK0 TMMK4
CMPMK ADMK KRMK TMMK5 TMMK2 TMMK1 TMMK0 WTMKI
FFE5H
XXMKX Enable interrupt handling. Disable interrupt handling.
Interrupt handling control
Cautions When watchdog timer being used watchdog timer mode attempt read TMMK4 flag results undefined value being detected. When port being used output port, output level changed, interrupt request flag set, because this port also used external interrupt input. port output mode, therefore, interrupt mask flag must advance.
µPD789405, 789406, 789407
External interrupt mode register (INTM0) INTM0 used specify effective edge INTP0 INTP2. INTM0 using 8-bit memory manipulation instruction. RESET input clears INTM0 00H. Figure 6-4. External Interrupt Mode Register Format
Symbol INTM0 Address FFECH When reset
ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20 Falling edge Rising edge specified Both rising falling edges
INTP2 effective edge selection
ES11 ES10 Falling edge Rising edge specified Both rising falling edges
INTP1 effective edge selection
ES01 ES00 Falling edge Rising edge specified Both rising falling edges
INTP0 effective edge selection
Cautions Bits must fixed Before setting INTM0, corresponding interrupt mask flag register disable interrupts. enable interrupts, clear corresponding interrupt request flag, then corresponding interrupt mask flag register.
µPD789405, 789406, 789407
External interrupt mode register (INTM1) INTM1 used specify effective edge INTP3 INTCMP. INTM1 using 8-bit memory manipulation instruction. RESET input clears INTM1 00H. Figure 6-5. External Interrupt Mode Register Format
Symbol INTM1 Address FFEDH When reset
ES61 ES60
ES31 ES30
ES61 ES60 Falling edge Rising edge specified Both rising falling edges
INTCMP effective edge selection
ES31
Falling edge Rising edge specified Both rising falling edges
INTP3 effective edge selection
Cautions Bits must fixed Before setting INTM1, corresponding interrupt mask flag register disable interrupts. enable interrupts, clear corresponding interrupt request flag, then corresponding interrupt mask flag register.
µPD789405, 789406, 789407
Program status word (PSW) program status word used hold instruction execution result current status interrupt requests. flag, used enable disable maskable interrupts, mapped PSW. read- write-accessed 8-bit units, well 1-bit units when using manipulation instructions dedicated instructions DI). RESET input loads into PSW. Figure 6-6. Program Status Word Configuration
Symbol When reset
When vector interrupt accepted,
automatically saved stack, flag reset (0).
Used execution ordinary instructions Disable Enable Whether enable/disable interrupt acceptance
return mode register (KRM) used specify which return signal detected. using 1-bit 8-bit memory manipulation instruction. (KRM0) 4-bit units KR0/P40 KR3/P43 pins. Bits (KRM4 KRM5) 1-bit units KR4/P44 KR5/P45 pins, respectively. RESET input clears 00H. Figure 6-7. Return Mode Register Format
Symbol KRM0 Address FFF5H When reset
KRM5 KRM4
KRMn Undetected
return signal detection selection
Detected falling edge port
Cautions Bits must fixed When (1), corresponding output connected pull-up resistor unless output mode. output mode, pull-up resistor connected. Before setting KRM, (KRMK disable interrupts. enable interrupts, clear (KRIF then (KRMK
µPD789405, 789406, 789407
Figure 6-8. Falling Edge Detection Circuit
return mode register (KRM) Note P40/KR0 P41/KR1 P42/KR2 P43/KR3 P44/KR4 P45/KR5 KRMK
Selector
Falling edge detection circuit
KRIF signal
Standby release signal
Note Selector used select used falling edge input
µPD789405, 789406, 789407
STANDBY FUNCTION Standby Function
standby function supported minimize system's power consumption. There standby modes: HALT STOP. HALT STOP modes selected using HALT STOP instructions, respectively. HALT mode HALT mode, clock stopped. average power consumption. STOP mode STOP mode, main system clock stopped. result, main system clock-based operation also stopped, thus minimizing power consumption. Caution Before shifting STOP mode, first stop operation hardware, then execute STOP instruction. Interleaving normal mode with HALT mode reduce
µPD789405, 789406, 789407
Table 7-1. Operation Statuses HALT Mode
HALT mode operation status while main system clock running Item While subsystem clock running Clock generator Port (output latch) 16-bit timer counter (TM5) 8-bit timer/event counter (TM0 TM1) 8-bit timer counter (TM2) Clock timer Watchdog timer Serial interface converter controller/driver Comparator External interrupt Operation enabled Operation enabled Operation enabled Operation enabled Operation disabled Operation enabled Operation enabled Operation enabled
Note Note
HALT mode operation status while subsystem clock running
While subsystem clock running
While main system clock running
While main system clock running Does run.
operate with main system clock. Does run. Remains state existing before selection HALT mode. Operation enabled
Does run.
Operation enabled
Note Note
Does run.
Note Note
Operation enabled Operation enabled
Operation enabled Operation enabled
Operation enabled Operation enabled
Operation disabled Operation enabled
Note
Operation enabled
Note
Operation enabled
Operation enabled
Note
Notes Operation enabled while main system clock selected. Operation enabled while subsystem clock selected. Operation enabled both three-wire serial UART modes while external clock being used. Operation enabled while operating, external interrupt. Maskable interrupt that masked
µPD789405, 789406, 789407
Table 7-2. Operation Statuses Stop Mode
STOP mode operation status while main system clock running While subsystem clock running Clock generator Port (output latch) 16-bit timer counter (TM5) 8-bit timer/event counter (TM0 TM1) 8-bit timer counter (TM2) Clock timer Watchdog timer Serial interface converter controller/driver Comparator External interrupt Operation enabled Operation enabled Does run. Operation enabled Does run. Operation enabled Operation enabled Operation enabled
Note Notes Note Note Note Note
Item
While subsystem clock running
Does operate with main system clock. Does run. Remains state existing before selection STOP mode. Does run.
Does run.
Does run. Does run.
Does run. Operation enabled
Note
Notes Operation enabled while subsystem clock selected. Operation enabled both three-wire serial UART modes while external clock being used. Maskable interrupt that masked Operation enabled while running. Operation enabled external interrupt.
µPD789405, 789406, 789407
Standby Function Control Register
oscillation settling time selection register (OSTS) used control wait time, from time STOP mode deselected interrupt request, until oscillation settles. OSTS manipulated using 8-bit memory manipulation instruction. RESET input loads into OSTS. RESET input used deselect STOP mode, time required deselect STOP mode will 215/fX, rather than 217/fX. Figure 7-1. Oscillation Settling Time Selection Register Format
Symbol OSTS Address FFFAH When reset
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 (819
Oscillation settling time selection
215/fx (6.55 217/fx (26.2
Other settings
Caution wait time required deselect STOP mode does include time ("a" following chart) required clock oscillation settle after STOP mode deselected, regardless whether STOP mode deselected RESET input interrupt.
STOP mode release voltage waveform
Remarks Main system clock oscillation frequency parenthesized values apply operation MHz.
µPD789405, 789406, 789407
RESET FUNCTIONS
µPD789405, µPD789406, µPD789407 reset using following signals. External reset signal input RESET Internal reset signal generated upon elapse period watchdog timer, used detecting unintended program loop external internal reset signals functionally equivalent. When RESET input, they cause program execution begin addresses indicated addresses 0000H 0001H, respectively. level signal applied RESET pin, watchdog timer overflows, reset occurs, causing each piece hardware enter states listed Table 8-1. While reset signal being input, while oscillation frequency settling immediately after reset sequence, each remains highimpedance state. high level signal applied RESET pin, reset sequence terminated, program execution begins once oscillation settling time /fx) elapses. watchdog timer overflow-based reset sequence terminated automatically. Similarly, program execution begins upon elapse oscillation settling time /fx). Cautions external reset sequence, supply level signal RESET maintain signal least When reset used deselect STOP mode, information related STOP mode held during reset sequence, that while reset signal applied. port pins remain high-impedance state, however. Figure 8-1. Reset Function Block Diagram
RESET
Reset control circuit
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
µPD789405, 789406, 789407
Table 8-1. State Hardware after Reset
Hardware Program counter (PC)
Note
State after reset Loaded with contents reset vector table (0000H, 0001H) Undefined
Stack pointer (SP) Program status word (PSW) Data memory General-purpose register Ports (P0, (output latch) Port mode registers (PM0, PM2, PM4, PM5, PM8, PM9) Pull-up resistor option registers (PU0 PU2) Processor clock control register (PCC) Subsystem clock oscillation mode register (SCKM) Subclock control register (CSS) Oscillation settling time selection register (OSTS) 16-bit timer/counter Timer register (TM5) Compare register (CR50) Capture register (TCP5) Mode control register (TMC5) 8-bit timer/event counters Timer registers (TM0 TM2) Compare registers (CR00 CR20) Mode control registers (TMC0 TMC2) Clock timer Watchdog timer Clock timer mode control register (WTM) Timer clock selection register (TCL2) Mode register (WDTM) converter converter mode register (ADM) converter input selection register (ADS) 8-bit conversion result register (ADCRH) controller/driver display mode register (LCDM) port selector (LPS) clock control register (LCDC) Serial interface Mode register (CSIM0) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Transmission shift register (TXS) Reception buffer register (RXB) Interrupts Request flag registers (IF0, IF1) Mask flag registers (MK0, MK1) External interrupt mode registers (INTM0, INTM1) return mode register (KRM)
UndefinedNote UndefinedNote 0000H FFFFH Undefined Undefined Undefined Undefined
Notes While reset signal being input, during oscillation settling period, contents will undefined, while remainder hardware will same after reset. standby mode, enters hold state after reset.
µPD789405, 789406, 789407
MASK OPTIONS
µPD789405, µPD789406, µPD789407 have following mask options. Mask option This option used specify whether incorporate pull-up resistor, follows: indicate whether pull-up resistor incorporated, individual specified, independently other bits. specification each indicates that pull-up resistor incorporated. Mask option VLC0 VLC2 pins BIAS This option used specify whether voltage division resistor incorporated driver, listed below:
RLC1 RLC2) None RLC2 None
Selectable selectable
VDD0 LIPS N-ch BIAS RLC1
VLC0
RLC2
VLC1 VLCD
RLC2
VLC2
RLC2
VSS0
LIPS: display mode register (LCDM)
µPD789405, 789406, 789407
INSTRUCTION OVERVIEW
instruction µPD789405, µPD789406, µPD789407 listed later.
10.1 Legend
10.1.1 Operand formats descriptions description made operand field each instruction conforms operand format instructions listed below (the details conform with assembly specification). more than operand format listed instruction, selected. Uppercase letters, pair used specify keywords, which must written exactly they appear. meanings these special characters follows: Immediate data specification Relative address specification Absolute address specification Indirect address specification Immediate data should described using appropriate values labels. specification values labels must accompanied pair Operand registers, expressed formats, described using both functional names etc.) absolute names (R0, other names listed Table 10-1). Table 10-1. Operand Formats Descriptions
Format sfrp Description (R0), (R1), (R2), (R3), (R4), (R5), (R6), (R7) (RP0), (RP1), (RP2), (RP3) Special function register symbol Special function register symbol (only registers having even addresses that manipulated 16-bit access mode) saddr saddrp addr16 addr5 word byte FE20H FF1FH: Immediate data label FE20H FF1FH: Immediate data label (even addresses only) 0000H FFFFH: Immediate data label (only even address 16-bit data transfer instructions) 0040H 007FH: Immediate data label (even addresses only) 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label
Remark special function register symbols, Table 4-1.
µPD789405, 789406, 789407
10.1.2 Descriptions operation field NMIS register (8-bit accumulator) register register register register register register register register pair (16-bit accumulator) register pair register pair register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicate that nonmaskable interrupt being handled Contents memory location indicated parenthesized address register name Logical product (AND) Logical (OR) Exclusive Inverted data
Upper lower bits 16-bit register
addr16 16-bit immediate data label jdisp8 Signed 8-bit data (displacement value) 10.1.3 Description flag operation field (blank) change cleared cleared according result restored previous value
µPD789405, 789406, 789407
10.2 Operations
Flag Mnemonic #byte saddr, #byte sfr, #byte saddr saddr, sfr, !addr16 !addr16, PSW, #byte PSW, [DE] [DE], [HL] [HL], byte] byte], saddr [DE] [HL] byte] MOVW #word saddrp saddrp,
Note Note Note
Operand
Byte
Clock byte
Operation
(saddr) byte byte (saddr) (saddr) (addr16) (addr16) byte (DE) (DE) (HL) (HL) byte) byte) (saddr) (sfr) (DE) (HL) byte) word (saddrp) (saddrp)
Note
Note
Notes Except when Except when Only when Remark instruction clock cycle based clock (fCPU), specified processor clock controller register (PCC).
µPD789405, 789406, 789407
Mnemonic
Operand
Note
Byte
Clock
Operation
Flag
XCHW
#byte saddr, #byte saddr !addr16 [HL] byte]
byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte)
ADDC
#byte saddr, #byte saddr !addr16 [HL] byte]
#byte saddr, #byte saddr !addr16 [HL] byte]
SUBC
#byte saddr, #byte saddr !addr16 [HL] byte]
#byte saddr, #byte saddr !addr16 [HL] byte]
Remark instruction clock cycle based clock (fCPU), specified processor clock controller register (PCC).
µPD789405, 789406, 789407
Flag Mnemonic #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] ADDW SUBW CMPW #word #word #word saddr saddr INCW DECW RORC ROLC Operand Byte Clock Operation byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) byte (saddr) (addr16) (HL) byte) word word word rr+1 (saddr) (saddr) rr-1 (saddr) (saddr) (CY, Am-1 (CY, Am+1 Am-1 Am+1
Remark instruction clock cycle based clock (fCPU), specified processor clock controller register (PCC).
µPD789405, 789406, 789407
Flag Mnemonic SET1 Operand saddr. sfr. PSW. [HL]. CLR1 saddr. sfr. PSW. [HL]. SET1 CLR1 NOT1 CALL !addr16 Byte Clock Operation (saddr. bit) sfr. PSW. (HL). (saddr. bit) sfr. PSW. (HL). 3)H, 3)L, addr16, CALLT [addr5] 1)H, 1)L, (00000000, addr5 (00000000, addr5), (SP), RETI (SP), NMIS PUSH PSW, rpH, rpL, (SP), (SP), MOVW !addr16 $addr16 addr16 jdisp8
Remark instruction clock cycle based clock (fCPU), specified processor clock controller register (PCC).
µPD789405, 789406, 789407
Flag Mnemonic $addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 Operand Byte Clock Operation jdisp8 jdisp8 jdisp8 jdisp8 jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 saddr. bit, $addr16 jdisp8 sfr. jdisp8 jdisp8 PSW. jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 DBNZ $addr16 jdisp8 sfr. jdisp8 jdisp8 PSW. then jdisp8 $addr16 then jdisp8 saddr, $addr16 (saddr) (saddr) then jdisp8 (saddr) Operation (Enable Interrupt) (Disable Interrupt) HALT Mode STOP Mode
HALT STOP
Remark instruction clock cycle based clock (fCPU), specified processor clock controller register (PCC).
µPD789405, 789406, 789407
ELECTRICAL CHARACTERISTICS (TARGET VALUES)
Caution ratings listed below target values product, established development stage. ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input voltage Symbol Output voltage Output high current Each Peak value Total pins Peak value Output current
Note
Conditions
Rated value -0.3 +7.0
Unit
Pins other than those port P50-P53 N-channel, open-drain
-0.3 -0.3 -0.3 +150
Each
Peak value
Total pins
Peak value
Operating ambient temperature Storage temperature
Tstg
Note Calculate with [rms] [peak value] duty cycle. Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values. Remark characteristic dual-function does differ between port function secondary function, unless otherwise stated.
µPD789405, 789406, 789407
CHARACTERISTICS MAIN SYSTEM CLOCK OSCILLATION CIRCUIT
Recommended circuit
Resonator Ceramic resonator
Parameter Oscillator frequency (fX)Note
Conditions oscillation voltage range
MIN.
TYP.
MAX.
Unit
Oscillation settling timeNote
After reaches MIN. oscillation voltage range
Crystal
Oscillator frequency (fX)Note
Oscillation settling timeNote
External clock
input frequency (fX)Note
PD74HCU04
input high/low level width (tXH, tXL)
Notes Only characteristic oscillation circuit indicated. characteristic instruction execution time.
description
Time required oscillation settle once reset sequence ends STOP mode deselected. Cautions When using main system clock oscillation circuit, observe following conditions wiring that section enclosed dotted lines above diagrams, avoid influence wiring capacitance. Keep wiring short possible. allow signal wires cross another. Keep wiring away from wires that carry high, non-stable current. Keep grounding point capacitors same level connect grounding point grounding wire that carries high current. extract signal from oscillation circuit. Before switching from subsystem clock back main system clock, always allow sufficient time oscillation settle specifying program.
µPD789405, 789406, 789407
CHARACTERISTICS MAIN SYSTEM CLOCK OSCILLATION CIRCUIT
Recommended circuit
Resonator Crystal
Parameter Oscillator frequency (fXT)Note
Conditions
MIN.
TYP. 32.768
MAX.
Unit
Oscillation settling timeNote
External clock
input frequency (fXT)
Note
PD74HCU04
input high/low level width (tXTH, tXTL)
14.3
15.6
Notes Only characteristic oscillation circuit indicated. characteristic instruction execution time.
description
Time required oscillation settle after reaches MIN. value oscillation voltage range. Cautions When using subsystem clock oscillation circuit, observe following conditions wiring that section enclosed dotted lines above diagrams, avoid influence wiring capacitance. Keep wiring short possible. allow signal wires cross another. Keep wiring away from wires that carry high, non-stable current. Keep grounding point capacitors same level connect grounding point grounding wire that carries high current. extract signal from oscillation circuit.
subsystem clock oscillation circuit designed have amplification degree maintain current drain. Therefore, more likely malfunction result noise than main system clock oscillation circuit. When using subsystem clock, therefore, particularly careful attention wired.
µPD789405, 789406, 789407
CHARACTERISTICS =-40
Parameter High-level input voltage VIH2 Symbol VIH1 Conditions P00-P03, P46, P47, P60P66, P80-P87, P90-P93 P50-P53 MIN. 0.7VDD 0.9VDD 0.7VDD 0.9VDD VIH3 RESET, P20-P27, P40-P45 VIH4 Low-level input voltage VIL2 VIL1 P00-P03, P46, P47, P60P66, P80-P87, P90-P93 P50-P53 0.8VDD 0.9VDD VIL3 RESET, P20-P27, P40-P45 VIL4 High-level output voltage Low-level output voltage VOL1 -100 Pins other than those port VOL2 P50-P53 High-level input leakage current LLIH2 LLIH3 Low-level input leakage current LLIL2 LLIL3 LLIL1 LLIH1 Pins other than pin, pin, those port P50-P53 (N-channel, open-drain) Pins other than pin, pin, those port P50-P53 (N-channel, open-drain) During input instruction execution VOUT VOUT TYP. MAX. 0.3VDD 0.1VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD Unit
High-level output leakage current Low-level output leakage current
ILOH ILOL
Remark characteristic dual-function does differ between port function secondary function, unless otherwise stated.
µPD789405, 789406, 789407
CHARACTERISTICS
Parameter Software-specified pull-up resistor Mask optionspecified pull-up resistor Power supply current
Note
Symbol
Conditions pins other than those port
MIN.
TYP.
MAX.
Unit
P50-P53
IDD1
5.0-MHz crystal oscillation operating mode
Note
0.05 0.05
16.5 12.5 18.3
Note
Note
IDD2
5.0-MHz crystal oscillation HALT mode
IDD3
32.768-kHz crystal oscillation operating modeNote
IDD4
32.768-kHz crystal oscillation HALT modeNote
IDD5
32.768-kHz crystal stop STOP mode
IDD6
5.0-MHz crystal oscillation operating mode
Notes power supply current does include AVREF, AVDD, port current (including current flowing through built-in pull-up resistor). When main system clock running. During high-speed mode operation (when processor clock control register (PCC) cleared 00H.) During low-speed mode operation (when loaded into PCC.) Remark characteristic dual-function does differ between port function secondary function, unless otherwise stated.
µPD789405, 789406, 789407
CHARACTERISTICS Characteristics
Parameter drive voltage Symbol VLCD VAON VAON voltage divider resistor Note output voltage deviationNote (common) output voltage deviationNote (segment) RLCD1 RLCD2 VODC VLCD0 VLCD VLCD1 VLCD VODS VLCD VLCD2 VLCD 1/3Note1 ±0.2
Note
Conditions
MIN.
TYP.
MAX.
Unit
±0.2
Notes ordinary mode (VAON RLCD1, RLCD2, no-resistor selected using mask option. voltage deviation deviation segment common output voltage from ideal value (VLCDn, where
µPD789405, 789406, 789407
CHARACTERISTICS Basic operations
Parameter Cycle time (minimum instruction execution time) Operation based subsystem clock input high/low level width input frequency Interrupt input high/low level width RESET level width tINTH, tINTL tRSL INTP0-INTP3 tTIH, tTIL Symbol Conditions Operation based main system clock MIN. TYP. MAX. Unit
(main system clock)
Measurement point
Cycle time
Supply voltage
µPD789405, 789406, 789407
Serial interface Serial interface channel Three-wire serial mode (SCK.Internal clock output)
Parameter cycle time Symbol tKCY1 Conditions MIN. high/low level width setup time (for hold time (for Delay from output tKH1, tKL1 tSIK1 tKCY1/2-50 tKCY1/2-150 tKSI1 tKSO1 Note TYP. MAX. Unit
Note resistance capacitance output line, respectively. (ii) Three-wire serial mode (SCK.External clock output)
Parameter cycle time Symbol tKCY2 Conditions MIN. high/low level width setup time (for hold time (for Delay from output tKSO2 Note tKH2, tKH2 tSIK2 tKSI2 TYP. MAX. Unit
Note resistance capacitance output line, respectively. (iii) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. Unit
µPD789405, 789406, 789407
(iv) UART mode (external clock input)
Parameter ASCK cycle time Symbol tKCY3 Conditions MIN. ASCK high/low level width Transfer rate tKH3, tKL3 ASCK rising time, falling time TYP. MAX. Unit
µPD789405, 789406, 789407
TIMING MEASUREMENT POINTS (except inputs)
0.8VDD 0.2VDD Measurement points 0.8VDD 0.2VDD
CLOCK TIMING
1/fX VIH4 (MIN.) VIL4 (MAX.)
input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
input
TIMING
tTIL0, tTIL1 tTIH0, tTIH1
TI0,
µPD789405, 789406, 789407
SERIAL TRANSFER TIMING Three-Wire Serial Mode:
tKCYm tKLm tKHm
tSIKm
tKSIm
Input data
tKSOm
Output data
UART Mode (External Clock Input):
tKCY3 tKL3 ASCK tKH3
µPD789405, 789406, 789407
8-BIT CONVERTER CHARACTERISTICS AVDD AVSS
Item Resolution Total error
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
AVDD AVDD
Conversion time Analog input voltage Reference voltage
tCONV VIAN
AVREF
Note quantization error (±1/2 LSB) included. COMPARATOR CHARACTERISTICS
Item Analog input range Reference voltage input range Precision Symbol VCIN VCREF Conditions MIN. TYP. MAX. ±100 Unit
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA HOLD CHARACTERISTICS
Item Data hold supply voltage Release signal time Oscillation settling time tWAIT Reset RESET Reset interrupt Note
Symbol VDDDR
Conditions
MIN.
TYP.
MAX.
Unit
tSREL
Note 212/fX, 215/fX, 217/fX selected according setting bits (OSTS0 OSTS2) oscillation settling time selection register. Remark Main system clock oscillation frequency
µPD789405, 789406, 789407
DATA HOLD TIMING (STOP mode release RESET)
Internal reset operation HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
DATA HOLD TIMING (standby release signal: STOP mode release interrupt signal)
HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
µPD789405, 789406, 789407
INTERRUPT INPUT TIMING
tINTL tINTH
INTP0-INTP3
RESET INPUT TIMING
tRSL
RESET
µPD789405, 789406, 789407
PACKAGE DIMENSIONS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
µPD789405, 789406, 789407
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 1.05 0.05±0.05 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.041 0.002±0.002 0.050 MAX. P80GK-50-BE9-4
µPD789405, 789406, 789407
APPENDIX DEVELOPMENT TOOLS
following development tools available developing systems using µPD789405, µPD789406, µPD789407. LANGUAGE PROCESSING SOFTWARE
RA78K0SNotes CC78K0S
Notes
Assembler package common 78K/0S series compiler package common 78K/0S series Device file µPD789407 sub-series compiler library source file common 78K/0S series
DF789407
Notes
CC78K0S-L
Notes
FLASH MEMORY WRITE TOOLS
Flashpro llNote FA-80GC FA-80GK
Note
Dedicated flash writer (formerly, Flashpro) Flash write adapter
Note
DEBUGGING TOOLS
ND-K904Notes In-circuit emulator µPD789407 sub-series ND-K904 incorporates NS-78K9 screen debugger. This interface board, required when PC-9800 series (other than notebook type) used host machine ND-K904. IF-PCD
Note
IF-98DNote
This interface board, required when PC/AT compatible (other than notebook type) used host machine ND-K904.
IF-CARD
Note
This interface board, required when PC-9800 notebook, PC/AT notebook, compatible used host machine ND-K904.
NP-80GC NP-80GK NJ-535
Note
Emulator probe 80-pin plastic (GC-8BT type) Emulator probe 80-pin plastic (GK-BE9 type) 100/120 adapter 100/240 adapter System emulator common 78K/0S series units Device file µPD789407 sub-series
Note
Note
NJ-550W
Note
SM78K0SNotes DF789407
Notes
µPD789405, 789406, 789407
REAL-TIME
MX78K0SNotes 78K/0S series
Notes Based PC-9800 series (MS-DOSTM) Based PC/ATand compatibles DOSTM/IBM DOSTM/MS-DOS) Based HP9000 series 700(HP-UXTM), SPARCstation(SunOSTM), NEWS(NEWS-OSTM) Product manufactured available from Naito Densei Machida Seisakusho Co., Ltd. (044-8223813). Based PC-9800 series (MS-DOS WindowsTM) Based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) Under development Remark RA78K0S, CC78K0S, ID78K0S, SM78K0S used combination with DF789407.
µPD789405, 789406, 789407
APPENDIX RELATED DOCUMENTS
DOCUMENTS RELATED DEVICES
Document Japanese English This manual
Document name
µPD789405, 789406, 789407 Preliminary Product Information µPD78F9418 Preliminary Product Information µPD789407, 789417 Sub-Series User's Manual
78K/0 Series User's Manual 78K/0S Series Instruction 78K/0S Series Instruction Summary Sheet 78K/0S Series Instruction
U12240J
released soon created released soon created U11047J created created created U11047E
µPD789407 Sub-Series Special Function Registers
DOCUMENTS RELATED DEVELOPMENT TOOLS (USER'S MANUAL)
Document Japanese RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K/0S Compiler Operation Language SM78K0S System Simulator Windows Base SM78K Series System Simulator Reference
External Parts User Open Interface Specifications
Document name
English U11622E U11599E U11623E
U11622J U11599J U11623J
U11816J U11817J U11489J U10092J
U11816E U11817E U11489E U10092E
DOCUMENTS RELATED SOFTWARE INCORPORATED INTO PRODUCT (USER'S MANUAL)
Document Japanese 78K/0S Series MX78K0S created English created
Document name
Caution above documents revised without notice. latest versions when design application systems.
µPD789405, 789406, 789407
OTHER DOCUMENTS
Document Japanese PACKAGE MANUAL Surface Mount Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Device Guide Products Related Micro-Computer: Other Companies C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E IEI-1209 C10983E MEI-1202 English
Document name
Caution above documents revised without notice. latest versions when design application systems.
µPD789405, 789406, 789407
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected
with
resistor, considered have

8-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT µPD7894

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