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METASTABILITY REPORT FPGAs
system designers continue push upper bound performance, understanding metastability operation flip-flops important reliability. High reliability achieved good synchronous design practice careful evaluation device characteristics. speed designs increases above, metastability becomes important issue determining system MTBF (mean-time-between-failure). Metastability very unpredictable event. cause erratic system operation which replicated bench. detailed analysis potential conditions mechanisms involved help designer avoid problems metastability.
WHAT METASTABILITY?
Metastability region uncertainty exhibited flip-flop when timing characteristics setup hold have been violated. ideal world, where logic designs synchronous inputs tied system clock, metastability would concern because timing conditions flipflops would met. since systems synchronous almost every design least completely asynchronous signal which needs synchronized system clock, designer needs take into account possibility violating some timing specifications. Metastable events associated with data transitions occurring close active edge clock. Figure shows example data changing within timing window which will result timing violation. Because timing violation occurred, flip-flop will exhibit erratic behavior. erratic behavior manifests itself form extended propagation delay with unpredictable resolution output.
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FIGURE Metastable Condition
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METASTABILITY REPORT FPGAs
METASTABILITY DESCRIBED?
Metastability typically described four measurements flip-flop performance MTBF, tau, tres. MTBF mean-time-between-failure flip-flop. measured characteristics flip-flop performance which dependant process technology internal design flip-flop. value tres resolution time allowed metastable event resolve itself before output will sampled. general expression describing MTBF MTBF
fclkfdata
where fclk fdata frequency clock data respectively. Solving equation tres results following equation: tres (tau) [(MTBF) (fclkfdata) (W)] Figure shows graph MTBF tres slight increases tres cause significant change MTBF flip-flop.
FIGURE MTBF tres (ns)
fclk fdat
MTBF (sec)
hour
3.00
6.00
tres (ns)
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METASTABILITY REPORT FPGAs
series measurements were taken evaluate metastability hardness QuickLogic's pASIC® family FPGA's. Figure depicts circuit used measure metastable events. first flip-flop (Labeled metastable event generator. Under normal operation, output flip-flops will different, making output exclusive gate logic metastable event occurs, outputs will same cause exclusive gate become logic When this occurs, flip-flop will record this event transmit through nand gate signal ERRCLK. ERRCLK signal that clocks ripple counter record number events that occurred during test. multiplexor output flip-flop used test circuit determine fmax register. signal test point further evaluation.
MEASUREMENTS
FIGURE Test Circuit
ERRCLK XNOR2i0
SEL/STP DATA
NAND2i0
MUX2x3
collection data accomplished stages. Stage determine fmax test circuit setting flip-flop divide-by-two configuration. This guarantees that failures detected flip-flops result exceeding fmax generated metastable events. Once fmax established, variety combinations fclk fdata applied circuit number failures recored over specified period time. maintaining constant relationship between product fclk fdata following equation used determine register.
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tres1 tres2
(MTBF1 (MTBF2 determined taking measurements several values fclk fdata over many different devices. inserting value into MTBF equation, determined graph Figure plotted MTBF tres. table below gives values QuickLogic QL12X16-0,1,2:
Device QL12x16-0 QL12x16-1 QL12x16-2 (sec) 2.91E-10 2.09E-10 1.85E-10 (sec) 2.94E-11 8.38E-11 1.23E-10
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METASTABILITY REPORT FPGAs
CONCLUSION
Comparing MTBF results QuickLogic metastability tests with other published FPGA manufacturers, Figure shows that pASIC devices have much better MTBF than other FPGAs' published data.
FIGURE MTBF Comparisons
week
fclk
MTBF (sec) MTBF
uickLo ilin ctel
tres (ns) (ns)
This very MTBF, combined with easy high-speed architecture, deterministic routing delays fully automatic compilation tools, makes QuickLogic best choice when designing high-performance, highly reliable FPGA-based systems.
1Xilinx data taken from 1992 Xilinx "The Programmable Gate Array Data Book" pages 6-16 through 6-17. Actel data taken from April 1992 Actel Data Book pages 5-2. Altera shown because from October 1990 Altera Data Book pages through 296, MTBF seconds equal tres 38.2
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