IDT71V280 Provides Cache Tag, Status Bits, interface control Data
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CMOS CACHE CONTROLLER WITH INTEL® PENTIUMPROCESSORS
IDT71V280
Provides Cache Tag, Status Bits, interface control Data SRAM control Pentium CPU-based systems High-performance secondary cache implementations Zero-wait state reads writes 3-1-1-1 burst performance Supports multiple cache configurations features 256KB, 512KB, cache sizes Pipelined burst, flow-through burst data SRAMs Write-back, look-aside cache architecture Supports Pentium address pipelining Boot-up selectable write allocation support 10-bit field 512MB cacheable address space using four words line status bits offer four encoded combinations: Invalid Shared (valid clean, write-through) Exclusive (valid clean, write-back) Modified (valid dirty) Power management features minimize power consumption 3.3V (±5%) power supply voltage Packaged 128-lead TQFP
DESCRIPTION
IDT71V280 provides Cache SRAM, Status Bits, interface control, Data SRAM control Pentium secondary cache implementation. Combining these elements single, cost-effective CMOS chip provides system designer with greatly enhanced cache performance reducing cache-subsystem delays. IDT71V280 provides zero-wait state 2-1-1-1 secondary cache performance frequencies 3-1-1-1 performance MHz. IDT71V280 supports number different system configurations performance levels. Cache size, cache wait-state performance, Data SRAM type, Data SRAM size offer system designer wide range cache choices optimize cache configuration exact system needs. Four mode pins determine cache subsystem configuration performance levels, with both asynchronous burst data SRAM support options offered. IDT71V280 uses single 3.3V power supply provide full LVTTL compatibility 3.3V applications. Multiple pins provide excellent noise immunity high frequencies, space saving 14mm 20mm 128-pin Thin Quad Flat Pack offers small board footprint profile maximum packing density.
BLOCK DIAGRAM
INTERFACE MEMORY CONTROL LOGIC CORE LOGIC INTERFACE
STATUS MEMORY DATA SRAM CONTROL INTERFACE
IDT71V280
3100
logo registered trademark Integrated Device Technology, Inc. Pentium trademark Intel Corporation
COMMERCIAL TEMPERATURE RANGE
©1996
JULY 1996
DSC-3100/1
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION
FLUSH# RESET PWRDN# HLDA ADV# BE7# BE6# BE5# BE4# BE3#
CHLDA EADS# AD3/4A(0) AD4/4B(0) AD3/4A(1) AD4/4B(1) LOCK# CACHE# MI/O CHITM# CBOFF# D/C# WRPT# SWB/WT#
PK128-1
BE2# BE1# BE0# SKEN# MODE0 MODE1 MODE2 MODE3 OEB#(1) OEA#(1) SBOFF# HITM# OEB#(0) OEA#(0) CEB#(1) CEA#(1) CEB#(0) CEA#(0) WE#7 WE#6
W/R# ADS# BRDY# CWB/WT# MOD# START# ALE/ADSC# WE0# WE1# WE2# WE3# WE4# WE5# PLLC
3100
TQFP VIEW
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Inputs Input High Voltage Input Voltage Min. Typ. 3.135 -0.3
RECOMMENDED OPERATING TEMPERATURE SUPPLY VOLTAGE
Max. Unit 3.465
Vcc+0.3
Grade Commercial
Temperature +70°C
3.3V
3100
NOTE: 3100 (min.) -1.0V pulse width less than 5ns, once cycle.
RESET FLUSH#
RESET FLUSH# EADS# SKEN# PWRDN# WRPT# PWRDN# WRPT#
RESET FLUSH# EADS# KEN#
TYPICAL SYSTEM IMPLEMENTATION
EADS# KEN#
ADS# A31-A3 BE7#-BE0# D/C# M/IO# W/R# CACHE# LOCK# BRDY# BRDY#
ADS# A31-A3 BE7#-BE0# D/C# M/IO# W/R# CACHE# LOCK#
ADS# A31-A3 BE7#-BE0# D/C# M/IO# W/R# CACHE# LOCK#
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
BRDY# BOFF# WB/WT#
BOFF# WB/WT#
CBOFF# CWB/WT# HITM# HLDA CHITM# CHLDA MOD# START# MODE(0:3)
SBOFF# SWB/WT#
HITM# HLDA
HITM# HLDA MOD# START#
Pentium Processor
Hardwired
Core Logic
DATA SRAM CONTROL
ALE/ADSC# AD3/4A(0:1) AD4/4B(0:1) ADV# CEA#(0:1) CEB#(0:1) OEA#(0:1) OEB#(0:1) WE7#-WE0#
PLLC
IDT71V280
3100
NOTE: PLLC left floating when burst SRAMs used.
COMMERCIAL TEMPERATURE RANGE
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Value -0.5 +4.6 -0.5 -0.5 VCC+0.5 +125 +125 Unit VTERM(2) Terminal Voltage with Respect VTERM(3) Terminal Voltage with Respect VTERM(4) Terminal Voltage with Respect TBIAS TSTG IOUT Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation Output Current
CAPACITANCE(1) +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Capacitance Condition Max. Unit
NOTE: 3100 These parameters maximum values guaranteed tested.
NOTES: 3100 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliabilty. terminal only. Input terminals only. Output terminals; 4.6V maximum.
ELECTRICAL CHARACTERISTICS
3.3V±
IDT71V280 Symbol |ILI| |ILO| Parameter Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Test Condition Max., VIH, VOUT 5mA, Min. -5mA, Min. Max., Min. Typ. Max. Unit
3100
ELECTRICAL CHARACTERISTICS(1)
(VCC 3.3V 0.2V, 0.2V)
Symbol ISB1 ISB2 ISB3 Parameter Dynamic Operating Current VIL, PWRDN VIH, Outputs Open, Max., Inputs Switching Standby Power Supply Current (TTL Level) VIH, PWRDN VIH, Max., Outputs Open, Inputs Switching Full Standby Power Supply Current (TTL Level) PWRDN VIL, Max., Outputs Open, Inputs Switching Full Standby Power Supply Current (CMOS Level) PWRDN VIL, Max., Outputs Open, Inputs Static, IDT71V280 Com'l. Unit
NOTE: values maximum guaranteed values.
3100
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
CLOCK HITM# CHITM# EADS# SNOOP
ADS# A31-A3 BE7#-BE0# D/C# M/IO# W/R# CACHE# LOCK#
ADDRESS CYCLE DEFINITION
WRPT# MOD# START#
CHIPSET COMMUNICATION
IDT71V280
ARBITRATION
SBOFF# CBOFF# HLDA CHLDA
SKEN# CWB/WT# SWB/WT# BRDY# TRANSFER CONTROL
ALE/ADSC# AD3/4A(0:1) AD4/4B(0:1) ADV# DATA SRAM CONTROL CEA#(0:1) CEB#(0:1) OEA#(0:1) OEB#(0:1) WE7#-WE0#
3.3V
RESET FLUSH# PWRDN#
MISC. CONTROL
MODE(0:3)
OPERATIONAL MODE PHASE LOCK LOOP
PLLC
3100
MODE CONFIGURATION TABLE
Performance Read Write/BurstWrite 2-1-1-1 3-1-1-1 2-1-1-1 3-1-1-1 2-1-1-1 3-1-1-1 2/2-1-1-1 3/3-1-1-1 2/2-1-1-1 3/3-1-1-1 2/2-1-1-1 3/3-1-1-1 Cache Line Fill Size 4-1-1-1 4-1-1-1 4-1-1-1 4-1-1-1 4-1-1-1 4-1-1-1 256K 256K 512K 512K SRAM Type(1) deep deep deep deep deep deep SRAM Speed Number 66MHz 50MHz Banks Notes 12ns 12ns 12ns 12ns 12ns 12ns Reserved Reserved banks banks Reserved Reserved Reserved Reserved
3100
Reserved Reserved Reserved Reserved
NOTE: Asynchronous, Flow-through Burst, Pipelined Burst, Applicable.
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
DEFINITION
Symbol A31-A3 Function Address Level Description These address lines. They inputs IDT71V280, except when IDT71V280 performing write cycle either line eviction supply dirty data snoop hit. These pins least significant address lines data SRAMs when asynchronous SRAMs used. When bank SRAMs used these pins AD4. banks interleaved SRAM used these pins AD4A AD4B; that least significant address Bank Bank These pins used with Burst Pipelined Burst data SRAMs. This used external devices inform IDT71V280 that valid address present input cache. This driven IDT71V280, while IDT71V280 asserting CBOFF#, evict dirty line from cache supply dirty data snoop hit. This used advance internal address counter Burst SRAMs. ADV# used with asynchronous data SRAMs. This used latch address into external latch(es) asynchronous data SRAMs, drives ADSC# when burst SRAM implementation used. These byte enable inputs IDT71V280. These inputs sampled during write cycles control byte writes, they used conjunction with M/IO#, W/R#, D/C# determine when special cycle being executed. These pins driven when IDT71V280 performing write cycle either line eviction, supply dirty data snoop hit. This functions "sustained tri-state" mode. BRDY# driven IDT71V280 when either read detected, write detected line marked EXCLUSIVE MODIFIED. IDT71V280 always drives this signal high before tri-stating This input when IDT71V280 detects read miss, write miss, write SHARED line during other cycles that must serviced system. write cycle must serviced system when IDT71V280 samples either LOCK# LOW, WRPT# LOW, HITM# LOW, HIGH initiation write cycle. weak pull-up resistor required maintatin BRDY# high while being actively driven IDT71V280 system. This sampled IDT71V280 beginning cycle determine length cacheability cycle. CACHE# beginning read cycle, read cacheable contains four data words. CACHE# HIGH beginning read cycle, cycle consists single data word. CACHE# beginning write cycle, will execute four word write back. CACHE# HIGH beginning write cycle, will write single word. When IDT71V280 executes write back evict dirty line this driven same time that CBOFF# asserted. This driven when IDT71V280 performing write cycle either line eviction, supply dirty data snoop hit. This output asserted IDT71V280 force when IDT71V280 detects that dirty line must evicted from secondary cache. IDT71V280 also asserts CBOFF#, delayed clock cycle, when SBOFF# input sampled LOW. These pins used assert Chip Enable data SRAMs, each bank SRAMs. This output asserted IDT71V280 clocks after snoop (inquire invalidate) cycle hits dirty line cache. IDT71V280 also asserts CHITM# when HITM# input asserted, with clock cycle delay. During Reset, CHITM# driven HIGH indicate mode with lead-off wait state, driven indicate mode with lead-off wait state. This reflects HLDA input delayed clock cycle. However, IDT71V280 will force CHLDA while performing write back operation. Once IDT71V280 released SBOFF#, will allow CHLDA asserted.
AD3/4A(0:1), AD4/4B(0:1)
Data Address
ADS#
Address Strobe
ADV# ALE/ ADSC# BE7#BE0#
Data Address Controller ADS# Byte Enable
BRDY#
Burst Ready
CACHE#
Cacheability
CBOFF#
Cache Back-off
CEA#(0:1), CEB#(0:1) CHITM#
Data Chip Enable Hit-Modified Output
CHLDA
Hold Acknowledge
HIGH
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
DEFINITION (CONT.)
Symbol Function Clock Level Description This clock input IDT71V280. timing references cache made with respect this input. clock input disabled, PWRDN# must first asserted. This input used disable IDT71V280 from responding memory snoop cycles. IDT71V280 will respond memory, snoop, cycle unless samples clock cycle prior clock concurrent with sampling either ADS# EADS# LOW. Power consumption significantly reduced when deasserted. Output from IDT71V280 CPU. driven reflect whether data being accessed during cache write back write through nature. other cycles, SWB/WT# passed through CWB/WT# with clock cycle delay. This used IDT71V280 conjunction with M/IO#, W/R#, BE7#-BE0# determine when special cycle being executed, type special cycle being executed. This driven HIGH IDT71V280, while IDT71V280 asserting CBOFF#, evict dirty line from cache supply dirty data snoop hit. This input used external devices perform snoop cache line IDT71V280. IDT71V280 recognizes initiation snoop access when EADS# sampled LOW. IDT71V280 ignores ADS# sampled concurrent with sampling EADS# LOW. When FLUSH# input sampled LOW, IDT71V280 control logic placed into flush pending state. While IDT71V280 flush pending state, does alter handles cycles. IDT71V280 initiates cache flush when detects Flush Acknowledge special cycle, dirty lines written back main memory. This input used indicate IDT71V280 that dirty line level cache during inquire (snoop invalidate) cycles. When HITM# sampled asserted, causes IDT71V280 assert CHITM# synchronously with clock cycle delay. Connects HLDA output from CPU, which used acknowledge hold request from HOLD. Except when IDT71V280 performing write back operation, HLDA will propagate through CHLDA with clock cycle delay. When IDT71V280 performing write back operation, will block propagation HLDA until released control bus. used conjunction with EADS# snoop, invalidate, cache line. HIGH, IDT71V280 will consider access invalidation. when EADS# asserted IDT71V280 will consider access snoop. LOCK# sampled beginning read cycle data cache dirty, read cycle treated non-cacheable read miss. cache contains dirty data address location requested locked read cycle, IDT71V280 backs evicts dirty line. LOCK# sampled beginning write cycle, IDT71V280 ignores internal write back/write through flag, treats write cycle write through. IDT71V280 drives this HIGH, while CBOFF# asserted, when executes write cycle evict dirty line from cache supply dirty data snoop hit. This used external devices inform IDT71V280 that memory access being made when this HIGH, that access being made when this LOW. cycles considered cacheable. This driven HIGH IDT71V280, while IDT71V280 asserting CBOFF#, evict dirty line from cache supply dirty data snoop hit. Output asserted IDT71V280 indicate that dirty line being accessed during memory read write cycle. MOD# does depend miss status. remains during Lock operations, driven HIGH response non-cacheable cycles indicated CACHE#. MOD# used system logic anticipate write back line refill sequence.
Cache Select
CWB/WT#
Write Back/Write Through Cache
D/C#
Data/Control
EADS#
External Address Strobe
FLUSH#
Flush
HITM#
Hit-Modified Input
HLDA
Hold Acknowledge
HIGH
Invalidate
HIGH
LOCK#
Lock
M/IO#
Memory/I/O
MOD#
Modified Line
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
DEFINITION (CONT.)
Symbol MODE0MODE3 Function Mode Select Next Address Level Description These pins used select mode which IDT71V280 operates allowed change once IDT71V280 powered This "sustained tri-state" signal that driven clock cycle IDT71V280 during burst read hits pipeline next cycle into current one. IDT71V280 will always drive HIGH before tri-stating input when memory controller servicing memory cycle. weak pull-up resistor required maintain HIGH while being actively driven IDT71V280 system. These pins used assert output enable data SRAMs, each bank SRAMs. This free running output. with asynchronous data SRAMS, which currently supported. should left floating when synchronous data SRAMs used. When used, this connects filter network phase lock loop. currently inactive, this left floating. PWRDN# used force IDT71V280 into lowest power mode while retaining data. long this input asserted IDT71V280 will initiate activity. After this input negated, IDT71V280 will respond normally within 1ms. This input sampled IDT71V280 initiation memory read write cycles. sampled HIGH initiation memory read that results cache miss, line returned automatically considered write through. sampled HIGH initiation memory write cycle, cache ignores value internal write back/write through flag, forced treat write cycle write through. IDT71V280 drives this LOW, while CBOFF# asserted, when IDT71V280 executes write cycle evict dirty line from cache supply dirty data snoop hit. RESET sampled HIGH IDT71V280, control logic reset known state. addition, when RESET sampled HIGH, resettable status bits forced INVALID. During RESET, IDT71V280 drives mode information CHLDA CHITM# pins, drives START# HIGH presence signal. This input forces IDT71V280 address data buses. When SBOFF# asserted, IDT71V280 will only recognize invalidation snoop cycles; however, cache will provide data address invalidation/snoop dirty line until SBOFF# deasserted. When SBOFF# sampled asserted, causes IDT71V280 assert CBOFF# synchronously with clock cycle delay. This sampled IDT71V280 determine whether data being returned during read miss cacheable. SKEN# must sampled least clock cycle before first word transferred cache. This input ignored LOCK# sampled beginning read cycle. With Burst Pipelined Burst SRAMs IDT71V280 samples SKEN# during write-back operations early indicator BRDY# that IDT71V280 time advance data SRAMs next Burst address. write back full speed (x-1-1-1), IDT71V280 must sample SKEN# clock cycle before BRDY# non-pipelined burst SRAMs, clock cycles before BRDY# Pipelined Burst SRAMs. During Reset, SKEN# used indicate IDT71V280 whether write allocation enabled disabled. SKEN# falling edge RESET, write allocation enabled. This output driven IDT71V280 inform system that must service current memory cycle. START# also driven when IDT71V280 writing back dirty line from cache. During Reset, START# driven HIGH presence detect system.
OEA#(0:1), OEB#(0:1)
Data Output Enable Output
PLLC PWRDN#
Loop Filter Power Down
Page Write Through
HIGH
RESET
Reset
HIGH
SBOFF#
System Back-off
SKEN#
Cacheable Data Input
START#
Memory Start
IDT71V280 CMOS CONTROLLER WITH INTEL PENTIUM PROCESSORS
COMMERCIAL TEMPERATURE RANGE
DEFINITION (CONT.)
Symbol SWB/WT# Function Write Back/Write Through System Level Description IDT71V280 samples this signal when first word data loaded into cache during read miss. HIGH this read cycle, value SWB/WT# ignored line returned considered write through. this read cycle, line marked write back SWB/WT# sampled HIGH, marked write through SWB/WT# sampled LOW. When SWB/ sampled LOW, forces CWB/WT# synchronously with clock cycle delay. These pins used assert Write Enable data SRAMs, each byte. This used external devices inform cache that either write being performed when this HIGH, that read being performed this LOW. This also driven HIGH IDT71V280, while IDT71V280 asserting CBOFF#, evict dirty line from cache supply dirty data snoop hit. This input from system sampled concurrently with beginning cycle. WRPT# LOW, IDT71V280 passes control servicing write cycle system controller treats write from write through, even line cache exclusive modified state. Power supply inputs IDT71V280. Ground pins IDT71V280.
3100
WE7#WE0# W/R#
Data Write Enable Write/Read
WRPT#
Write Pass Through
Power Ground
ORDERING INFORMATION
71V280 Device Type Power Speed Package
128-pin Thin-Quad Flat-Pack (PK128-1)
Maximum Clock Rate
71V280
Standard Power CMOS Cache Controller with
3100
Integrated Device Technology, Inc. reserves right make changes specifications this data sheet order improve design performance supply best possible product.
2975 Stender Way, Santa Clara, 95054-3090 Telephone: (800) 544-SRAM FAX: (408) 754-4547
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