LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter

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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter

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LXT350/351 Integrated T1/E1 Transceivers
With Crystal-less Jitter Attenuation
General Description
LXT350 LXT351 full-featured, fully-integrated transceivers short-haul applications. They software switchable between operation, offer pulse equalization settings short-haul line interface (LIU) applications. LXT350 LXT351 identical except their control interface. LXT350 provides both serial port microprocessor control hardware control mode stand alone operation. LXT351 offers Intel- Motorola-bus compatible parallel port microprocessor control. Both incorporate advanced crystal-less digital jitter attenuation either transmit receive data path starting B8ZS/HDB3 encoding/ decoding unipolar bipolar data available. Both LIUs provide loss signal monitoring variety diagnostic loopback modes. LXT350/351 design uses advanced double-poly, double-metal fabrication process requires only single 5-volt power supply.
Features
Fully integrated transceiver short-haul interfaces Crystal-less digital jitter attenuation -Selectable either transmit receive path crystal high-speed external clock required Meet exceed specifications ANSI T1.403 G.73 ETSI 300-166 300-233; AT&T 62411 Support coax), twisted-pair) twisted-pair) applications Fully restores received signal after transmission through cable with attenuation 18dB, 1024 Five Pulse Equalization Settings short-haul applications Transmit/receive performance monitors with Driver Fail Monitor Open (DFM) Loss Signal (LOS) outputs Selectable unipolar bipolar data B8ZS/ HDB3 encoding/decoding QRSS generator/detector testing monitoring Output short circuit current limit protection Local, remote analog loopback capability Multiple-register serial- parallel-control interface Fully compatible with Level One's LXT360/361 Long Haul/Short Haul Transceiver Available 28-pin PLCC packages
RTIP NOISE CROSSTALK FILTER RECEIVE EQUALIZER RRING
Applications
T1/E1 Asynchronous Multiplexers Digital Loop Carrier Subscriber Carrier Systems SDH/SONET Multiplexers T1/E1 LAN/WAN interfaces Bridges Digital Cross Connects
LXT350 Transceiver Block Diagram
EC3-1 TTIP TCLK TPOS TNEG MODE INTERNAL PATTERN GENERATOR (QRSS) B8ZS/HDB3 UNIPOLAR ENCODER TRANSMIT TIMING CONTROL TRANSMIT ATTENUATION FILTER LINE DRIVERS MONITOR TRING CLKE SERIAL PORT SCLK ALOOP ENABLE EC1/ ANALOG LOOPBACK EQUALIZER CONTROL
QRSS ENABLE
ENCODER ENABLE
TAOS ENABLE
Select
CONTROL/STATUS REGISTERS RLOOP ENABLE LLOOP ENABLE
TRSTE
REMOTE LOOPBACK JITTER ATTENUATOR
LOCAL LOOPBACK
JASEL MCLK
ENABLE
CLOCK GENERATOR
ENABLE/ REPORT
DECODER ENABLE
GAIN
RCLK RPOS RNEG INTERNAL PATTERN DETECTOR LOS/
B8ZS/HDB3 UNIPOLAR DECODER
TIMING DATA RECOVERY SLICERS PEAK DETECTORS
PROCESSOR
DETECTOR
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure LXT350 Hardware Controlled Bipolar Mode Assignments
LXT350PE
LXT350NE Table LXT350 Clock Data Assignments Mode1
External Data Modes TPOS TNEG RNEG RPOS TDATA INSBPV RDATA RCLK TTIP TGND TVCC TRING RTIP RRING RNEG RPOS Bipolar Mode Unipolar Mode MCLK TCLK INSLER INSBPV RDATA QRSS Modes Bipolar Mode Unipolar Mode
Data pins change based whether external data internal QRSS mode active. Clock pins remain same both Hardware Host Modes
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Table LXT350 Control Pins Mode
Hardware Modes Unipolar/ Bipolar QRSS Host Modes Unipolar/ Bipolar QRSS LOS/ Hardware Modes Unipolar/ Bipolar RLOOP LLOOP TAOS QRSS QRSS Host Modes Unipolar/ Bipolar SCLK CLKE QRSS
MODE TRSTE JASEL LOS/
MODE TRSTE
Table LXT350 Hardware Controlled Bipolar Mode Signal Descriptions
Symbol MCLK I/O1 Description Master Clock. Connect 1.544 operation; 2.048 MCLK requires external, independent input generate internal clocks. Required accuracy better than with typical duty cycle 50%. Upon Loss Signal (LOS), RCLK derived from MCLK. Transmit Clock. 1.544 2.048 clock input. Transceiver samples TPOS TNEG falling edge TCLK Transmit Data Positive Negative. Bipolar mode, these pins positive negative sides bipolar input pair. Data transmitted onto line input these pins. Table describes Unipolar Mode functions. Mode Select. Connecting MODE puts LXT350 Hardware Mode. Hardware Mode, serial interface disabled hardwired pins used control configuration report status. Leaving MODE open activates Hardware Mode enables B8ZS/HDB3 encoder/ decoder Unipolar Mode. Connecting MODE High puts LXT350 Host Mode. Host Mode, serial interface controls LXT350 displays status. Receive Data Negative Positive. Bipolar mode, these pins positive negative sides bipolar output pair. Data recovered from line interface output these pins. signal RNEG corresponds receipt negative pulse RTIP/RRING. signal RPOS corresponds receipt positive pulse RTIP/ RRING. RNEG/RPOS outputs Non-Return-to-Zero. Both outputs stable valid rising edge RCLK. Refer Table Unipolar mode function descriptions. Recovered Clock. clock recovered from line input signal output this pin. Under conditions there smooth transition from RCLK MCLK output. Tristate. Connecting TRSTE High forces output pins high-impedance state. Connecting TRSTE sets LXT350 Hardware Bipolar Mode. Leaving TRSTE open enables Unipolar Mode. (See Table Unipolar function descriptions.) connection. Leave this floating.
TCLK TPOS TNEG MODE
RNEG RPOS
RCLK TRSTE
Column entries: DI-Digital Input; DO-Digital Output; DI/O-Digital Input/Output; AI-Analog Input; AO-Analog Output
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT350 Hardware Controlled Bipolar Mode Signal Descriptions continued
Symbol JASEL I/O1 Description Jitter Attenuation Select. Selects jitter attenuation location. Connecting JASEL High activates jitter attenuator receive path. Connecting JASEL activates jitter attenuator transmit path. Leaving JASEL open disables Loss Signal Indicator. mode, goes High receipt consecutive spaces returns when received signal reaches mark density 12.5% (determined receipt marks within sliding window bits with fewer than consecutive zeros). modes, goes High receipt consecutive spaces, returns when receiver detects 12.5% mark density (determined receipt marks within sliding window bits with fewer than consecutive zeros). transceiver outputs receives marks RPOS RNEG even when High. Transmit Ring. Differential Driver Outputs. These outputs designed drive load. transformer line matching resistors should selected give desired pulse height return loss performance. Ground. Ground return transmit driver power supply TVCC. Power Supply input transmit drivers. TVCC must vary from more than Ground. this ground. Leave this open. Receive Ring. signal received from line applied these pins. transformer required. Data clock from signal applied these pins recovered output RPOS/RNEG, RCLK pins. Power Supply circuits except transmit drivers. (Transmit drivers supplied TVCC.) Ground. Ground return power supply VCC. Equalization Control 3-1. These pins define Pulse Equalization settings. Table additional details. Remote Loopback. When held High, clock data inputs from framer (TPOS/ TNEG TDATA) ignored data received from line transmitted back onto line RCLK frequency. During remote loopback, device ignores inline encoders/decoders. Figure Local Loopback. When held High, data TPOS TNEG loops back digitally RPOS RNEG outputs (through enabled). Leaving this open enables Analog Loopback (TTIP TRING looped back RTIP RRING). Figures Transmit Ones. When held High transmit data inputs ignored LXT350 transmits stream TCLK frequency. TCLK supplied, MCLK transmit clock reference.) TAOS inhibited during Remote Loopback. Leaving this open enables QRSS pattern generation detection. Figures
TTIP TRING TGND TVCC RTIP RRING RLOOP
LLOOP
TAOS
Column entries: DI-Digital Input; DO-Digital Output; DI/O-Digital Input/Output; AI-Analog Input; AO-Analog Output
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT350 Hardware Controlled Unipolar Mode Signal Assignments
Symbol TDATA INSBPV I/O1 Description Transmit Data. Unipolar input data transmitted onto line. Insert Bipolar Violation. This sampled falling edge TCLK control Bipolar Violation Insertions transmit data stream. Low-to-High transition required insert subsequent BPVs. Bipolar Violation. goes High report receipt bipolar violation from line. This output, valid rising edge RCLK. Receive Data. RDATA unipolar output data recovered from line interface. Hardware Mode RDATA stable valid rising edge RCLK.
RDATA
Column entries: DI-Digital Input; DO-Digital Output; DI/O-Digital Input/Output; AI-Analog Input; AO-Analog Output
Table LXT350 Hardware Controlled QRSS Unipolar Mode Signal Assignments
Symbol INSLER I/O1 Description Insert Logic Error. When this goes from High, transceiver inserts logic error into transmitted QRSS data pattern. error follows data flow whatever loopback mode effect. LXT350 samples this falling edge TCLK MCLK, TCLK present). Insert Bipolar Violation. When this goes from High, transceiver inserts bipolar violation error into transmitted QRSS data pattern. subsequent insertion requires another High transition. LXT350 samples this falling edge TCLK MCLK, TCLK present). Bipolar Violation. goes High report receipt bipolar violation from line. This output, valid rising edge RCLK. Received Data. RDATA unipolar output data recovered from line interface. hardware Mode, RDATA stable valid rising edge RCLK. Loss Signal/QRSS Pattern Detect. This acts indicator well indicator. QRSS Pattern synchronization criterion fewer than four errors bits. this mode, long transceiver does detect QRSS pattern stays High. soon device does detect QRSS pattern, goes Low; errors cause High half clock cycle. This output trigger external error counter. condition also makes this High. Figure QRSS. Leaving this open, enables QRSS pattern generation detection. transceiver transmits QRSS pattern TCLK rate MCLK, TCLK present).
INSBPV
BPV2 RDATA2
LOS/QPD
QRSS
Column entries: DI-Digital Input; DO-Digital Output; DI/O-Digital Input/Output; AI-Analog Input; AO-Analog Output QRSS Bipolar Mode, pins RNEG RPOS output, respectively.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT350 Host Controlled Bipolar Mode Signal Assignments
Symbol RNEG RPOS I/O3 Description Received Data-Negative Positive. Bipolar Mode, these pins negative positive sides bipolar output pair. transceiver outputs data recovered from line interface these pins. signal RNEG corresponds receipt negative pulse RTIP/RRING. signal RPOS corresponds receipt positive signal RTIP/RRING. RNEG/RPOS outputs Non-Return-to-Zero (NRZ). CLKE determine clock edge which these outputs stable valid. Figure Tristate. Connecting TRSTE High forces output pins high-impedance state. Connect this normal operation. connected. this ground. this ground Interrupt (Active Low-Maskable). goes flag host when LOS, AIS, QRSS DFMO changes state when there Elastic Store overflow underflow. open drain output which requires connection power supply through resistor. Reset writing respective Interrupt Clear Register. Serial Data Input. Input port 16-bit serial address/command data word. LXT350 samples rising edge SCLK. Figure Serial Data Output. CLKE High, valid rising edge SCLK. CLKE Low, valid falling edge SCLK. This goes highimpedance state when serial port being written when High. Figure Chip Select (Active Low). This input used access serial interface. each read write operation, must transition from High Low, remain Low. Serial Clock. This clock used write data read data from serial interface registers. clock frequency rate 2.048 MHz. Clock Edge. Setting CLKE High causes RPOS RNEG valid falling edge RCLK, with valid rising edge SCLK. Setting CLKE makes RPOS RNEG valid rising edge RCLK valid falling edge SCLK.
TRSTE
SCLK CLKE
pins described this table, Table data pins Unipolar QRSS Modes remains same Tables Host Mode, control pins (23-28) change shown Table QRSS Bipolar Mode, pins seven RNEG RPOS, respectively. Column entries: DI-Digital Input; DO-Digital Output; DI/O-Digital Input/Output; AI-Analog Input; AO-Analog Output
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure LXT351 Bipolar Mode Assignments
LXT351PE
LXT351NE
QRSS Modes Bipolar Mode MCLK TCLK Unipolar Mode
Table LXT351 Clock Data Assignments Mode1
External Data Modes TPOS TNEG RNEG RPOS TDATA INSBPV RDATA RCLK TTIP TGND TVCC TRING RTIP RRING RNEG RPOS Bipolar Mode Unipolar Mode
INSLER INSBPV RDATA
Data pins change based whether external data internal QRSS mode active. These pins remain same both Hardware Host Modes.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Table LXT351 Processor Interface Pins
Address/Data Type Intel Motorola Address/Data Type Intel Motorola
Table LXT351 Bipolar Mode Signal Assignments
Symbol MCLK I/O1 Description Master Clock. Connect 1.544 operation; 2.048 MCLK requires external, independent input generate internal clocks. Required accuracy better than with typical duty cycle 50%. Upon Loss Signal (LOS), transceiver derives RCLK from MCLK. Transmit Clock. 1.544 2.048 rate clock input. transceiver samples TPOS TNEG falling edge TCLK Transmit Data Positive Negative. Bipolar Mode, these pins positive negative sides bipolar input pair. Data transmission onto line input these pins. Address Latch Enable/Address Strobe (Active Low). Connects Intel (ALE) Motorola (AS) signal. Motorola bus, this signal Active Low. Leaving this floating forces output pins into high impedance state. Receive Data Negative Positive. Bipolar mode, these pins positive negative sides bipolar output pair. Data recovered from line interface output these pins. signal RNEG corresponds receipt negative pulse RTIP/RRING. signal RPOS corresponds receipt positive pulse RTIP/RRING. RNEG/RPOS outputs Non-Return-to Zero. Both outputs stable valid rising edge RCLK. Refer Table Unipolar mode function descriptions. Recovered Clock. output this clock recovered from line input signal. Under conditions there smooth transition from RCLK MCLK output.
TCLK TPOS TNEG RNEG RPOS
RCLK
column entries Digital Input; Digital Output, DI/O Digital Input Output; Analog Input Analog Output.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT351 Bipolar Mode Signal Assignments continued
Symbol I/O1 Description Read (Active Low)/Data Strobe (Active Low). Intel bus, this signal, Read, goes command read operation. Motorola bus, this signal, Data Strobe, goes when data being driven address/data bus. Data valid rising edge Address/Data lines Used with pins 24-28 address/data bus.
DI/O DI/O
Write (Active Low) Write/Read. Intel bus, driving this signal (Write) enables write operation Address/Data bus. Motorola bus, driving this signal (Read/Write) High commands read operation, driving commands write operation. Transmit Ring. Differential Driver Outputs. design load these outputs Select transformer line matching resistors give desired pulse height. Ground. Ground return transmit drivers power supply TVCC. Power Supply input transmit drivers. TVCC must vary from more than
TTIP TRING TGND TVCC
Chip Select (Active Low). each read write Address/Data bus, this must during operation. Figures timing requirements. case single processor controlling several chips, this line uses command specific transceiver. Interrupt (Active Low). This goes signal interrupt chip. identify specific interrupt, read Performance Status Register. clear mask interrupt, write appropriate Clear Interrupt Register. Receive Ring. signal received from line applied these pins. transformer required. Data clock from signal applied these pins recovered output RPOS/RNEG, RCLK pins. Power Supply circuits except transmit drivers. (Transmit drivers supplied TVCC.) Ground return power supply VCC.
RTIP RRING
DI/O
Address/Data Lines 0-5. (Also pins 11-AD6 Conform Intel Motorola Address/Data specifications.
column entries Digital Input; Digital Output, DI/O Digital Input Output; Analog Input Analog Output.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT351 Unipolar Mode Signal Assignments1
Symbol TDATA INSBPV I/O2 Description Transmit Data. Unipolar data transmission onto line. Insert Bipolar Violation. Controls bipolar violation insertions, requires Low-to-High transition insert each violation, LXT351 samples signal falling edge TCLK. Bipolar Violation. goes High receipt bipolar violation from line. This output, valid rising edge RCLK. Received Data. RDATA output data recovered from line interface. RDATA valid rising edge RCLK.
RDATA
descriptions pins identified this table, Table LXT351 Bipolar Mode Signal Assignments. column entries Digital Input; Digital Output, DI/O Digital Input Output; Analog Input Analog Output.
Table LXT351 QRSS Unipolar Mode Signal Assignments1,2
Symbol INSLER I/O3 Description Insert Logic Error. When this goes from High, transceiver inserts logic error into transmitted QRSS data pattern. error follows data flow whatever loopback mode effect. LXT351 samples this falling edge TCLK MCLK, TCLK present). Insert Bipolar Violation. When this goes from High, transceiver inserts bipolar violation error into transmitted QRSS data pattern. subsequent insertion requires another High transition. LXT351 samples this falling edge TCLK MCLK, TCLK present). Bipolar Violation. goes High receipt bipolar violation from line. This output, valid rising edge SCLK. Received Data. RDATA output data recovered from line interface. RDATA valid rising edge RCLK.
INSBPV
RDATA
descriptions pins identified this table, Table LXT351 Bipolar Mode Signal Assignments. QRSS Bipolar Mode, pins RNEG RPOS, respectively. column entries Digital Input; Digital Output, DI/O Digital Input Output; Analog Input, Analog Output.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure LXT351 Block Diagram
TTIP TCLK TPOS TNEG INTERNAL PATTERN GENERATOR (QRSS) B8ZS/HDB3 UNIPOLAR ENCODER TRANSMIT TIMING CONTROL TRANSMIT EQUALIZER LINE DRIVERS MONITOR TRING AD0-7 Select CONTROL ENABLE JASEL MCLK INTERNAL PATTERN DETECTOR RCLK RPOS RNEG DECODER ENABLE RLOOP ENABLE LLOOP ENABLE REMOTE LOOPBACK JITTER ATTENUATOR LOCAL LOOPBACK ENABLE CLOCK GENERATOR ALOOP ENABLE EQUALIZER CONTROL ANALOG LOOPBACK PARALLEL PORT ALE/AS RD/DS WR/W/R
QRSS ENABLE
ENCODER ENABLE
TAOS ENABLE
B8ZS/HDB3 UNIPOLAR DECODER
TIMING DATA RECOVERY SLICERS PEAK DETECTORS PROCESSOR DETECTOR
RRING NOISE CROSSTALK FILTER RECEIVE EQUALIZER RTIP
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
FUNCTIONAL DESCRIPTION
NOTE This functional information design only. Unless specified otherwise, descriptions, tables figures apply equally both LXT350 LXT351 transceivers. LXT350 LXT351 fully-integrated, transceivers short-haul, 1.544 Mbps (T1) 2.048 Mbps (E1) applications allowing full-duplex transmission digital data over existing twisted-pair installations. They interface with lines (one pair each transmit receive) through standard pulse transformers appropriate resistors. figure front this Data Sheet shows block diagram LXT350. Host Mode device controlled through serial microprocessor. Hardware Mode controlled individual pins. Figure block diagram LXT351. LXT351 parallel port microprocessor control. Both transceivers provide high-precision, crystal-less jitter attenuator. user place transmit receive path, bypass completely. transceivers meet exceed ANSI, requirements.
TRANSMITTER Digital Data Interface
Input data transmission onto line clocked serially into device TCLK rate. TPOS TNEG bipolar data inputs. TDATA accepts unipolar data. (Leaving TRSTE open enables Hardware Unipolar Mode.) Input data pass through either Jitter Attenuator B8ZS/HDB3 encoder both. CR1.ENCENB enables B8ZS/HDB3 encoding Host Mode. Hardware Mode, leaving MODE open selects zero suppression coding. With zero suppression enabled, inputs (see Table determine coding scheme (B8ZS HDB3 mode). HDB3 scheme, EC3-1 001. Other settings select B8ZS option. transmit clock (TCLK) supplies input synchronization. Test Specifications section defines transmit timing requirements TCLK Master Clock (MCLK).
Short Circuit Limit
transmitter includes short-circuit limiter. This limits current sourced into low-impedance load. automatically resets when load current drops below limit. current determined interface circuitry (total resistance transmit side). Host Mode, Performance Status Register flags open circuits PSR.DFMO. transition DFMO will provide interrupt transition sets TSR.DFMO Writing ICR.CDFMO clears interrupt; leaving masks that interrupt.
INITIALIZATION
During power transceiver remains static until power supply reaches approximately crossing this threshold, device begins reset cycle calibrate Phase Locked Loops. transceiver uses reference clock calibrate PLL-the transmitter reference TCLK, receiver reference clock MCLK. MCLK mandatory chip operation.
Output Drivers
transceivers transmit data line code shown Figure Activating line driver only during mark reduces power consumption. output driver disabled during transmission space. Biasing transmit level on-chip.
Reset Operation
Reset clears sets registers resets status state machines LOS, QRSS blocks. Hardware Mode, holding pins RLOOP, LLOOP TAOS High least clock cycle resets device. Writing CR2.RESET commands reset Host Mode. Allow device settle after removing reset conditions.
Figure Duty Cycle Coding Diagram
TTIP Mark TRING Space Mark
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Idle Mode
Transmit Idle Mode normal operational mode opposed modes) which allows multiple transceivers connected single line redundant applications. TTIP TRING remain high impedance state when TCLK present. Remote Dual Loopback, TAOS internal transmit patterns temporarily disable high impedance state.
RECEIVER
transformer provides interface line. Recovered data output RPOS/RNEG (RDATA Unipolar mode), recovered clock output RCLK. Test Specifications section shows receiver timing. transceiver filters equalized signal applies peak detector data slicers. peak detector samples inputs determines maximum value received signal. data slicers peak value ensure optimum signal-to-noise performance operation. After processing through data slicers, received signal goes data timing recovery section, then B8ZS/HDB3 decoder selected) receive monitor. data timing recovery circuits provide input jitter tolerance significantly better than required AT&T 62411 G.823. Test Specifications section.
Pulse Shape
Equalizer Control inputs (EC3 through EC1) determine transmitted pulse shape. Host Mode, port controls values. LXT350 Hardware Mode, three individual pins provide inputs. Shaped pulses meeting DSX-1 specifications applied line driver transmission onto line TTIP TRING. Refer Test Specifications section pulse mask specifications.
Table Equalizer Control Input Settings
Function
Pulse G.703 0-133 133-266 266-399 399-533 533-655
Cable Coax/120
Coding1 HDB3 B8ZS B8ZS B8ZS B8ZS B8ZS
When enabled.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Digital Data Interface
either Host Hardware Control Mode recovered data goes Loss Signal (LOS) Monitor. Host Control Mode, also goes through Alarm Indication Signal (AIS, Blue Alarm) Monitor. jitter attenuator circuit enabled disabled receive data path transmit path. Received data through either B8ZS HDB3 decoder neither. Finally, device send digital data framer either unipolar bipolar data. When transmitting unipolar data framer, device reports receiving bipolar violations driving High. During operation Host Control Mode, device report HDB3 code violations Zero Substitution Violations pin. diagnostics section explains these options more detail.
JITTER ATTENUATION
Jitter Attenuation Loop (JAL) with Elastic Store (ES) provides jitter attenuation shown Test Specifications section. requires special circuitry, such external quartz crystal high-frequency clock (higher than line rate). timing reference master clock, MCLK. Hardware Control Mode 2-bit register. Setting JASEL High places circuitry received data path; setting JASEL places transmit data path; leaving open disables Host Mode, CR1.JASEL0 enables disables circuit. With CR1.JASEL0 CR1.JASEL1 controls circuit placement (see Table 17). either 2-bit 2-bit register depending value CR3.ES64 (see Table 19.) device clocks data into using either TCLK RCLK depending whether circuitry transmit receive data path, respectively. Data shifted elastic store using dejittered clock from JAL. When FIFO within bits overflowing underflowing, adjusts output clock period. produces average delay bits bits, with 64-bit option selected Host Control Mode) associated data path. When Jitter Attenuator receive path, output RCLK transitions smoothly MCLK event condition. Transition Status Register bits TSR.ESOVR TSR.ESUNF indicate overflow underflow, respectively These sticky bits: Once they remain until host reads register. also provide maskable interrupt either overflow underflow.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation DIAGNOSTIC MODE OPERATION
LXT350/351 offers multiple diagnostic modes shown Table Hardware Mode, diagnostic modes selected combination settings. Host Mode, diagnostic modes selected writing appropriate bits Diagnostic Control Register.
Table Diagnostic Mode Availability
Availability1 Diagnostic Mode Loopback Modes Local Loopback (LLOOP) Analog Loopback (ALOOP) Remote Loopback (RLOOP) Dual Loopback (DLOOP) Internal Data Pattern Generation Detection Transmit Ones (TAOS) Quasi-Random Signal Source (QRSS) Error Insertion Detection Bipolar Violation Insertion (INSBPV) Logic Error Insertion (INSLER) Bipolar Violation Detection (BPV) Logic Error Detection, QRSS (QPD) HDB3 Code Violation Detection (CODEV) HDB3 Zero violation Detection (ZEROV) Alarm Condition Monitoring Receive Loss Signal (LOS) Monitoring Receive Alarm Indication Signal (AIS) Monitoring Transmit Driver Failure Monitoring-Open (DFMO) Elastic Store Overflow Underflow Monitoring Built-In Self Test (BIST) Host Host Mode2 Maskable
Hardware Control Mode, combination settings selects Diagnostic Modes; Host Control Mode, writing appropriate bits into Control Registers selects Diagnostic Modes. Host Control Mode allows interrupt masking writing corresponding Interrupt Clear Register. Hardware Control Mode interrupt masking feature.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation LOOPBACK MODES
NOTE Hardware Mode pins discussed this section refer LXT350 only. Local Loopback Figures Hardware Mode, Local Loopback (LLOOP) selected tying LLOOP High; Host Mode, setting CR2.ELLOOP LLOOP inhibits receiver circuits. transmit clock data inputs (TCLK TPOS/TNEG TDATA) loop back through jitter attenuator enabled) show RCLK RPOS/ RNEG RDATA. (During LLOOP, JASEL input strictly Enable/Disable control; does affect placement JAL. enabled, active loopback circuit. bypassed, active loopback circuit.) transmitter circuits unaffected LLOOP. LXT350/351 transmits TPOS/TNEG TDATA inputs stream TAOS asserted) normally. When used this mode, transceiver function stand-alone jitter attenuator.
Figure Local Loopback Selected)
Local Loopback with Receive Path
B8ZS/HDB3 ENCODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Local Loopback with Transmit Path
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 DECODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Analog Loopback Figure Analog Loopback (ALOOP) exercises maximum number functional blocks. ALOOP operation disconnects RTIP/RRING inputs from line routes transmit outputs back into receive inputs. This tests encoders/decoders, jitter attenuator, transmitter, receiver timing recovery sections. Hardware Mode, leaving open commands Analog Loopback; Host Mode, writing CR2.EALOOP enables function. ALOOP function overrides other loopback modes.
Figure TAOS with LLOOP Selected)
Transmit Ones Local Loopback with Receive Path
B8ZS/HDB3 ENCODER*
TAOS TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled
TTIP TRING
Figure Analog Loopback Selected)
Analog Loopback with Receive Path
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 DECODER*
Timing Recovery
RTIP RRING
TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 DECODER*
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Transmit Ones Local Loopback with Transmit Path
TAOS
B8ZS/HDB3 ENCODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING
Analog Loopback with Transmit Path
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 DECODER*
RTIP RRING
B8ZS/HDB3 DECODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
B8ZS/HDB3 DECODER*
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Remote Loopback
Figure Remote Loopback (RLOOP) mode, device ignores transmit data clock inputs (TCLK TPOS/TNEG TDATA), bypasses in-line encoders/decoders. RPOS/RNEG RDATA outputs loop back through transmit circuits TTIP TRING RCLK frequency. RLOOP command does affect receiver circuits which continue output RCLK RPOS/RNEG RDATA signals received from twisted-pair line. Host Mode, command RLOOP writing CR2.ERLOOP. Hardware Mode, RLOOP commanded setting High.
INTERNAL PATTERN GENERATION DETECTION Transmit Ones
Figure Transmit Ones (TAOS) Mode transceiver ignores TPOS TNEG inputs transmits continuous stream TCLK frequency. (With TCLK, TAOS output clock MCLK.) This used Alarm Indication Signal (AIS-also called Blue Alarm). Host Mode, TAOS commanded writing CR2.ETAOS. Hardware Mode setting High does Both TAOS Local Loopback occur simultaneously shown Figure Remote Loopback inhibits TAOS. When both TAOS LLOOP active, TCLK TPOS/TNEG loop back RCLK RPOS/RNEG through jitter attenuator enabled), ones pattern goes TTIP/TRING.
Dual Loopback
Figure select Dual Loopback (DLOOP), both RLOOP LLOOP High Hardware Mode bits CR2.ERLOOP CR2.ELLOOP Host Mode. DLOOP mode, transmit clock data inputs (TCLK TPOS/TNEG TDATA) loop back through Jitter Attenuator (unless disabled) RCLK RPOS/RNEG RDATA. data clock recovered from line loop back through transmit circuits TTIP TRING without jitter attenuation.
Figure TAOS Data Path
TAOS TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 B8ZS/HDB3 DECODER* ENCODER*
Timing Control Enabled Timing Recovery
TTIP TRING
Figure Remote Loopback Selected)
Remote Loopback with Receive Path
RTIP RRING
TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 ENCODERS*
B8ZS/HDB3 DECODERS*
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Quasi-Random Signal Source (QRSS)
operation Quasi-Random Signal Source (QRSS) 220-1 pseudo-random sequence (PRBS) with more than consecutive zeros. operation, QRSS 215-1 PRBS with inverted output. Both Hardware Host Modes allow QRSS Mode. QRSS pattern normally locked TCLK; there TCLK, MCLK clock source. Bellcore 62411 defines QRSS transmit format G.703 defines format. Leaving TAOS (pin open enables QRSS transmission Hardware Mode. Host Mode, setting bits CR2.EPAT0 CR2.EPAT1=1enables this function. With QRSS transmission enabled, possible insert logic error into transmit data stream causing Low-to-High transition INSLER (pin However, logic errors inserted into QRSS pattern, INSLER must remain Low. Logic Error insertion waits until next current "jammed". (When there more than consecutive output jammed
Remote Loopback with Transmit Path
B8ZS/HDB3 ENCODERS*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Figure
TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 B8ZS/HDB3 DECODER* ENCODER*
B8ZS/HDB3 DECODERS*
Dual Loopback
Timing Control Enabled Timing Recovery RTIP RRING TTIP TRING
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Furthermore bipolar violation QRSS pattern possible causing Low-to-High transition INSBPV (pin without regard whether device bipolar unipolar operating mode.
ERROR INSERTION DETECTION Bipolar Violation Insertion (INSBPV)
Unipolar Mode, both Hardware Host Modes provide Bipolar Violation Insertion (INSBPV). Choosing Unipolar Mode configures INSBPV. Bipolar violation insertion requires Low-to-High transition INSBPV. Sampling occurs falling edge TCLK. When INSBPV goes High inserted next available mark except three following situations: Zero suppression (HDB3 B8ZS) violated LLOOP TAOS both active, looped back RNEG/BPV indicator line driver transmits ones with violation. insertion disabled with RLOOP (remote loopback) active. With LXT350/351 configured transmit internally generated QRSS data patterns inserted transmit pattern independent whether device unipolar bipolar mode operation.
Figure QRSS Mode
Choosing QRSS Mode also enables QRSS Pattern Detection (QPD) receive path. QRSS pattern synchronized when there fewer than four errors bits. After achieving synchronization device drives (pin (QPD output available LXT350 only). LXT351 does support error detection QRSS Mode. LXT350 QRSS Mode, subsequent error QRSS pattern causes High half RCLK clock cycle (the precise relationship RCLK depends value CLKE-when CLKE Low, goes High while RCLK High; CLKE High, goes High while RCLK Low). This signal edge serve trigger external bit-error counter. condition loss QRSS synchronization will cause this output High continuously. this case, with either Unipolar Mode encoders/decoders enabled, indicates BPVs, CODEVs ZEROVs chosen. Host Mode offers additional interrupt indicate that QRSS detection sychronization have occurred, that synchronization lost. This interrupt available when ICR.CQRSS signal triggers error counter, interrupt could start reset counter. Also Host Mode, PSR.QRSS provides indication QRSS pattern synchronization. This goes with QRSS pattern detected (i.e., when there more than four errors bits). TQRSS Transition Status Register indicates that QRSS status changed since last QRSS Interrupt Clear command.
Logic Error Insertion (INSLER)
When configured transmit internally generated QRSS data patterns, device insert logic error transmit data pattern when there Low-to-High transition INSLER. transceiver treats data patterns same treats data applied TPOS/TNEG, inserted logic error will follow data flow path defined loopback mode effect.
Logic Error Detection (QPD) (LXT350 Only)
After receiving pattern synchronization when configured QRSS Mode, LXT350 reports logic errors (pin 12). indicate logic error, this goes High half RCLK cycle (during High period RCLK CLKE during RCLK period CLKE High). monitor logic errors, connect error counter QPD. continuous High level this indicates loss either QRSS pattern lock condition. QRSS section additional details QRSS pattern lock criteria. Bipolar Violation Detection (BPV) With internal encoders/decoders enabled when configured Unipolar Mode, LXT350/351 reports received Bipolar Violations (pin goes High full clock cycle indicate receipt BPV. However, encoders/decoders enabled, LXT350/ does report bipolar violations line coding scheme.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation HDB3 Code Violation Detection (CODEV)
LXT350/351 detect HDB3 code violations Host Mode with HDB3 encoders enabled. This requires CR1.ENCENB CR1.EC3-1 000, 010, which establishes operation. enable CODEV, CR4.CODEV HDB3 code violation (CODEV) occurs when device receives consecutive bipolar violations same polarity (refer O.161). With CODEV detection enabled, LXT350/351 reports violation along with received BPVs ZEROVs these options enabled). LXT350/351 forces High full RCLK cycle report CODEV. operation, condition cleared when received signal rises above dBtypical below minimum level 12.5% density (four sliding 32-bit window with fewer than consecutive 0s). Host Mode operation, out-of-LOS criterion modified from 12.5% marks density consecutive marks setting CR4.COL32CM During LOS, device sends received data RPOS/ RNEG pins RDATA Unipolar Mode). LXT350 reports condition Hardware Mode. Host Mode, Performance Status Register goes High indicate condition will interrupt host controller programmed.
Alarm Indication Signal Detection (AIS)
Alarm Indication Signal (AIS) available only Host Mode. receiver detects pattern when receives fewer than three string 2048 bits. device clears condition when receives three more string 2048 bits. Performance Status Register indicates detection. When status changes, TAIS Transition Status Register goes High. change status interrupts host controller pulling Low, unless interrupt masked. Writing ICR.CAIS masks interrupt until returns
HDB3 Zero Substitution Violation Detection (ZEROV)
With encoders/decoders enabled, LXT350/351 detect HDB3 zero substitution violations (ZEROV) Host Mode. This requires CR1.ENCENB CR1.EC3-1 000, 001, 1010, which establish operation, CR4.ZEROV LXT350/351 forces High full RCLK cycle report ZEROV. HDB3 ZEROV receipt four more consecutive zeros. This does occur with correctly encoded HDB3 data unless there transmission errors. With ZEROV detection enabled, device reports violation along with received BPVs CODEVs these options enabled).
Driver Failure Mode Open (DFMO)
Host Mode Open (DFMO) available Performance Status Register indicate open condition lines. DFMO generate host controller. Transition Status Register DFMO indicates transition status bit. Writing ICR.CDFMO will clear mask interrupt.
ALARM CONDITION MONITORING Loss Signal (LOS)
LXT350/351 Loss Signal (LOS) monitor function compatible with G.775 ETSI 300233. They combination analog digital detection scheme. receiver monitor loads digital counter RCLK frequency. counter increments with each received resets receipt signal that remains typical below nominal signal consecutive pulse generates internal condition. operations, 175; operations, Host Mode, either number changed 2048 setting CR4.LOS2048 MCLK replaces recovered clock RCLK output smooth transition. operation, when received signal 12.5% density marks sliding 128-bit period, with fewer than consecutive 0s), flag returns recovered clock replaces MCLK RCLK output another smooth transition.
Elastic Store Overflow/Underflow
(ESOVR/ESUNF) When count Elastic Store (ES) within bits overflowing underflowing adjusts output clock period. Host Mode, provides indication overflow underflow TRS.ESOVR TSR.ESUNF. These sticky bits will stay until host controller reads register. These interrupts cleared masked writing bits ICR.CESO ICR.CESU, respectively.
OTHER DIAGNOSTIC MODES Built-In Self Test (BIST)
LXT350/351 provides Built-In Self Test (BIST) capability Host Mode. BIST exercises internal circuits
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
providing internal QRSS pattern, running through encoders transmit drivers then looping back through receive equalizer, Jitter Attenuator decoders QRSS pattern detection circuitry. blocks this data path work correctly, receive pattern detector locks onto pattern. then pulls sets following bits High: TSR.TQRSS PSR.QRSS PSR.BIST (pin also indicates completion status test. Starting test forces this High. During test, remains High until test finishes successfully which time goes Low.
Table Control Operational Mode Selection LXT350 Transceiver
Input Pin1 Mode High High High Open Open TRSTE High Open High Open High Open Hardware Bipolar Hardware Tristate Hardware Unipolar Software2 Software2 Tristate Outputs Software2 Hardware Unipolar (Encoder Hardware Unipolar (Encoder On); Tristate Outputs Hardware Unipolar (Encoder Mode
OPERATING MODES
LXT350/351 share many features. However, their control modes very different. LXT350 operates either Hardware (Serial Port) Host Mode LXT351 operates (Parallel Port) Host Mode only. Hardware Mode (LXT350 only) individual pins control transceiver. logic level MODE sets LXT350 mode operation. Host Mode (LXT350/351), microprocessor controls device through data interface. LXT350 serial interface LXT351 uses parallel interface.
Open
Open either midrange voltage floating Software Mode, contents register determine operation mode.
Host Mode Operation
LXT350 operates Host Mode when MODE High. Host Mode microprocessor accesses controls transceiver through data port using internal registers. outputs (RPOS/RNEG RDATA) valid rising edge RCLK Host Mode there eight control status registers- five read/write three read-only registers. LXT350 accesses them through serial interface (SIO). LXT351 provides this access using 8-bit parallel interface (PIO). host processor/controller completely configure device well full diagnostic/status report through PIO. Only clocks data Bipolar Mode BPV/Logic Error insertions Unipolar QRSS Mode need provided directly input pins. Similarly, recovered clock, data, BPV/Logic Error occurrences available only output pins. other mode settings diagnostic information available through data port. Table shows address used access each register LXT350 LXT351, respectively. Table summarizes control status registers labels each they contain. Tables through identify bits each register.
Hardware Mode Operation (LXT350 Only)
LXT350 operates Hardware Mode when MODE left open Low. Hardware Mode individual pins access control transceiver. outputs (RPOS/ RNEG RDATA) valid rising edge RCLK. There some advanced functions provided only Host Mode. Interrupt (INT), detection indicator, open indicator CLKE functions some features available Host Mode.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Table Serial (LXT350) Parallel (LXT351) Port Register Addresses
Register Name Control Control Control Interrupt Clear Transition Status Performance Status Control
"don't care". Abbr
Serial Port (A7-A1)
Address1
Parallel Port (A7-A0)
x010000 x010001 x010010 x010011 x010100 x010101 x010111
x010000x x010001x x010010x x010011x x010100x x010101x x010111x
Table Register Addresses Names
Register Name Control Control Control Interrupt Clear Transition Status Performance Status Control reserved2 reserved2 reserved2 reserved2 COL32CM LOS2048 ZEROV CODEV reserved2 BIST DFMO reserved2 QRSS reserved2 ESUNF ESOVR TDFMO reserved2 TQRSS TAIS reserved2 TLOS Type JASLE1 RESET JA6HZ CESU JASEL0 EPAT1 PCLKE1 CESO ENCEB EPAT0 SBIST CDFMO UNIENB ETAOS reserved2 reserved2 EALOOP ES64 CAIS
ELLOOP ERLOOP ESCEN ESJAM
EQZMON reserved2 reserved3 CQRSS
reserved2 CLOS
CR3.PCLKE available only LXT351; LXT350, this zero. write registers, bits labeled reserved should (except note below) normal operation ignored read only registers. Write into this normal operation.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Control Register Read/Write, Address (A7-A1) x010000
Jitter Attenuation Name UNIENB ENCENB reserved, this ignore when reading. Enables Unipolar Mode insertion/detection BPVs. Enables B8ZS/HDB3 encoders/decoders; device enters Unipolar Mode pins change their unipolar functions. Jitter Attenuation Mode, selects jitter attenuation circuitry position data path disables right hand section table values. Equalizer Control codes (see Table 12). Function JASEL0 JASEL1 Position Transmit Receive disabled
JASEL0 JASEL1
Table Control Register Read/Write, Address (A7-A1) x010001
Pattern Name ERLOOP1 ELLOOP1 EALOOP ETAOS EPAT0 EPAT1 RESET Function Enables Remote Loopback (RLOOP) Enables Local Loopback (LLOOP) Enables Analog Loopback (ALOOP) reserved, this ignore when reading. Enables Transmit Ones (TAOS) Enables internal data pattern transmission. right hand section table values. RESET resets device state registers. EPAT0 EPAT1 Selected Transmit TPOS/TNEG Detect transmit QRSS
enable Dual Loopback (DLOOP), both ERLOOP ELLOOP
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Control Register Read/Write, Address (A7-A1) x010010
Name ESJAM ESCEN ES64 SBIST PLCKE Description Disables Jamming Elastic Store Read Clock (1/8 bit-time adjustment over/underflow). Centers pointer difference (depending depth-clears automatically). Increases depth from bits. reserved-set normal operation. reserved-set normal operation. Starts Built-In Self Test. This meaningful only LXT351- LXT350, this PCLKE sets RPOS/RNEG valid rising edge RCLK. PCLKE sets RPOS/RNEG valid falling edge RCLK When JA6HZ changes bandwidth Jitter Attenuation Loop from (default)
JA6HZ
Table Interrupt Clear Register Read/Write, Address (A7-A1) x010011
Name CLOS CAIS CQRSS CDFMO CESO CESU Clears/Masks Interrupt. reserved, this normal operation. Clears/Masks Interrupt. Clears/Masks QRSS Interrupt. reserved-set this normal operation. Clears/Masks DFMO. Clears/Masks Overflow Interrupt. Clears/Masks Underflow Interrupt. Function
Leaving these bits masks associated interrupt.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Table Transition Status Register Read Only, Address (A7-A1) x010100
Name TLOS TAIS TQRSS TDFMO ESOVR ESUNF Function Loss Signal (LOS) changed since last clear interrupt occurred. reserved-ignore. changed since last clear interrupt occurred. QRSS changed since last clear QRSS interrupt occurred1. reserved-ignore. DFMO changed since last clear DFMS interrupt occurred. overflow status sticky bit2. underflow status sticky bit2.
QRSS transition indicates receive QRSS pattern sync loss. simple error QRSS pattern reported transition. Tripping overflow underflow indicator sets ESOVR/ESUNF status bit(s). Reading Transition Status Register clears these bits. Setting CESO CESU Interrupt Clear Register masks these interrupts.
Table Performance Status Register Read Only, Address (A7-A1) x010101
Name QRSS DFMO BIST Loss Signal (LOS) Status. reserved-ignore. Alarm Indicator (AIS) Status. QRSS Pattern Detect Status. reserved-ignore. Driver Open Indication. Built-In Self Test Status. reserved-ignore Function
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Control Register Read/Write, Address (A7-A1) x010111
Name CODEV ZEROV LOS2048 COL32CM Function Enables detection HDB3 code violation along with bipolar violations ZEROVs enabled). Enables detection four consecutive zeros HDB3 coding violation) along with bipolar violation ZEROVs enabled). Changes detection threshold from consecutive zeros (for operation) consecutive zeros operation) 2048 consecutive zeros either environment. Mode, changes "clear condition" criterion from 12.5% marks density (default) receipt consecutive marks. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading.
Serial Port Operation (LXT350 Only)
LXT350 operates Host Mode when MODE High. Figure shows data structure. registers accessible through 16-bit word: 8-bit Command/Address byte (bits A1-A7) subsequent 8-bit data byte (bits D0-7). determines whether read write operation occurs. Bits A6-1 Command/Address byte address specific registers (the address decoder ignores A7). data byte depends both value address register Command/Address byte. Host Mode provides latched interrupt output (INT). change state following bits Performance Status Register will drive Low: LOS, AIS, QRSS, DFMO. interrupt will also occur when there elastic store overflow underflow. When interrupt occurred, output pulled Low. output stage each consists only pull-down device, each requires external pull-up resistor. interrupt cleared when interrupt condition longer exists, host processor writes respective interrupt causing bit(s) Interrupt Register. Leaving these interrupt status bits masks that interrupt.
Host Mode also allows control serial data receive data output timing. clock edge (CLKE) signal determines when outputs valid, relative Serial Clock (SCLK) RCLK shown Table
Table CLKE Settings
CLKE Output RPOS RNEG RPOS RNEG High Clock RCLK RCLK SCLK RCLK RCLK SCLK Valid Edge Rising Rising Falling Falling Falling Rising
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure LXT350 Serial Interface Data Structure
Parallel Port Operation (LXT351 Only)
LXT351 address/control pins control pins compatible with both Intel Motorola address/data buses. Figures timing diagram each bus. device automatically detects timing based Intel Motorola microprocessor specifications. maximum recommended processor speed Intel device MHz; Motorola device, 16.78 MHz. Table summarizes control status registers LXT351. Tables through identify explain bits control registers. LXT351 provides latched interrupt output (INT). change state following bits Performance Status Register will drive Low: LOS, AIS, QRSS, DFMO. When interrupt occurred, output pulled Low. output stage consists only pull-down device, each requires external pull-up resistor. interrupt cleared when interrupt condition longer exists, host processor writes respective interrupt causing bit(s) Interrupt Register. Leaving these interrupt status bits masks that interrupt. received data output valid rising edge RCLK, when CR3.PCLKE data output valid falling edge RCLK when CR3.PCLKE There five read/write three read-only registers. Only bits A6-1 address byte valid. (The address decoder ignores bits A0.) Tables through show register address bits A7-1, without regard
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
APPLICATION INFORMATION
NOTE
Table Transmit Return Loss (2.048 Mbps)
EC3-1 Xfrmr/ 1:2/ Rload (pF) 1:2.3/ Return Loss (dB)
This application information design only. Table shows specification transmit return loss applications. (The G.703/CH specification Swiss Telecommunications Ministry specification.) Table shows transmit return loss values applications. Table shows receive return loss values.
Table Transmit Return Loss Requirements
Return Loss Frequency Band 51-102 102-2048 2048 3072 G.703/CH
Table Transmit Return Loss (1.544 Mbps)
EC3-1 Xfrmr/ 1:2/ 1:1.151/ Rload (pF) Return Loss (dB)
1:1.15 transmit transformer keeps total transceiver power dissipation level, 0.47 blocking capacitor must placed TTIP TRING.
Table Transformer Specifications LXT350/LXT351
Primary Inductance (minimum) Leakage Inductance (max) 0.80 0.80 0.80 1.10 Interwinding Capacitance (max) (maximum) 0.90 1.70 0.70 1.20 1.70 1.10 1.10 Dielectric1 Breakdown (minimum) 1500 VRMS 1500 VRMS2 (3000 VRMS) 1500 VRMS2 (3000 VRMS) 1500 VRMS2 (3000 VRMS)
Frequency 1.544 2.048 1.544/2.048
Turns Ratio 1:1.15 1:2.3
1.544/2.048
Some ETSI applications require dielectric breakdown voltage. Some applications require transformers guarantee performance extended temperature range (-40° +85° ETSI applications require dielectric breakdown voltage 3000 VRMS.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Recommended Transformers LXT350/LXT351
Tx/Rx Turns Ratio 1:1.15 Part Number PE-65388 PE-65770 PE-65351 PE-65771 0553-5006-IC 66Z-1308 671-5832 67127370 67130850 TD61-1205G TD67-1205G 1:2.3 PE-65558 8006-155 671-5792 PE-64936 PE-65778 67130840 67109510 TD61-1205 TD67-1205G HALO (combination Tx/Rx set) Schott Corp Pulse Engineering Fil-Mag Midcom Pulse Engineering HALO (combination Tx/Rx set) Bell-Fuse Fil-Mag Midcom Schott Corp Manufacturer Pulse Engineering
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Figure shows typical LXT350 application either environment. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely. Excessive capacitance will distort transmitted signals.
Figure Typical T1/E1 LXT350 Hardware Mode Application
2.048MHz/ 1.544
MCLK
TAOS LLOOP RLOOP
TCLK TPOS TNEG T1/E1 Framer RCLK RPOS RNEG
TCLK TPOS TNEG MODE TRSTE RCLK LXT350
From CMOS Control Logic
JASEL TTIP TRING
RPOS RNEG
NLOOP TVCC TGND
RTIP RRING
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Figure shows application using LXT350 Host Controlled Mode. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely. Excessive capacitance will distort transmitted signals.
Figure Typical T1/E1 LXT350 Host Mode Application
2.048MHz/ 1.544 MCLK CLKE TCLK TPOS TNEG T1/E1 Framer RCLK RPOS RNEG MODE TRSTE RCLK RPOS RNEG TCLK TPOS TNEG LXT350 SCLK TTIP NLOOP TVCC TGND RRING TRING RTIP Host
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Figure shows application using LXT351. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely.
Figure Typical T1/E1 LXT351 Application
2.048MHz/ 1.544 MCLK ALE/AS TCLK TPOS T1/E1 Framer TNEG RCLK RPOS RNEG TCLK TPOS TNEG RCLK RPOS RNEG TTIP TVCC TGND RRING TRING RTIP LXT351 RD/DS WR/R/W
(Intel Motorola)
AD0-7
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
TEST SPECIFICATIONS
NOTE minimum maximum values Tables Figures through represent performance spcifications LXT350 LXT351 guaranteed test, except where noted design.
Table Absolute Maximum Ratings
Parameter supply (reference GND) Input voltage, Input current, Storage Temperature ,TVCC TSTG CAUTION
Operation these limits permanently damage device. Normal operation these extremes guaranteed. TVCC must differ more than during operation. TGND must differ more than during operation. Transient currents will cause latch-up. TTIP, TRING, TVCC, TGND withstand continuous currents
-0.3
Units
Table Recommended Operating Conditions
Parameter Supply
VCC,TVCC
4.75
Typ1
5.25
Units
Test Conditions
Ambient Operating Temperature Total Power Dissipation3
100% mark density mark density 100% mark density mark density
Typical figures design only; guaranteed subject production testing. TVCC must differ more than Power dissipation while driving load over operating range operation load operation. Includes power dissipation device load. Digital levels within supply rails digital outputs driving capacitive load.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT350 Electrical Characteristics (over recommended operating range)
Parameter Digital Pins High level input voltage (pins 1-4, 23-25) level input voltage (pins 1-4, 23-25) High level output voltage (pins 6-8, level output voltage (pins 6-8, Three-state leakage current (all outputs) Mode Input Pins High level input voltage (pins 26-28) Midrange output voltage (pins 26-28) level input voltage (pins 26-28) Input leakage current (pins 26-28) TTIP/TRING Leakage current power down tristate IOUT -400 IOUT Units Test Conditions
Functionality depends mode. Host Mode Hardware Mode description Output drivers will output CMOS logic levels into CMOS loads. alternative supplying these pins, they left open.
Table LXT351 Electrical Characteristics (over recommended operating range)
Parameter Digital Pins High level input voltage (pins 1-5, 9-12, 2328) level input voltage (pins 1-5, 9-12, 2328) High level output voltage (pins 6-8, 11,23, level output voltage (pins 6-8, 11,23, Input leakage current IOUT -400 IOUT Units Test Conditions
Functionality pins depends mode. Host Mode description. Output drivers will output CMOS logic levels into CMOS loads.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Analog Characteristics (over recommended operating range)
Parameter Recommended output load TTIP/TRING Output Pulse Amplitudes Jitter added transmitter2 Broad Band Receiver Sensitivity Allowable consecutive zeros before (T1) Allowable consecutive zeros before (E1) Input jitter tolerance (T1) Input jitter tolerance (E1) Jitter attenuation curve corner frequency Driver Output Impedance Receiver Input Impedance Receive Return Loss (E1) kHz3 2.048 MHz3 2.048 3.072 MHz3
Typ1
0.02 0.025 0.025 0.05
Units
Test Conditions
1024 1.431
line AT&T 62411 line (G.823) selectable data port
RTIP RRING
Typical figures design only; guaranteed subject production testing. Input signal TCLK jitter-free. Jitter Attenuator receive path disabled. Guaranteed characterization; subject production testing. Circuit attenuates jitter dB/decade above corner frequency.
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure 2.048 Mbps Pulse (See Table
(244+25)
NOMINAL PULSE
100%
(244-
(244-25)
(244+244)
Table 2.048 Mbps Pulse Mask Specifications
Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio positive negative pulse amplitudes center pulse Ratio positive negative pulse amplitudes nominal half amplitude ±0.30 95-105 95-105 Coax 2.37 ±0.237 95-105 95-105 Unit
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Figure 1.544 Mbps Pulse (DSX-1) (See Table
Normalized Amplitude
DSX-1
-0.5 Time
Unit Intervals)
-0.5
Table 1.544 Mbps (DSX-1) Pulse Mask Corner Point Specifications
DSX-1 Template (per ANSI 102-1993) Minimum Curve Time (UI) -0.77 -0.23 -0.23 -0.15 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Amplitude -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 Maximum Curve Time (UI) -0.77 -0.39 -0.27 -0.27 -0.27 0.27 0.35 0.93 1.16 Amplitude 0.05 0.05 0.80 0.80 1.15 1.05 1.05 -0.07 0.05 0.05
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Master Transmit Clock Timing Characteristics Operation
(over recommended operating range) (see Figure Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG hold time MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT Typ1 1.544 1.544 ±100 Units Notes must supplied
Typical figures design only; guaranteed subject production testing.
Table Master Transmit Clock Timing Characteristics Operation
(see Figure Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG hold time MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT Typ1 2.048 2.048 ±100 Units Notes must supplied
Typical figures design only; guaranteed subject production testing.
Figure Transmit Clock Timing
TCLK
tSUT
TPOS TNEG
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table Receive Timing Characteristics Operation (See Figure
Parameter Receive clock duty cycle Receive clock pulse width Receive clock pulse width high Receive clock pulse width low1,3 RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold time RLCKd tPWH tPWL tSUR Typ1 Units
Typical figures design only; guaranteed subject production testing. RCLK duty cycle widths will vary according extent received pulse jitter displacement. RCLK duty cycles worst case jitter conditions. Worst case conditions guaranteed design only.
Table Receive Timing Characteristics Operation (See Figure
Parameter Receive clock duty cycle Receive clock pulse width
RLCKd tPWH tPWL tSUR
Typ1
Units
Receive clock pulse width high Receive clock pulse width
RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold time
Typical figures design only; guaranteed subject production testing. RCLK duty cycle widths will vary according extent received pulse jitter displacement. RCLK duty cycles worst case jitter conditions (0.4 clock displacement 1.544 MHz.) Worst case conditions guaranteed design only.
Figure 19:Receive Clock Timing
RCLK tPWH tSUR RPOS RNEG
LXT350 Host Mode-CLKE High LXT351 CR3.PCLKE High
tPWL
tSUR RPOS RNEG
LXT350 Host Mode-CLKE= Hardware Mode LXT351 CR3.PCLKE
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT350 Serial Timing Characteristics (See Figures
Parameter Rise/fall time-any digital output SCLK setup time SCLK hold time SCLK time SCLK high time SCLK rise fall time falling edge SCLK rising edge Last SCLK edge rising edge inactive time SCLK valid time SCLK falling edge rising edge high-Z tCDH tCCH tCWH tCDV tCDZ Typ1 Units Parameter Load
Typical figures design only; guaranteed subject production testing.
Figure LXT350 Serial Data Input Timing Diagram
tCWH tCCH tCDH
DATA BYTE
SCLK
tCDH
CONTROL BYTE
Figure Serial Data Output Timing Diagram
CLKE SCLK CLKE High SCLK tCDZ tCCH tCDZ tCCH
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT351 Intel Parallel Timing Characteristics (See Figure
Parameter pulse width Address valid falling edge falling edge address hold time falling edge falling edge falling edge falling edge falling edge falling edge falling edge falling edge pulse width falling edge data valid Data hold time after rising edge rising edge rising edge rising edge address valid hold time after rising edge pulse width Data setup time before rising edge Data hold time after rising edge rising edge rising edge hold time after rising edge TLHLL TAVLL TLLAX TLLRL TLLWL TCLRL TCLWL TRLRH TRLDV TRHDX TRHLH TRHAV TRHCH TWLWH TDVWH TWHDX TWHLH TWHCH Units Test Conditions
Figure LXT351 Timing Diagram Intel Address/Data
TCLWL TCLRL TWHCH TRHCH
TLHLL TLLAX TAVLL
TLLRL TLLWL
TRHLH TWHLH TRLRH TRLDV TRHAV TRHDX
AD0-7_R
TWLWH
TDVWH
TWHDX
AD0-7_W
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LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation Table LXT351 16.78 Motorola Parallel Timing Characteristics
(See Figure Parameter rising edge rising edge high pulse width Address valid setup time falling edge falling edge Address valid hold time falling edge falling edge falling edge falling edge pulse width falling edge data valid Data hold time after rising edge falling edge falling edge Data setup time before rising edge Data hold time after rising edge hold time after rising edge hold time after rising edge DSHASH TASHASL TAVASL TASLAX TASLDSL TCSLDSL TDSLDSH TDSLDV TDSHDX TRWLDSL TDVDSH TDXDSH TDSHRWH TDSHCSHV Units Test Conditions
Figure LXT351 Timing Diagram Motorola Address/Data
TASHASL TAVASL TASLDSL TASLAX TDSHASH TDSLDSH DVDSH DXDSH TDSHRWH TCSLDSL DSHCSH
TRWLDSL R/W_Read AD0-7_Read R/W_Write AD0-7_Write TDSLDV
TDSHDX
2-193
LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Figure Input Jitter Tolerance (Typical)
Typical Input Jitter Tolerance
10000 1000
Jitter
LXT350/LXT351Device Typical Jitter Tolerance Loop Mode
62411 1990
Frequency
Typical Input Jitter Tolerance
1000
LXT350/LXT351Device Typical Jitter Tolerance Loop Mode
Jitter
G.823
1993
Slope equivalent dB/decade
Frequency
2-194
LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter Attenuation
Figure Jitter Transfer Performance (Typical)
G.736 Template
-19.5
Gain
-19.5 LXT350/LXT351 Device Performance
Frequency
Figure Jitter Transfer Performance (Typical)
62411
Gain
-33.8 62411 Template LXT350/ LXT351 Device Performance
Frequency
2-195

LXT350/351 Integrated T1/E1 Transceivers With Crystal-less Jitter

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