Guidelines Printed Circuit Board Layout MT8910 March 1992 In
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Guidelines Printed Circuit Board Layout MT8910
March 1992
Introduction
MT8910 Digital Subscriber Line Interface Circuit (DSLIC) most complex integrated circuits ever developed telecommunication applications. performance this complex device incorporating both analog digital circuitry maximized proper design printed circuit board. This application sheet provides guidelines design PCBs holding DSLICs.
DSLIC's internal circuit layout carefully done minimize interference between analog digital sections. configuration also selected accordingly, reduce crosscoupling effects between sections.
Suggested Ground Supply Connections
DSLIC's Internal Layout Configuration
semiconductor process used DSLIC does permit full isolation analog digital circuitry same silicon die. shown Fig. analog digital ground pins, remain isolated long differential voltage between them does exceed 0.4V. supply pins AVDD internally connected through substrate, connection between them behaves resistive short. This direct bearing decoupling circuit because does allow fully independent power supplies. separate power supplies used, then differential voltage between supplies power-up damage internal structure DSLIC.
Proper grounding, power supply distribution decoupling techniques printed circuit board have impact total performance system associated with DSLIC. suggested that external components, tracks circuits board (see Fig. follow similar separation between digital analog sections inside DSLIC) reduce effect interference another. Grounding power supply distribution depends upon number metallic layers printed circuit board. case two-layer boards, recommended separate power distribution networks, analog other digital circuitry. Both distribution networks MUST CONNECTED TOGETHER single place board (usually edge connector) protect DSLIC from being damaged. Two-layer PCBs will perform well density application, case compact design, fourlayer PCBs with separate "GROUND" "+5V" layers highly recommended. Experiments show that solid power ground planes provide very good performance. useful even further split "GROUND" plane into "ANALOG GROUND" "DIGITAL GROUND" within same physical plane. similar split also planned "+5V" supply plane. Recommended decoupling shown Applications section MT8910 data sheet. Both figures show that VRef (pin Bias (pin pins should decoupled AVSS with capacitors. Special considerations should given when selecting decoupling capacitors because capacitors good decoupling. most common mistake high quality capacitors with very losses. Unfortunately, this type capacitor, instead suppressing high frequency interference, resonates conjunction with
MT8910
AVSS
AVDD
Figure Internal Arrangement Power Supply Distribution
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inductance tracks. recommend decoupling capacitors with high dielectric losses like ones based dielectric. this value available then alternative choice electrolytic tantalum capacitor parallel with 0.1µF ceramic capacitors (with dielectric). case line cards where many DSLICs same board, each them should have decoupling capacitors (+5V) (+5V). These capacitors should placed very close power supply pins effective.
Application Sheet
MH89101
MT8910
Figure Example Components Layout Board
ANALOG CIRCUIT AREA DIGITAL CIRCUIT AREA
Components List: Transformer TPW4671 D1-D4 Protection Diodes MUR105 VRef Decoupling Capacitor VBias Decoupling Capacitor AVDD Decoupling Capacitor Decoupling Capacitor Xtal 10.24 Crystal
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