CONTENTS MVIP MVIP Overview History Purpose Architecture MVIP MVI

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CONTENTS MVIP MVIP Overview History Purpose Architecture MVIP MVI

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MSAN-148 Application Note Introduction MVIPand Details Implementation using MT90810
CONTENTS MVIP MVIP
Overview History Purpose Architecture MVIP MVIP Digital Switching MVIP Digital Clocking MVIP Software MVIP Interface Chip MT90810 1.4.1 Multi-chassis MVIP Potential Growth Products Market
ISSUE
September 1994
Overview MVIP (Multi-Vendor Integration Protocol) provides coherent approach building solutions worldwide markets merging computing communications technologies under open architecture. MVIP ensures interoperability among telephone-based resources (such trunk interfaces, voice, video, fax, text-to-speech, speech recognition) within computer chassis individual networked configuration. architecture both supported driven industry-wide group over companies worldwide licensees MVIP technology. History Mitel Semiconductor initially defined ST-BUS (Serial Telecom Bus) provide effective means communication information transfer between functional modules. required interface this designed into ST-BUS compatible components such digital switches phone chips. telecommunications computer technologies merged, long before applications devices grew include personal computer (PC). Now, there requirement provide means communication between physical cards within chassis. Based ST-BUS interface associated clocks signalling, MVIP developed. MVIP vendor-independent standard; thus name "multi-vendor". MVIP standard cooperatively developed group companies, including Mitel, address problem interoperability today's call processing environment. Today, MVIP widely deployed industry standard that ensures interoperability simple integration multiple technologies from different vendors. Purpose MVIP provides framework within which manufacturers computers communications systems plan hardware software products, complete systems customer solutions meet current market demand future market directions. broad-based, worldwide adoption
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MT90810 (FMIC)
Overview MT90810 Support circuitry Distributed Switching Advantage Applications 2.4.1 Glitch-free Clock Reconfiguration 2.4.2 Interactive Voice Response (IVR) System 2.4.3 Meeting Network Specifications 2.4.4 Capability Device Throughput Delay Microprocessor Accesses
References
MSAN-148
Application Note
intchip
itch
inthip itch
software
Figure MVIP System Elements manufacturers systems developers provides proven, extensible platform upon which end-users plan implementation their near-term longterm telephony-enhanced solutions. Architecture MVIP architecture specifies following five integral elements: bus, switching, digital clocks, software interface chip. MVIP MVIP standard digital telephony that permits connections different technologies within chassis. MVIP consists 2.048 Mb/s serial streams eight streams eight streams associated clock signals. channels, kb/s each, time division multiplexed onto DSi/DSo stream. direction DSi/DSo1 channel-pair uniquely determined. Therefore, combination input output channels multiplexed onto single DSi/DSo stream. complete MVIP bus, however, will always carry total input channels output channels fullduplex channels (refer Figure "The MVIP serial streams" serial streams referred MVIP streams ST-BUS streams they electrically compatible with Mitel's ST-BUS specification inter-chip communications. Application Note MSAN 126, ST-BUS Generic Device
DSi/DSo channel pair refers channel {0,1,2,.31}) stream (n={0,1,2,.7}) corresponding channel stream A-270
Specification (Rev.B), provides detail explanation ST-BUS. MVIP carries serial streams between boards ribbon cable allowing cards exchange information directly. therefore opens architecture voice, video, data applications that would otherwise over burden processor with data transfers. MVIP equivalent extra backplane that capable routing circuit switched data. MVIP Digital Switching MVIP architecture supports advanced distributed digital circuit-switching within under software control. Switching capacity distributed amongst MVIP-compatible boards. MVIP defines three levels switching. order increasing capabilities, they are: MVIP Switching Compatible device board that MVIP Switching Compatible capable making full-duplex connections. provide interface only subset complete MVIP Bus. switch blocking capable connecting channel MVIP channel driving local channel from MVIP channel. MVIP Standard Switching Compliant device board that MVIP Standard Switching Compliant capable making fullduplex connections. must provide interface complete MVIP Bus. switch blocking capable connecting channel MVIP channel driving local channel from MVIP channel.
Application Note
MSAN-148
channels 0-31 stream
channels 0-31 stream
DSi0 DSi1 DSi2 DSi3 DSi4 DSi5 DSi6
DSo0 DSo1 DSo2
Switch Matrix
DSo3 DSo4 DSo5 DSo6
DSi7
DSo7
Bidirectional streams DSi0-7
Bidirectional streams DSo0-7
Figure MVIP Serial Streams MVIP Enhanced Switching Compliant device board that MVIP Enhanced Switching Compliant capable making fullduplex connections well providing channel pair direction control MVIP channel pairs MVIP Bus. must, therefore, provide interface complete MVIP Bus. 256x256 non-blocking switch. MVIP Digital Clocking MVIP system, clock source chosen drive MVIP clock signals called master clock. master clock must source following three clocks: C4(4 MHz), C2(2 MHz) F0(8 framing signal). timing signals passed across MVIP from master clock, configured upon power-up, under software control. device board that provides network interface function should capable driving MVIP clock lines, that become master clock. choice drive receive MVIP clock signal selectable, either installation time under software control. MVIP software standards include Connection Control Standard which describes collection software entities that cooperate establish terminate circuit-switched connections between multiple devices, multiple MVIP cards, mutiple expansion buses, across more computer chassis (refer Section 1.4.1 Multichassis MVIP details). standard specifies services objects provided Application Programming Interface (API) order allow connections established terminated abstract fashion. These services include making breaking connections, configuring network MVIP cards, monitoring maintaining status connections. MITEL's Connection Masteris software product that implements Connection Control Standard. Connection Master tool designers systems variety MVIP cards their systems. Connection Master interacts with circuit switches multiple MVIP cards make connections resolve switching contention. Connection Master supports multichassis MVIP allowing resources distributed throughout network. Furthermore, interfaces between applications makes connections such that simple, chassis applications become networked applications.
MVIP Software addition hardware standards, MVIP defines software interface standard access MVIP hardware elements such switching MVIP clock timing. standard specifies functionality independent programming language.
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MSAN-148
MVIP Interface Chip MT90810 Mitel's MT90810, Flexible MVIP Interface Circuit (FMIC), provides cost-effective solution complete MVIP compliant interface between MVIP wide variety processors, telephony interfaces other circuits. MT90810 specifically designed meet switching requirements MVIP Bus. Device details found MT90810 datasheet. 1.4.1 Multi-chassis MVIP MVIP architecture scalable interconnection switching telephony traffic between computer nodes. Multi-chassis MVIP supports interconnection MVIP chassis facilitates interoperation with between other buses. multi-chassis architecture includes standard Connection Control API. provides common software control alternative physical media (see Table supports bus, ring star interconnection topologies. example, Figure shows implementation multi-chassis MVIP using Mitel's FIM. Potential Growth MVIP provides potential opportunity powerful growth. MVIP specifies multi-chassis architecture scalable interconnection switching telephony traffic between computer nodes. defines comprehensive switching fabric that reconfigured systems grow from board multi-board well chassis multichassis. Multi-Chassis MVIP supports interconnection MVIP-based computer chassis, well MVIP chassis with other chassis supporting variation kb/s traffic. Furthermore, MVIP focuses easy inter-operation with existing equipment therefore provides interface implementation assist interconnection proprietary equipment.
Application Note
Products Market MVIP allows developers users provide broad range MVIP compatible board-level products, end-user products, systems integrated solutions. Driven market demand, MVIP community been creating products thus continuously expanding existing base products. date, thousands MVIP compatible products have been shipped MVIP licensed companies.
MT90810 (FMIC)
Overview MT90810, otherwise known Flexible MVIP Interface Circuit (FMIC), MVIP (MultiVendor Integration Protocol) compliant device. provides complete, MVIP interface between MVIP wide variety processors, telephony interfaces other circuits. MT90810's built-in digital time-slot switch provides MVIP Enhanced Switching between full MVIP combination full duplex local channels kb/s each. microprocessor port allows real-time control switching programming device configuration. device, with enhanced switching capability, well suited distributed systems whereby resources have switching capability have rely central switching resource. MT90810's internal clock circuitry, including both analog digital phase-locked loops, supports MVIP clock modes. device therefore able provide glitch-free clock reconfiguration event network failure synchronizing alternate network reference source. MT90810's local serial interface supports rates 2.048, 4.096 8.192 Mb/s, channel message mode, additional control stream, well parallel through microprocessor port.
Link name
Link type
Number kb/s timeslots
Maximum number chassis supported
Maximum distance
mesh other point-to-point links Mitel Twisted-pair copper FDDI-II fiber copper SDH/SONET fiber over fiber 1408 1536 2400/4800 hundreds hundreds limited metres many kilometres many kilometres kilometres
Table Physical Implementations Multi-Chassis MVIP (MC-MVIP)
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Application Note
MSAN-148
EDtr*x
copper fiber
Local T1/E1 Network
Figure Typical Implementation Multi-Chassis MVIP
Note: detailed illustration Matrix found MT8985 datasheet.
Furthermore, device's programmable group output framing signals local output clocks used provide appropriate frame clock pulses drive other local serial buses such GCI. MT90810 designed applications where voice data samples encoded into individual kb/s timeslots. such applications, MT90810 allows cost effective implementation non-blocking channel switch. MT90810 facilitates implementation complete MVIP interface. MT90810 Support circuitry Figure "MT90810 Support circuitry" shows MT90810 with suggested support circuitry: I/Os connected MVIP connector through series 47ohm resistor networks. MVIP clock framing signals connect directly device. terminations MVIP clock lines jumper-selectable, specified MVIP Standard.
buffered microprocessor interface signals from interface connect directly MT90810. this example, grounded MT90810's microprocessor interface INTEL non-multiplexed mode. used generate interrupts MT90810's interface readily operates with external Controller provide transfers local channels. local interface, local output clocks programmable framing signals used interface other devices. four header provides access JTAG pins MT90810 boundary scan board connectivity testing. Inset shows interface circuitry: 16.384 crystal connected across crystal oscillator pins This crystal oscillator provides time base MT90810 when programmed become timing master MVIP bus.
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MSAN-148
MVIP Header
resistors
Application Note
1.8k 1.8k .001µF .001µF
0.1µF
0.1µF
0.1µF
Local Serial Device Interface
LDO0 DSi7 DSo7 FGB9 DSi6 DSo6 DSi5 DSo5 DSi4 DSo4 FGA9 DSi3 DSo3 DSi2 DSo2 FGB8 DSi1 DSo1 DSi0 DSo0 FGA8 SEC8K FGB7
FGA10 LDO1 LDO2 FGB10 LDO3 LDI0 LDI1 LDI2 LDI3 EX8_KA EX8_KB FRAME CLK8 FGA11 CLK4 CLK2 FGB11 FGA0
MT90810 PQFP
DREQ1 DREQ0 DACK1 DACK0 FGA7 FGB6 FGA6
external controller
0.1µF
AD0-7
FGA1 FGA2 FGA3 CSTo FGA4 FGB0 FGB1 FGB2 FGB3 FGB4 X1/CLKIN RESET FGA5 VCO_VSS PLL_LO PLL_LI VCO_VDD WR/[R/W] RD/[DS] FGB5 RDY/[DTACK]
A0,1
PCRESET 74HCT04 IOCHRDY 74HCT125 IOWR
JTAG Header
interface Inset
interrupt interface
SA0-15
A0,1
IORD
address selector
switches
D0-7
AD0-7
data buffer
Inset 33µF tant. 16.384MHz 4.7k 18pF 18pF 0.1µF Keep this circuitry tight place close FMIC
Interface
Figure MT90810 Support Circuitry
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VCO_VSS
PLL_LO PLL_LI VCO_VDD
Application Note
make standard lead-lag loop filter phase lock loop circuitry MT90810. MT90810 extremely high gain about volt. Consequently, components making loop filter should placed close possible MT90810. MT90810 internal modulated variations power supply. Consequently, power supply heavily filtered This pass filter eliminates high frequency power supply fluctuations. frequency fluctuations tracked response time loop filter.
MSAN-148
Distributed Switching Advantage MT90810 enables system designer create distributed switching system easily cost effectively. Central Switching central switching system, resources only transmit receive from other resources through central switching resource. That channels used establish single channel communication link between resources from resource central switch another from central switch resource. Furthermore, broadcasting data various resources inefficient since application must duplicate data different channel each resource bandwidth costly.
Migrating from centralized switching.
itch
link itio
Local Network
distributed switching.
niti
link
Local Network
Figure MT90810 Supports Migration towards Distributed Switching
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MSAN-148
Distributed Switching Distributed switching eliminates dedicated switching resources allows more flexibility extensibility system configuration. distributed switching system, resources transmit receive from other resource without depending central switching resource. Switching reduced single stage. Applications broadcast data efficiently many resources using single available channel, thus saving data bandwidth. Applications 2.4.1 Glitch-free Clock Reconfiguration Figure illustrates application whereby MT90810 used support glitch-free clock reconfiguration event link failure. shown, MT90810's MVIP master clock programmed frequency lock three 8kHz timing reference clocks EX8KA, EX8KB SEC8K. MVIP master clock initially frequency locked EX8KA, that 8kHz extracted from local T1/E1 link. event failure link1, MT90810 Dual T1/E1 Card will remain master MVIP bus, reference will come from
Application Note
different source. MT90810 will frequency lock EX8KB, reference derived from local T1/E1 link2. then, link2 also fails, MT90810 Dual T1/E1 Card still remain MVIP master. frequency lock SEC8K, secondary 8KHz derived from local T1/E1 link3 passed from single T1/E1 card over MVIP bus. MT90810 Dual T1/E1 card must modes (depending 8kHz source selected) whereby frequency phase locked external 8kHz. This enables device frequency lock various sources without causing glitch output clocks. phase difference between MVIP clocks system clocks handled slip buffer within MH89760/90B. MT90810 single T1/E1 card must mode that drive SEC8K clock slave MVIP bus. 2.4.2 Interactive Voice Response (IVR) System Figures
MVIP
SEC8K
FMde
link
oter
0/90B
Local T1/E1 Network
Figure MT90810 Supports Glitch-free Clock Reconfiguration
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Application Note
MSAN-148
T1/E1
Network T1/E1
T1/E1
Figure in-between Network PBX. Implementation uses MT90810 provide MVIP interfaces.
itio
T1/E1
Network T1/E1
Figure behind PBX. Implementation uses MT90810 provide MVIP interfaces.
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MSAN-148
2.4.3 Meeting Network Specifications MT90810's digital analog combination meet some international standards jitter performance. cases where strict jitter specifications must met, external PLL, such MT9042 (refer Figure required internal analog should disabled. MT9042 meets AT&T TR62411 (ACCUNET® T1.5) ETSI specifications 1.544 (T1) 2.048 (E1) input reference.
Application Note
2.4.4 capability MT90810's interface readily operates with external controller provide local channels it's local serial interface. Figure illustrates application where MT90810 used send compressed video signals from video compressor card, host bus, T1/E1 link. shown illustration, dual port required avoid contention between controller host bus. this application, MT90810 switching video signals through switch matrix. Instead, performing fast parallel serial conversion compressed video signals output T1/E1 link. Control signalling provided HDLC through MVIP interface. This will require that MVIP stream dedicated perform signalling functions.
MVIP
SEC8K
slave
aster
60/9 60/9
Network
Figure trunk card using MT90810 MT9042 meet stringent network specifications
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Application Note
MSAN-148
MVIP
other MVIP resources
Card Stor
aste
link
HOST
ller
Local T1/E1 Network
Figure Video Application using MT90810's capability Device Throughput Delay delay through 90810 results when channel information transferred from timeslot input stream another timeslot output stream. input information must first written data memory, where awaits next available timeslot allocated output. delay result stages through which data must pass into device well ordering memory access cycles. MT90810 non-blocking switch. This implies that during each timeslot, device must read write, from, input output streams, that input channels switched output channels. Reading from input streams involves converting data from serial parallel, latching then writing into MT90810s data memory. Writing output streams involves reading from MT90810s data memory, latching then converting from parallel serial data. order which channel information written into read from data memory listed Table "Memory Access Cycles within Mb/s timeslot" shown table, device cycles through reads writes from every MVIP local stream during Mb/s timeslot. FMIC state number refers number clock cycles within Mb/s timeslot. Mb/s timeslot which equal clock cycles FMIC states. connection data memory runs half speed FMIC state machine. Memory therefore accessed every other state. stages device determine when channel information written read from data memory. Channel information shifted into input shift registers during timeslot allocated channel latched written data memory timeslot immediately following. Conversely, channel information always read from data
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MSAN-148
FMIC State Memory Access Cycle MVIP stream write MVIP stream read LOCAL stream write microprocessor access cycle LOCAL stream read MVIP stream write MVIP stream read microprocessor access cycle MVIP stream write MVIP stream read LOCAL stream write microprocessor access cycle LOCAL stream read MVIP stream write MVIP stream read microprocessor access cycle FMIC State
Application Note
Memory Access Cycle MVIP stream write MVIP stream read LOCAL stream write microprocessor access cycle LOCAL stream read MVIP stream write MVIP stream read microprocessor access cycle MVIP stream write MVIP stream read LOCAL stream write microprocessor access cycle LOCAL stream read MVIP stream write MVIP stream read microprocessor access cycle
Table Memory Access Cycles within Mb/s Timeslot memory latched output during timeslot immediately preceding shifted shift registers timeslot allocated. This ordering events implies that information entering MT90810 cannot leave same timeslot timeslot immediately following. Information that output same timeslot input, relative frame pulse, will output following frame. Similarly, channel information switched timeslot immediately following input timeslot will output timeslot allocated frame later. Examples channels being switched channels immediately following are: switching from Channel Channel Channel Channel (all independent stream changes). minimum delay that information entering leaving MT90810 experience depends data rate selected serial streams. Mb/s data rates, minimum delay Mb/s timeslots. Whether this minimum delay achievable depends which streams channel information enters leaves This order which information read written into data memory shown Table Certain input output stream combinations will allow channel information leave timeslots after channel information received (refer Table Note that combinations listed have output stream access occurring after input stream access within Mb/s timeslot.
Input Stream MVIP stream MVIP stream MVIP stream MVIP stream MVIP stream MVIP stream MVIP stream
Output Stream MVIP stream LOCAL stream MVIP stream LOCAL stream MVIP stream LOCAL stream MVIP stream LOCAL stream MVIP stream LOCAL stream MVIP stream LOCAL stream MVIP stream LOCAL stream
LOCAL stream MVIP stream LOCAL stream LOCAL stream MVIP stream LOCAL stream LOCAL stream MVIP stream LOCAL stream LOCAL stream MVIP stream
Table Input Stream Output Stream Combinations that provide minimum Channel Delay Mb/s data rates, minimum delay three Mb/s timeslots Mb/s data rates minimum five Mb/s time slots. Tables summarize throughput delay values output stream access occurring before after input stream access various rates. shaded areas tables highlight minimum delay
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Application Note
MSAN-148
-(n-m) t.s. -(n-m) t.s. m=n, (m-n) t.s. (m-n) t.s. (m-n) t.s. m=n+2 (m-n) t.s. (m-n) t.s. (m-n) t.s. m=n+3, (m-n) t.s. (m-n) t.s. (m-n) t.s. m>n+4 (m-n) t.s. (m-n) t.s. (m-n) t.s.
Input/Output Rate 2.048 Mb/s (t.s. 4.096 Mb/s (t.s. 1.95
8.192 Mb/s (t.s. 0.975 -(n-m) t.s.
Table Throughput Delay Values Output Stream Read occurring after Input Stream Write
Input/Output Rate 2.048 Mb/s (t.s. 4.096 Mb/s (t.s. 1.95
-(n-m) t.s. -(n-m) t.s.
m=n, n+1, (m-n) t.s. (m-n) t.s. (m-n) t.s.
m=n+3, (m-n) t.s. (m-n) t.s. (m-n) t.s.
m=n+5.n+8 (m-n) t.s. (m-n) t.s. (m-n) t.s.
m>n+8 (m-n) t.s. (m-n) t.s. (m-n) t.s.
8.192 Mb/s (t.s. 0.975 -(n-m) t.s.
Table Throughput Delay Values Output Stream Read occurring before Input Stream Write
Notes: output channel; input channel t.s.= timeslot used synonymously with channel 125µs frame
achievable each rate, under condition specified. summary, delay through MT90810 dependent input output stream, source destination channel, well data rate. device therefore, best suited applications where voice data samples encoded into individual kb/s timeslots where maintaining sequence integrity between input output channels required. applications where concatenated grouped time slots used carry voice, video and/or data, MT90810 must programmed correctly, using tables above, maintain frame integrity. alternative,
applications where sequence integrity concatenated N*64 kb/s channels maintained, MT8985 Enhanced Digital Switch highly recommended. device provides perchannel selection between variable constant throughput delay designed specifically hyperchannel switching. Microprocessor Accesses MT90810 data sheet specifies microprocessor fast slow access time table titled Electrical Characteristics Microprocessor Timing". fast tACC applies register accesses slow tACC applies memory accesses. Slow memory accesses occur because MT90810 only
CSTo output timing LD0ch0 LD1ch0 LD2ch0 LD3ch0AA LD0ch1 LD1ch1 LD2ch1 LD3ch1 LD0ch2 LD1ch2 LD2ch2 LD3ch2AALD0ch3
Local timing bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 LD0-3, channel LD0-3, channel LD0-3, channel LD0-3, channel
Figure CSTo Timing relative Local Timing
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MSAN-148
allocates discrete access windows microprocessor memory access. shown Table microprocessor access windows occur every four clock cycles eight FMIC states). microprocessor runs asynchronously FMIC state machine must therefore wait until designated state access memory. External Control Using CSTo Connection memory high local channels includes CSTo bit. inverted value this CSTo output sequentially CSTo stream order shown Figure "CSTo timing relative local timing" CSTo stream, like MVIP streams, divided into frames that bits long. Each CSTo occupies bits CSTo stream because there twice many bits stream there local channels with associated CSTo bits. four CSTo bits that correspond channel timeslot output timeslot preceding that
Application Note
CSTo bits perform external control functions, advance, channels they correspond (see Figure 11). CSTo bits, example, used control loop back circuitry. CSTo stream enable disable driver specific channel looped back. This function ideal performing system level diagnostics and/or delay line applications. CSTo stream also used sychronize microprocessor local stream timing notifying microprocessor when predetermined timeslot local stream timing will occur.
References
Datasheets: MT9042 Global Digital Trunk Synchronizer MT8985 Enhanced Digital Switch MT8980D Digital Switch MT90810 Flexible MVIP Interface CIrcuit MT90710 Fiber Interface (FIM1) MSAN-126 ST-BUS Generic Device Specification (Rev.B).
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CONTENTS MVIP MVIP Overview History Purpose Architecture MVIP MVI

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