LXT360/361 Integrated T1/E1 LH/SH Transceivers DS1/DSX-1/CSU NTU/

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LXT360/361 Integrated T1/E1 LH/SH Transceivers DS1/DSX-1/CSU NTU/

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Preliminary Information APRIL, 1996
LXT360/361 Integrated T1/E1 LH/SH Transceivers
DS1/DSX-1/CSU NTU/ISDN Applications
General Description
LXT360 LXT361 first full-featured, fully integrated, combination transceivers ISDN Primary Rate Interface long- short-haul applications. They operate over 0.63 AWG) twisted-pair cables kft) offer Line Build-Outs pulse equalization settings Line Interface Unit (LIU) applications. LXT360 LXT361 identical except their control options. LXT361 offers Intel- Motorolabus compatible parallel port microprocessor control. LXT360 provides both serial port microprocessor control hardware control mode stand alone operation. Both incorporate advanced crystal-less digital jitter attenuation either transmit receive data path starting B8ZS/HDB3 encoding/decoding unipolar bipolar data available. Both LIUs provide loss signal monitoring variety diagnostic loopback modes. LXT360/361 uses advanced double-poly, doublemetal fabrication process requires only single 5-volt power supply.
Features
Fully integrated transceivers Long- Short-Haul interfaces Crystal-less digital jitter attenuation Select either transmit receive path crystal high speed external clock required Meet exceed specifications ANSI T1.403 T1.408; G.703, G.736, G.775 G.823; ETSI 300-166 300-233; AT&T 62411 Support coax), twisted-pair) twisted-pair) applications Selectable receiver sensitivity Fully restores received signal after transmission through cable with attenuation either 1024 Five Pulse Equalization Settings short-haul applications Four Line Build-Outs long-haul applications from -22.5 Transmit/receive performance monitors with Driver Fail Monitor Open Loss Signal outputs Selectable unipolar bipolar data B8ZS/ HDB3 encoding/decoding Line attenuation indication output steps QRSS generator/detector testing monitoring Output short circuit current limit protection Local, remote, analog inband network loopback generation detection Multiple-register serial- parallel-interface microprocessor control Available 28-pin DIP, 28-pin PLCC packages
RTIP NOISE CROSSTALK FILTER RECEIVE EQUALIZER RRING
Applications
ISDN Primary Rate Interface (ISDN PRI) CSU/NTU interface T1/E1 Service Wireless Base Station interface T1/E1 LAN/WAN bridge/routers T1/E1 Mux; Channel Banks Digital Loop Carrier Subscriber Carrier Systems
LXT360 Block Diagram
EC4-1 TTIP TCLK TPOS TNEG MODE INTERNAL PATTERN GENERATOR (QRSS) B8ZS/HDB3 UNIPOLAR ENCODER TRANSMIT TIMING CONTROL TRANSMIT ATTENUATION FILTER LINE DRIVERS MONITOR TRING CLKE SERIAL PORT EC1/ ALOOP ENABLE ANALOG LOOPBACK EQUALIZER CONTROL SCLK ENABLE/ REPORT
SELECTED
QRSS ENABLE
ENCODER ENABLE
TAOS ENABLE
Select
CONTROL/STATUS REGISTERS CONTROL
TRSTE
NLOOP ENABLE
RLOOP ENABLE REMOTE LOOPBACK JITTER ATTENUATOR DECODER ENABLE LOCAL LOOPBACK
LLOOP ENABLE
JASEL MCLK ENABLE RCLK RPOS RNEG
CLOCK GENERATOR
GAIN
B8ZS/HDB3 UNIPOLAR DECODER
SELECTED
TIMING DATA RECOVERY SLICERS PEAK DETECTORS
INTERNAL PATTERN DETECTOR NLOOP LOS/
INBAND NLOOP DETECTOR
PROCESSOR
DETECTOR
6-55
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure LXT360 Hardware Controlled Bipolar Mode Assignments
MCLK TCLK TPOS TNEG MODE RNEG RPOS RCLK TRSTE JASEL TTIP TGND
TAOS LLOOP RLOOP RRING RTIP NLOOP TRING TVCC
MCLK TCLK TPOS TNEG MODE RNEG RPOS RCLK TRSTE JASEL TTIP TGND
TAOS LLOOP RLOOP
LXT360PE
RRING RTIP NLOOP TRING TVCC
LXT360NE
Table LXT360 Clock Data Assignments Mode1
External Data Modes Bipolar Mode TPOS TNEG RNEG RPOS TDATA INSBPV RDATA RCLK TTIP TGND TVCC TRING RTIP RRING RNEG RPOS Unipolar Mode MCLK TCLK INSLER INSBPV RDATA QRSS Modes Bipolar Mode Unipolar Mode
Data pins change based whether external data internal QRSS mode active. Clock pins remain same both Hardware Host Modes.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT360 Control Pins Mode
Hardware Modes Unipolar/ Bipolar MODE TRSTE JASEL LOS/ QRSS Host Modes Unipolar/ Bipolar QRSS LOS/ Hardware Modes Unipolar/ Bipolar NLOOP RLOOP LLOOP TAOS QRSS QRSS Host Modes Unipolar/ Bipolar NLOOP SCLK CLKE QRSS
MODE TRSTE
Table LXT360 Hardware Controlled Bipolar Mode Signal Descriptions
Symbol MCLK I/O2 Description Master Clock. Connect 1.544 operation; 2.048 MCLK input requires external independent clock signal generate internal clocks. Required accuracy better than with typical duty cycle 50%. Upon Loss Signal (LOS), RCLK derived from MCLK. Transmit Clock. 1.544 2.048 clock input. Transceiver samples TPOS TNEG ling edge TCLK Transmit Data Positive Negative. Bipolar mode, these pins positi negative sides bipolar input Data transmitted onto sted-pair line input these pins. Table descri Unipolar Mode functions. Mode Select. Connecting MODE puts LXT360 Hardware Mode. Hardware Mode, serial interface disabled hardwired pins used control confi guration report status. Connecting MODE Midrange3 activates Hardware Mode enables B8ZS/HDB3 encoder/decoder Unipolar Mode. Connecting MODE puts LXT360 Host Mode. Host Mode, serial interface controls LXT360 displays status. Receive Data Negative Positive. Bipolar mode, these pins positi negative sides bipolar output pair. Data recovered from line interface output these pins. signal RNEG corresponds recei negative pulse RTIP/RRING. signal RPOS corresponds recei positive RTIP/RRING. RNEG/RPOS outputs Non-Return-to-Zero. Both outputs stable valid rising edge RCLK. Refer Table Unipolar mode function descriptions.
TCLK TPOS TNEG
MODE
RNEG RPOS
These pins change functi operati mode changes. Tables through describe these pins. entries: Digital Input; Digital Output; DI/O Digi Input/Output; Analog Input; Analog Output. drange tage level such that Midrange float.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT360 Hardware Controlled Bipolar Mode Signal Descriptions continued
Symbol RCLK I/O2 Description Recovered Clock. clock recovered from line input signal output pin. Under conditions there smooth transition from RCLK signal (derived from recovered data) MCLK signal RCLK output. Tristate. Connecting TRSTE forces output pins high impedance state. Connecti TRSTE sets LXT360 Hardware Bipolar Mode. Connecti TRSTE Midrange3 enables Unipolar Mode. (See Table Unipolar function descriptions.) connection. Leave this floating. Jitter Attenuation Select. Selects jitter attenuation location. Connecti JASEL High activates jitter attenuator recei path. Connecti JASEL activates jitter attenuator transmi path. Connecti JASEL Midrange3 disables Loss Signal Indicator. modes, goes receipt consecuti spaces returns when recei signal reaches mark density 12.5% (determined receipt marks within sliding window bits with fewer than consecuti zeros). modes, goes High receipt consecuti spaces, returns when receiver detects 12.5% mark density (determined recei marks within sliding window bits fewer than consecutive zeros). transcei outputs received marks RPOS RNEG even when High. Transmit Ring. Differential Driver Outputs. These outputs designed drive load. transformer matching resistors should selected give desired pulse return loss performance. Ground return transmit drivers power supply TVCC. Power Supply input transmit drivers. TVCC must vary from more than Equalization Control Used with EC3-1 (pins 23-25) pulse equalization setti ngs. Network Loopback Detection. LXT360 confi gured detect Network Loopback (NLOOP) connecting RLOOP Midrange this goes High when Inband Network Loopback been activated reception 00001 pattern five seconds. NLOOP reset reception five seconds, activation RLOOP. Receive Ring. signal recei from line applied these pins. transformer required. Data clock from signal applied these pins recovered output RPOS/RNEG, RCLK pins.
TRSTE
JASEL
TTIP TRING
TGND TVCC NLOOP
RTIP RRING
These change function operating mode changes. Tables through descri these column entries: Digi Input; Digital Output; DI/O Input/Output; Analog Input; Analog Output. Midrange tage level such that drange float.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT360 Hardware Controlled Bipolar Mode Signal Descriptions continued
Symbol RLOOP I/O2 Description Power Supply circuits except transmit drivers. (Transmit vers supplied TVCC.) Ground return power supply VCC. Equalization Control 3-1. EC4-1 ncluding define Pulse Equalization, Line Build Outs Equalizer Gain Limit setti ngs. Table additional details. Remote Loopback. When held High, clock data inputs from framer (TPOS/TNEG TDATA) ignored data received from twisted-pair line transmitted back onto line RCLK frequency. During remote loopback, device ignores in-line encoders/decoders. Connecting this Midrange enables Network Loopback. Figure Local Loopback. When held data TPOS TNEG loops back digitally RPOS RNEG outputs (through enabled). Connecting this Midrange3 enables Analog Loopback (TTIP TRING looped back RTIP RRING). Figures Transmit Ones. When held transmit data inputs ignored LXT360/361 transmits stream TCLK frequency. TCLK supplied, MCLK transmit clock reference.) TAOS inhi bited during Remote Loopback. Connecting Midrange enables QRSS pattern generati detection. Figure
LLOOP
TAOS
These pins change functi operati mode changes. Tables through describe these pins. entries: Digital Input; Digital Output; DI/O Digi Input/Output; Analog Input; Analog Output. drange tage level such that Midrange float.
Table LXT360 Hardware Controlled Unipolar Mode Signal Assignments
Symbol TDATA INSBPV I/O1 Description Transmit Data. Unipolar input data transmitted onto twisted-pair line. Insert Bipolar Violation. This sampled falling edge TCLK control Bipolar Violation Inserti transmit data stream. Low-to-High transition requi insert subsequent BPVs. Bipolar Violation. goes report receipt bipolar violation from line. This output, valid rising edge RCLK. Receive Data. RDATA polar output data recovered from line interface. Hardware Mode RDATA stable valid rising edge RCLK.
RDATA
entries: Digital Input; Digital Output; DI/O Digi Input/Output; Analog Input; Analog Output.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table LXT360 Hardware Controlled QRSS Unipolar Mode Signal Assignments
Signal Name INSLER I/O1 Description Insert Logic Error. When this goes from transceiver inserts logic error into transmitted QRSS data pattern. error follows data flow whatever loopback mode effect. LXT360 samples this falling edge TCLK MCLK, TCLK present). Insert Bipolar Violation. When this goes from High, transceiver inserts bipolar violation error into transmitted QRSS data pattern. subsequent inserti requi another High transiti LXT360 samples this falling edge TCLK MCLK, TCLK present). Bipolar Violation. goes High report receipt bipolar olati from sted-pai line. This output, valid rising edge RCLK. Received Data. RDATA unipolar output data recovered from line interface. hardware Mode, RDATA stable valid rising edge RCLK. Loss Signal/QRSS Pattern Detect. This acts indicator well indicator. QRSS Pattern synchroni zation criteri fewer than four errors bits. this mode, long transceiver does detect QRSS pattern stays soon devi does detect QRSS pattern, goes Low; errors cause High half clock cycle. output trigger external error counter. condition also make this High. Figure QRSS. Setting Midrange2, enables QRSS pattern generation detection. transceiver transmits QRSS pattern TCLK rate MCLK, TCLK present).
INSBPV
BPV3 RDATA3
LOS/QPD
QRSS
column entries: Digi Input; Digital Output; DI/O Input/Output; Analog Input; Analog Output. Midrange tage level such that drange float. QRSS Bipolar Mode, pins RNEG RPOS, respectively.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT360 Host Controlled Bipolar Mode Signal Assignments
Signal Name RNEG RPOS I/O3 Description Received Data-Negative Positive. Bipolar Mode, these pins negative positive sides bipolar output pair. transcei outputs data recovered from line interface these pins. signal RNEG corresponds receipt negati pulse RTIP/RRING. signal RPOS corresponds receipt positive signal RTIP/RRING. RNEG/RPOS outputs Non-Return-to-Zero (NRZ). CLKE determi clock edge which these outputs stable valid. Figure Tristate. Connecti TRSTE High forces output pins high-impedance state. Connect this normal operation. connected. Connect Low. Connect Low. Network Loopback. This goes High when Inband Network Loopback been activated. Interrupt (Acti Low-Maskable). goes flag host when LOS, NLOOP, AIS, QRSS, DFMS DFMO changes state when there Elasti Store overflow underflow. open drain output which requires connection power supply through resistor. Reset writi respective Interrupt Clear Register. Serial Data Input. Input port 16-bit serial address/command data word. LXT360 samples sing edge SCLK. Figures Serial Data Output. CLKE High, valid sing edge SCLK. CLKE Low, valid falling edge SCLK. This goes highimpedance state when seri port being written when High. Figure Chip Select (Active Low). This input used access serial interface. each read write operation, must transition from Low, remain Low. Serial Clock. This clock used data read data from serial interface registers. clock frequency rate 2.048 MHz. Clock Edge. Setting CLKE causes RPOS RNEG valid ling edge RCLK, with sing edge SCLK. Setti CLKE makes RPOS RNEG sing edge RCLK valid falling edge SCLK.
TRSTE none none none NLOOP
SCLK CLKE
pins described this table, Table data pins Unipolar QRSS Modes remains same Tables Host Mode, control pins (23-28) change shown Table QRSS polar Mode, pins seven RNEG RPOS, respectively. entries: Digital Input; Digital Output; DI/O Digi Input/Output; Analog Input; Analog Output.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure LXT361 Bipolar Mode Assignments
MCLK TCLK TPOS TNEG ALE/AS RNEG RPOS RCLK RD/DS WR/R/W TTIP TGND
RRING RTIP TRING TVCC
MCLK TCLK TPOS TNEG ALE/AS RNEG RPOS RCLK RD/DS WR/R/W TTIP TGND
LXT361PE
RRING RTIP TRING TVCC
LXT361NE
Table LXT361 Clock Data Assignments Mode1
External Data Modes Bipolar Mode TPOS TNEG RNEG RPOS TDATA INSBPV RDATA RCLK TTIP TGND TVCC TRING RTIP RRING RNEG RPOS Unipolar Mode MCLK TCLK INSLER INSBPV RDATA QRSS Modes Bipolar Mode Unipolar Mode
Data pins change based whether external data internal QRSS mode active. These pins remain same both Hardware Host Modes.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT361 Processor Interface Pins
Address/Data Type Intel Motorola -Pin Address/Data Type Intel -Motorola
Table LXT361 Bipolar Mode Signal Assignments
Symbol MCLK I/O1 Description Master Clock. Connect 1.544 operation; 2.048 MCLK requi external independent input generate internal clocks. Required accuracy with typical duty cycle 50%. Upon Loss Signal (LOS), transceiver derives RCLK from MCLK. Transmit Clock. 1.544 2.048 rate clock input. transceiver samples TPOS TNEG ling edge TCLK Transmit Data Positive Negative. Bipolar Mode, these pins positive negative sides bipolar input Data transmission onto sted-pair line input these pins. Address Latch Enable/Address Strobe (Acti Low). Connects Intel (ALE) Motorola (AS) signal. Motorola bus, this signal Acti Low. Leaving this floating forces output pins into high impedance state. Receive Data Negative Positive. Bipolar mode, these pins positi negative sides bipolar output pair. Data recovered from line interface output these pins. signal RNEG corresponds receipt negative pulse RTIP/RRING. signal RPOS corresponds recei positive RTIP/RRING. RNEG/RPOS outputs Non-Return-to Zero. Both outputs stable rising edge RCLK. Refer Table polar mode functi descri ptions. Recovered Clock. output clock recovered from line input signal Under conditi there smooth transition from RCLK MCLK output.
TCLK TPOS TNEG
RNEG RPOS
RCLK
entries: Digital Input; Digital Output; DI/O Digi Input/Output; Analog Input; Analog Output.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT361 Bipolar Mode Signal Assignments continued
Symbol I/O1 Description Read (Active Low)/Data Strobe (Active Low). Intel bus, this signal, Read, goes command read operation. Motorola bus, this signal, Data Strobe, goes when data driven address/data bus. Data valid rising edge Address/Data lines Used with pins 24-28 address/data bus. Write (Active Low) Write/Read. Intel bus, driving signal, enables write operation Address/Data bus. Motorola bus, ving this signal, Read/Write, commands read operati driving commands write operation. Transmit Ring. Differenti Driver Outputs. design load these outputs transformer line matching resistors give desired pulse height. Ground return transmit drivers power supply TVCC. Power Supply input transmit drivers. TVCC must vary from more than Chip Select (Active Low). each read write Address/Data bus, this must duri operation. Figures timing requirements. case single processor controlling several chips, line uses command specifi transceiver. Interrupt (Active Low). This goes signal interrupt chip. identify specifi interrupt, read Performance Status Register. clear mask interrupt, write appropri Clear Interrupt Regi ster. Receive Ring. signal recei from line applied these pins. transformer required. Data clock from signal applied these pins recovered output RPOS/RNEG, RCLK pins. Power Supply circuits except transmit drivers. (Transmit drivers supplied TVCC.) Ground return power supply VCC. DI/O Address/Data Lines 0-5. (Also pins 11-AD6 Conform Intel Motorola Address/Data specifications.
DI/O DI/O
TTIP TRING
TGND TVCC
RTIP RRING
column entries: Digi Input; Digital Output; DI/O Input/Output; Analog Input; Analog Output.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT361 Unipolar Mode Signal Assignments
Symbol TDATA INSBPV I/O2 Description Transmit Data. Unipolar data transmission onto twisted-pair line. Insert Bipolar Violation. Controls bipolar olation insertions, requires Low-toHigh transition insert each violati LXT361 samples signal ling edge TCLK. Bipolar Violation. goes High receipt bipolar violati from twistedpai line. output, valid sing edge RCLK. Received Data. RDATA output data recovered from line interface. RDATA valid rising edge RCLK.
RDATA
descripti identified this table, Table LXT361 Bipol Mode Signal Assignments. entries input; gital output, DI/O digital input output; analog input analog output.
Table LXT361 QRSS Unipolar Mode
Symbol INSLER I/O3
Signal Assignments1,2
Description
Insert Logic Error. When this goes from transceiver inserts logic error into transmitted QRSS data pattern. error follows data flow whatever loopback mode effect. LXT361 samples this ling edge TCLK MCLK, TCLK present). Insert Bipolar Violation. When this goes from transceiver inserts bipolar violation error into transmi tted QRSS data pattern. subsequent insertion requires another High transition. LXT361 samples falling edge TCLK MCLK, TCLK present). Bipolar Violation. goes High recei bipolar violation from stedpai line. This output, valid rising edge SCLK. Received Data. RDATA output data recovered from line interface. RDATA valid rising edge RCLK.
INSBPV
RDATA
descripti identified this table, Table QRSS polar Mode, pins RNEG RPOS, respectively. entries input; gital output, DI/O digital input output; analog input, analog output.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure LXT361 Integrated T1/E1 Transceiver Block Diagram
TTIP INTERNAL PATTERN GENERATOR (QRSS) B8ZS/HDB3 UNIPOLAR ENCODER
TCLK TPOS TNEG
SELECTED
TRANSMIT TIMING CONTROL
TRANSMIT ATTENUATION FILTER
LINE DRIVERS
MONITOR TRING
QRSS ENABLE
ENCODER ENABLE
TAOS ENABLE
Select PARALLEL PORT ENABLE/ REPORT ALOOP ENABLE ANALOG LOOPBACK EQUALIZER CONTROL GAIN AD0-7
CONTROL/STATUS REGISTERS NLOOP ENABLE RLOOP ENABLE REMOTE LOOPBACK JITTER ATTENUATOR DECODER ENABLE LOCAL LOOPBACK LLOOP ENABLE
ALE/AS RD/DS WR/R/W
JASEL MCLK RCLK RPOS RNEG ENABLE
CLOCK GENERATOR
B8ZS/HDB3 UNIPOLAR DECODER
SELECTED
TIMING DATA RECOVERY SLICERS PEAK DETECTORS
RRING NOISE CROSSTALK FILTER RECEIVE EQUALIZER RTIP
INTERNAL PATTERN DETECTOR
INBAND NLOOP DETECTOR
PROCESSOR
DETECTOR
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
FUNCTIONAL DESCRIPTION
NOTE This functional description design LXT360 LXT361 integrated, transceivers long- short-haul 1.544 Mbps (T1) 2.048 Mbps (E1) applications allowing full-duplex transmission digital data over twisted-pai instal lations. They interface with twisted-pair lines (one each transmit receive) through standard transformers appropri resistors. figure front this Data Sheet shows block diagram LXT360. Control this chip either serial microprocessor port Hardware Mode, individual settings. Figure block diagram LXT361. LXT361 parallel port microprocessor control. Both transceivers provide gh-precision, crystal-less jitter attenuator. user place transmit recei path, bypass completel transceivers meet exceed AT&T specificati DSX-1 applications, ANSI ETSI requirements ISDN applications.
TRANSMITTER Digital Data Interface
Input data transmission onto line clocked serially into device TCLK rate. TPOS TNEG bipolar data inputs. TDATA accepts unipolar data. (Setting TRSTE Midrange enables Hardware Unipolar Mode.) Input data pass through ther tter Attenuator B8ZS/HDB3 encoder both. CR1.ENCENB enables B8ZS/HDB3 encoding Host Mode. Hardware Mode, connecting MODE Midrange ects zero suppression coding. With zero suppression enabled, inputs (see Table determi coding scheme (B8ZS HDB3 mode). select HDB3 scheme, EC4-1 1000, 1001 1010. Other settings B8ZS option. transmit clock (TCLK) supplies input synchroni zation. Test Specifi cations section defines transmit timing requirements TCLK Master Clock (MCLK).
Short Circuit Limit
transmitter includes short circuit limiter. This limits current sourced into impedance load. automatical resets when load current drops below limit. current determined interface circuitry (total resistance transmi side). Host Mode, Performance Status Register flags open circui PSR.DFMO. transition DFMO will provide interrupt transition sets TSR.DFMO Writing ICR.CDFMO clears interrupt; leavi masks that interrupt.
INITIALIZATION
During power transceiver remai static until power supply reaches approximately crossing this threshold, devi begi reset cycle calibrate Phase Lock Loops (PLL). transcei uses reference clock ibrate PLL; transmitter reference TCLK, receiver reference clock MCLK. MCLK mandatory operati
Output Drivers
transcei vers transmit data line code shown Figure Activating driver only during mark reduces power consumption. output driver disabled during transmission space. asing transmi level on-chip.
Reset Operation
Reset clears sets registers resets status state machines LOS, AIS, NLOOP, QRSS blocks. Hardware Mode, holding pins RLOOP, LLOOP TAOS High least clock cycle resets devi Writing CR2.RESET commands reset Host Mode. Allow devi settle after removing reset conditi ons.
Figure Duty Cycle Coding Diagram
TTIP
CELL
TRING
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LXT360/361 Integrated T1/E1 LH/SH Transceivers Idle Mode
Transmit Idle Mode normal operational mode opposed modes) lows multiple transcei vers connected single line redundant applications. TTIP TRING remain impedance state when TCLK present. Remote Dual Loopback, TAOS internal transmit patterns temporarily disable high impedance state detection Network Loop code receive direction. received signal. data slicers peak value ensure optimum signal-to-noise performance. After processing through data slicers, recei signal goes data recovery section, then B8ZS/HDB3 decoder selected) recei monitor. data timing recovery circuits provide input jitter tolerance significantly better than required AT&T 62411 G.823. Test Specifi cations section.
Pulse Shape
Equal izer Control inputs (EC4-1) determine transmitted pulse shape Table Host Mode, port controls values. LXT360 Hardware Mode, four indivi dual pins provi inputs. Shaped pulses meeting various DS1, DSX-1 specifi cations applied line transmission onto TTIP TRING. transceivers produce DSX-1 pulses short-haul applications (settings from +3.0 dB), pulses long-haul applications (setti from -22.5 dB), G.703 applications. Refer Test Specificati section pulse mask specifications.
Digital Data Interface
either Host Hardware Control Mode recovered data goes Loss Signal (LOS) Monitor. Host Control Mode, goes through Alarm Indication Signal (AIS, Blue Alarm) Monitor. jitter attenuator circui enabled disabled receive data path transmit path. Received data through either B8ZS HDB3 decoder neither. Finally, devi send digital data framer either unipolar bipolar data. When transmitting unipolar data framer, devi reports receiving bipolar violati ving High. During operati Host Control Mode, device report HDB3 code violati Zero Substitution Violations pin. diagnostics section explai these opti more detail.
RECEIVER
transformer provides interface twisted-pair line. Recovered data output RPOS/RNEG (RDATA polar Mode), recovered clock output RCLK. Test Specificati section shows receiver
Receiver Monitor Mode
receive equal izer LXT360/361 used Moni Mode applicati ons. Monitor Mode applications those requiri resistive attenuation signal additi small amount cable attenuation than dB). Setting CR3.EQZMON configures device work Moni Mode. device must long-haul receiver mode (set bits CR1.ECx 0xx0 1001 1010) Monitor Mode. feature available LXT360 Hardware Mode. device Monitor Mode, receive equalizer handles signal attenuated resistivel along with cable attenuation both applicati ons.
Receiver Equalizer
receive equalizer processes signal received RTIP RRING. equalizer gain longhaul applications. long-haul applications, equalizer control (ECx) input pins register bits determine maximum gain applied equalizer. With Low, gain applied. When gain limit provide increased noise margin shorter loop operations. receiver accurately recover signals with cable attenuati (from cable attenuati (from operation.
JITTER ATTENUATION Data Recovery
transceiver filters equal ized signal applies peak detector data slicers. peak detector samples inputs determi maximum value Jitter Attenuation Loop (JAL) with Elastic Store (ES) provides itter attenuation shown Test Specifications section. requires special circuitry, such external quartz crystal high-frequency clock
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
(higher than line rate). reference master clock, MCLK. Hardware Control Mode 2-bit register. Setting JASEL High places circui received data path; setting JASEL places transmit data path; tying Midrange disables Host Mode, CR1.JASEL0 enables disables circuit. With CR1.JASEL0 CR1.JASEL1 controls circuit placement (see Table 16). either 2-bit 2-bit register depending value CR3.ES64 (see Table 18.) device clocks data using either TCLK Receiver Recovered Clock depending whether circuitry transmit receive data path, respectively. Data shifted astic store using ittered clock from JAL. When FIFO within bits overflowi underfl owing, adjusts output clock period. produces average delay bits bits, with 64-bit option selected Host Control Mode) associated data path. When tter Attenuator receive path, output RCLK transiti smoothly MCLK event condition. Transition Status Register bits TSR.ESOVR TSR.ESUNF indicate overflow underflow, respectively, These sticky bits: once they remai until host reads register. provide maskable interrupt ther overfl underflow.
Table Equalizer Control Input Settings
EC11
Function Long Haul Long Haul Long Haul Long Haul Long Haul Long Haul Long Haul Long Haul Short Haul Long Haul Long Haul Short Haul Short Haul Short Haul Short Haul Short Haul
Pulse pulse -7.5 pulse -15.0 pulse -22.5 pulse pulse -7.5 pulse -15.0 pulse -22.5 pulse G.703 G.703 G.703 0-133 133-266 266-399 399-533 533-655
Cable TP/75 Coax TP/75 Coax
Gain
Coding2 B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS HDB3 HDB3 HDB3 B8ZS B8ZS B8ZS B8ZS B8ZS
sets receive equalizer gain (EGL) during long-haul operation. When enabl
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LXT360/361 Integrated T1/E1 LH/SH Transceivers DIAGNOSTIC MODE OPERATION
LXT360/361 offers tiple diagnostic modes shown Table Hardware Mode, diagnostic modes ected combination settings. Host Mode, diagnosti modes selected writi appropriate bits agnostic Control Regi ster.
Table Diagnostic Mode Availability
Diagnostic Mode Availability1 Loopback Modes Local Loopback (LLOOP) Anal Loopback (ALOOP) Remote Loopback (RLOOP) In-band Network Loopback (NLOOP) Dual Loopback (DLOOP) Internal Data Pattern Generation Detection Transmit Ones (TAOS) Quasi-Random Signal Source (QRSS) In-band Loop up/down Code Generator Error Insertion Detection polar Violation Insertion (INSBPV) Logi Error Insertion (INSLER) polar Violation Detecti (BPV) Logi Error Detection, QRSS (QPD) HDB3 Code Violati Detection (CODEV) HDB3 Zero violation Detection (ZEROV) Alarm Condition Monitoring Receive Loss Signal (LOS) Moni toring Receive Indication Signal (AIS) Monitoring Transmit Failure Monitoring-Open (DFMO) astic Store Overfl Underfl Monitoring Other Diagnostic Reports Receive Attenuation Indicator (LATN) Built-In Self Test (BIST) Host Host Mode2 Maskable
Hardware Control Mode, combination settings selects Diagnostics Modes; Host Control Mode, writing appropri Control Registers selects Diagnostic Modes. Host Control Mode allows interrupt masking writing corresponding Interrupt Clear Register. Hardware Control Mode interrupt masking feature.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers LOOPBACK MODES
NOTE Hardware Mode pins discussed this section refer LXT360 only.
Figure Local Loopback Selected)
Local Loopback with Receive Path
B8ZS/HDB3 ENCODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Local Loopback
Figures Hardware Mode, Local Loopback (LLOOP) selected tying LLOOP High; Host Mode, setting CR2.ELLOOP LLOOP inhibits receiver circuits. transmit clock data inputs (TCLK TPOS/TNEG TDATA) loop back through jitter attenuator enabled) show RCLK RPOS/ RNEG RDATA. (During LLOOP, JASEL input strictly Enable/Disable control; does affect placement JAL. enabled, active loopback circuit. bypassed, active loopback circuit.) transmitter circuits unaffected LLOOP. LXT360/361 transmits TPOS/TNEG TDATA inputs stream TAOS asserted) normally. When used this mode, transceiver function stand-alone jitter attenuator.
Local Loopback with Transmit Path
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 DECODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Analog Loopback
Figure Analog Loopback (ALOOP) exercises maximum number functional blocks. ALOOP operation disconnects RTIP/RRING inputs from line routes transmit outputs back into receive inputs. This tests encoders/decoders, jitter attenuator, transmitter, receiver timing recovery sections. Hardware Mode, tying Midrange commands Analog Loopback; Host Mode, writing CR2.EALOOP enables function. ALOOP function overrides other loopback modes.
Figure TAOS with LLOOP Selected)
Transmit Ones Local Loopback with Receive Path
TAOS
B8ZS/HDB3 ENCODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Figure Analog Loopback Selected)
Analog Loopback with Receive Path
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 DECODER*
B8ZS/HDB3 DECODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Transmit Ones Local Loopback with Transmit Path
TAOS
B8ZS/HDB3 ENCODER*
B8ZS/HDB3 ENCODER*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
TCLK TPOS TNEG RCLK RPOS RNEG
Analog Loopback with Transmit Path
B8ZS/HDB3 DECODER*
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
B8ZS/HDB3 DECODER*
B8ZS/HDB3 DECODER*
6-71
LXT360/361 Integrated T1/E1 LH/SH Transceivers Remote Loopback
Figure Remote Loopback (RLOOP) mode, device ignores transmit data clock inputs (TCLK TPOS/TNEG TDATA), bypasses in-line encoders/decoders. RPOS/RNEG RDATA outputs loop back through transmit circuits TTIP TRING RCLK frequency. RLOOP command does affect receiver circuits which continue output RCLK RPOS/RNEG RDATA signals received from twisted-pair line. Host Mode, command RLOOP writing CR2.ERLOOP. Hardware Mode, RLOOP commanded setting High.
Dual Loopback
Figure select Dual Loopback (DLOOP), both RLOOP LLOOP High Hardware Mode bits CR2.ERLOOP CR2.ELLOOP Host Mode. DLOOP mode, transmit clock data inputs (TCLK TPOS/TNEG TDATA) loop back through Jitter Attenuator (unless disabled) RCLK RPOS/RNEG RDATA. data clock recovered from twisted-pair line loop back through transmit circuits TTIP TRING without jitter attenuation.
Figure Remote Loopback Selected)
Remote Loopback with Receive Path
Network Loopback
Network Loopback (NLOOP) initiated only when Network Loopback detect function enabled. Host Mode, writing CR2.ENLOOP enables NLOOP detection. Hardware Mode, setting RLOOP Midrange enables Network Loopback detection. With NLOOP detection enabled, receiver looks NLOOP data patterns (00001 enable, disable) input data stream. When receiver detects NLOOP enable data pattern repeated minimum five seconds, device enables RLOOP. device responds both framed unframed NLOOP patterns. Once NLOOP detection enabled chip activated appropriate data pattern, identical Remote Loopback (RLOOP). NLOOP disabled receiving pattern five seconds, activating RLOOP ALOOP, disabling NLOOP detection. device goes into Dual Loopback Mode (DLOOP) case where detects both NLOOP LLOOP functions.
TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 ENCODERS*
B8ZS/HDB3 DECODERS*
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Remote Loopback with Transmit Path
B8ZS/HDB3 ENCODERS*
TCLK TPOS TNEG RCLK RPOS RNEG
Timing Control Enabled Timing Recovery
TTIP TRING RTIP RRING
Figure
TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 B8ZS/HDB3 DECODER* ENCODER*
B8ZS/HDB3 DECODERS*
Dual Loopback
Timing Control Enabled Timing Recovery RTIP RRING TTIP TRING
6-72
LXT360/361 Integrated T1/E1 LH/SH Transceivers INTERNAL PATTERN GENERATION DETECTION Transmit Ones
Figure Transmit Ones (TAOS) Mode transceiver ignores TPOS TNEG inputs transmits continuous stream TCLK frequency. (With TCLK, TAOS output clock MCLK.) This used Alarm Indication Signal (AIS-also called Blue Alarm). Host Mode, TAOS commanded writing CR2.ETAOS. Hardware Mode setting High does Both TAOS Local Loopback occur simultaneously shown Figure Remote Loopback inhibits TAOS. When both TAOS LLOOP active, TCLK TPOS/TNEG loop back RCLK RPOS/RNEG through jitter attenuator enabled), ones pattern goes TTIP/TRING. Furthermore bipolar violation QRSS pattern possible causing Low-to-High transition INSBPV (pin without regard whether device bipolar unipolar operating mode.
Figure QRSS Mode
MCLK TCLK TPOS TNEG RCLK RPOS RNEG RCLK (CLKE
B8ZS/HDB3 B8ZS/HDB3 DECODERS* ENCODERS*
QRSS Pattern Generator
Timing Control Timing Recovery
QRSS Sync/Error Detector
TTIP TRING RTIP RRING
RCLK (CLKE
Receive QRSS Pattern Lock
Receive QRSS Logic Error Detector
Figure TAOS Data Path
TAOS TCLK TPOS TNEG RCLK RPOS RNEG
B8ZS/HDB3 B8ZS/HDB3 DECODER* ENCODER*
Timing Control Enabled Timing Recovery
TTIP TRING
RTIP RRING
Quasi-Random Signal Source (QRSS)
Figure operation, Quasi-Random Signal Source (QRSS) 220-1 pseudo-random sequence (PRBS) with more than consecutive zeros. operation, QRSS 215-1 PRBS with inverted output. Both Hardware Host Modes allow QRSS Mode. QRSS pattern normally locked TCLK; there TCLK, MCLK clock source. Bellcore 62411 defines QRSS transmit format G.703 defines format. Connecting TAOS (pin Midrange enables QRSS transmission Hardware Mode. Host Mode, setting bits CR2.EPAT0 CR2.EPAT1=1enables this function. With QRSS transmission enabled, possible insert logic error into transmit data stream causing Low-to-High transition INSLER (pin However, logic errors inserted into QRSS pattern, INSLER must remain Low. Logic Error insertion waits until next current "jammed". (When there more than consecutive output jammed
Choosing QRSS Mode also enables QRSS Pattern Detection (QPD) receive path. QRSS pattern synchronized when there fewer than four errors bits. After achieving synchronization device drives (pin (QPD output available LXT360 only). LXT361 does support error detection QRSS Mode. LXT360 QRSS Mode, subsequent error QRSS pattern causes High half RCLK clock cycle (the precise relationship RCLK depends value CLKE-when CLKE Low, goes High while RCLK High; CLKE High, goes High while RCLK Low). This signal edge serve trigger external bit-error counter. condition loss QRSS synchronization will cause this output High continuously. this case, with either Unipolar Mode encoders/decoders enabled, indicates BPVs, CODEVs ZEROVs chosen. Host Mode offers additional interrupt indicate that QRSS detection sychronization have occurred, that synchronization lost. This interrupt available when ICR.CQRSS signal triggers error counter, interrupt could start reset counter. Also Host Mode, PSR.QRSS provides indication QRSS pattern synchronization. This goes with QRSS pattern detected (i.e., when there more than four errors bits). TQRSS Transition Status Register indicates that QRSS status changed since last QRSS Interrupt Clear command. 6-73
LXT360/361 Integrated T1/E1 LH/SH Transceivers In-Band Network Loop Down Code Generator
Host Mode, LXT360/361 transmit in-band Network Loop Loop Down code. Loop code 00001; Loop Down code 001. Loop code transmission occurs when Control Register bits EPAT0 EPAT1 Loop Down code transmi ssion requi that both EPAT0 EPAT1 With this mode enabled, logi errors bipolar violations inserted into transmi data stream. Inserting logi error requires Low-to-High transition INSLER (pin there logi errors insert, INSLER must remai Low.) Inserting bipolar olation requires Low-to-High transiti INSBPV (pin independent polar Bipolar operati Logic Error Detection (QPD) (LXT360 Only) After recei ving pattern synchronizati when configured QRSS Mode, LXT360 reports logic errors (pin 12). indicate ogic error, this goes RCLK cycle (during High peri RCLK CLKE during RCLK period CLKE High). tally logic errors, connect error counter QPD. continuous ogic this indicates loss either QRSS pattern lock condition. QRSS section additi onal details QRSS pattern lock criteria. Bipolar Violation Detection (BPV) internal encoders/decoders enabled when configured Unipolar Mode, LXT360/361 reports received Bipolar Violations (pin goes High clock cycle indicate receipt BPV. However, encoders/decoders enabled, LXT360/ does report bipolar violations line coding scheme. HDB3 Code Violation Detection (CODEV) LXT360/361 detect HDB3 code violati Host Mode HDB3 encoders enabled. This requires CR1.ENCENB CR1.EC4-1 100x 1010, establishes operation. enable CODEV, CR4.CODEV HDB3 code violation (CODEV) occurs when device receives consecutive bipolar violations same polarity (refer O.161). With CODEV detection enabled, LXT360/361 reports violation along with recei BPVs ZEROVs these options enabled). LXT360/361 forces High full RCLK cycle report CODEV. HDB3 Zero Substitution Violation Detection (ZEROV) encoders/decoders enabled, LXT360/361 detect HDB3 zero substi tution violations (ZEROV) Host Mode. This requi CR1.ENCENB CR1.EC4-1 100x 1010, which establish operati CR4.ZEROV LXT360/361 forces High full RCLK cycle report ZEROV. HDB3 ZEROV recei four more consecutive zeros. This does occur with correctly encoded HDB3 data unless there transmission errors. With ZEROV detection enabled, devi reports violation along with received BPVs CODEVs these options enabled).
ERROR INSERTION DETECTION Bipolar Violation Insertion (INSBPV)
Unipolar Mode, both Hardware Host Modes provide Bipolar Violation Insertion (INSBPV). Choosing Unipolar Mode configures INSBPV. Bipolar olation inserti requires Low-to-High transition INSBPV. Sampling occurs falling edge TCLK. When INSBPV goes inserted next available mark except four following situations: Zero suppression (HDB3 B8ZS) violated LOOP TAOS both active, looped back EG/BPV indicator line driver transmits ones with violation. inserti disabled with RLOOP (remote loopback) acti insertion disabled with NLOOP asserted (pin High) With LXT360/361 configured transmi internal generated data patterns (QRSS NLOOP), inserted transmi pattern independent whether device polar bipolar mode operati LOGIC ERROR INSERTION (INSLER) When configured transmi internally generated data patterns (QRSS NLOOP Up/Down codes), device insert logic error transmi data pattern when there Low-to-High transition INSLER. QRSS Mode, there logi error insertion jammed forced suppress transmission more than consecutive zeros). transcei treats data patterns same treats data applied TPOS/TNEG, inserted logic error will follow data flow path defi loopback mode effect.
6-74
LXT360/361 Integrated T1/E1 LH/SH Transceivers ALARM CONDITION MONITORING Loss Signal (LOS)
LXT360/361 Loss Signal (LOS) monitor functi compatible G.775 ETSI 300233. receiver monitor loads digital counter RCLK frequency. count increments with each received counter resets receipt When count reaches flag goes MCLK replaces recovered clock RCLK output smooth transiti operati ons, number 175, operati ons, Host Mode, ther number changed 2048 setting CR4.LOS2048 operati when received signal 12.5% marks sliding 128-bit peri with fewer than consecutive 0s), returns recovered clock replaces MCLK RCLK output another smooth transition. operation, condition cleared when received signal 12.5% density (four sliding 32-bit window fewer than consecutive 0s). Host Mode operati out-of-LOS criteri modifi from 12.5% marks density consecutive marks setti CR4.COL32CM During LOS, device sends recei data RPOS/ RNEG pins RDATA Unipolar Mode). LXT360 reports condition Hardware Mode. Host Mode, Performance Status Regi ster goes High indicate condition will interrupt host controller programmed. lines. DFMO generate host controller. Transition Status Register DFMO indicates transition status bit. Writing ICR.CDFMO will clear mask interrupt.
Elastic Store Overflow/Underflow
(ESOVR/ESUNF)
When count Elastic Store (ES) within bits overfl owing underflowing adjusts output clock peri Host Mode, provides indication overflow underfl TRS.ESOVR TSR.ESUNF. These bits will stay unti host controller reads register. These interrupts cleared masked writing bits ICR.CESO ICR.CESU, respecti vely.
OTHER DIAGNOSTIC REPORTS Receive Line Attenuation Indication
(LATN)
equalizer status register (ESR) provides approximation line attenuati encountered device. four most signi ficant bits regi ster (ESR.LATN7-4) indicate line attenuation approximately steps both operati receive equalizer. instance, ESR.LATN7-4 (decimal), then receiver seeing signal attenuated approximately (2.9 cable loss.
Built-In Self Test (BIST)
LXT360/361 provides Built-In Self Test (BIST) capability Host Mode. BIST exercises internal circuits provi ding internal QRSS pattern, running through encoders transmi vers then looping back through recei equal izer, tter Attenuator decoders QRSS pattern detection circuitry. blocks this data path work correctl receive pattern detector locks onto pattern. then sets following bits High: TSR.TQRSS PSR.QRSS PSR.BIST (pin also indicates completi status test. Starti test forces High. During test, remai until test finishes successfully time goes Low. most reliable test resul separate TCLK MCLK -22.5 (CR1.EC4-1 011x).
Alarm Indication Signal Detection (AIS)
Alarm Indication Signal (AIS) available only Host Mode. receiver detects pattern when receives fewer than three stri 2048 bits. device clears condition when recei three more string 2048 bits. Performance Status Register indicates detection. When status changes, TAIS Transition Status Register goes High. change status interrupts host controller pulling Low, unless interrupt masked. Writing ICR.CAIS masks interrupt until returns
Driver Failure Open Mode (DFMO)
Host Mode Open (DFMO) available Performance Status Register indicate open condition
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LXT360/361 Integrated T1/E1 LH/SH Transceivers OPERATING MODES
LXT360/361 share many features. However, their control modes very different. LXT360 operates either Hardware (Serial Port) Host Mode LXT361 operates (Paral Port) Host Mode Hardware Mode (LXT360 indivi dual pins control transceiver. logic level MODE sets LXT360 mode operation. Host Mode (LXT360/361), microprocessor controls device through data interface. LXT360 seri interface LXT361 uses paral interface.
Host Mode Operation
LXT360 operates Host Mode when MODE High. Host Mode microprocessor accesses controls transceiver through data port using nternal registers. outputs (RPOS/RNEG RDATA) rising edge RCLK Host Mode there eight control status registers- five read/wri three read-only regi sters. LXT360 accesses them through serial interface (SIO). LXT361 provides this access using 8-bit parallel nterface (PIO). host processor/controller completely configure device well full diagnostic/status report through PIO. Only clocks data Bipolar Mode BPV/Logic Error insertions Unipolar QRSS Mode need provi directly input pins. Similarly, recovered clock, data, BPV/Logi Error occurrences avai lable only output pins. other mode setti diagnostic informati avai lable through data port. Table shows address used access each register LXT360 LXT361, respectively. Table summari control status regi sters labels each they contain. Tables through identi bits each register.
Hardware Mode Operation (LXT360 Only)
LXT360 operates Hardware Mode when MODE Midrange Low. Hardware Mode indivi dual pins access control transceiver. outputs (RPOS/RNEG RDATA) sing edge RCLK There some advanced functions provided only Host Mode. Interrupt (INT), detection indicator, open indicator CLKE functions some features available Host Mode.
Table
Serial (LXT360) Parallel (LXT361) Port Register Addresses
Address1
Abbr
Serial Port Parallel Port
Register Name Control Control Control Interrupt Clear Transition Status Performance Status Equalizer Status Control
"don't care".
x010000 x010001 x010010 x010011 x010100 x010101 x010110 x010111
x010000x x010001x x010010x x010011x x010100x x010101x x010110x x010111x
6-76
LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Register Addresses Names
Register Name
Control Control Control Interrupt Clear Transition Status Performance Status Equalizer Status Control
Type
JASEL1 RESET JA6HZ CESU ESUNF reserved LATN7 reserved
JASEL0 EPAT1 PCLKE CESO ESOVR BIST LATN6 reserved
ENCEB EPAT0 SBIST CDFMO TDFMO DFMO LATN5 reserved
UNIENB ETAOS EQZMON reserved reserved reserved LATN4 reserved
EALOOP ES64 CAIS TAIS reserved LOS2048
ELLOOP ESCEN CNLOOP TNLOOP NLOOP reserved ZEROV
ERLOOP ESJAM CLOS TLOS reserved CODEV
ENLOOP reserved CQRSS TQRSS QRSS reserved
COL32CM
CR3.PCLKE available only LXT361; LXT360, this zero. registers, bits labeled reserved should (except note below) normal operation ignored read only registers. Write into this normal operation.
Table Control Register Read/Write, Address (A7-A1) x010000
Name Function Jitter Attenuation JASEL0 JASEL1 UNIENB ENCENB Enables Unipolar Mode inserti on/detecti BPVs. Enables B8ZS/HDB3 encoders/decoders; device enters Unipolar Mode pins change their polar functions. Jitter Attenuation Mode, ects jitter attenuation circuitry position data path disables right hand secti table values. Position Transmit Recei disabled
Equalizer Control codes (see Table 12).
JASEL0 JASEL1
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Control Register Read/Write, Address (A7-A1) x010001
Name Function EPAT0 ERLOOP1 ELLOOP1 EALOOP Enables Remote Loopback (RLOOP) Enables Local Loopback (LLOOP) Enables Analog Loopback (ALOOP) Pattern EPAT1 Selected Transmit TPOS/TNEG Detect transmit QRSS In-band Loop Code 00001 In-band Loop Down Code
ENLOOP
Enables Network Loopback Detecti (NLOOP) Enables Transmi Ones (TAOS) Enables internal data pattern transmi ssion. right hand section table values. RESET resets device state registers.
ETAOS EPAT0 EPAT1 RESET
enable Dual Loopback (DLOOP), both ERLOOP ELLOOP
Table Control Register Read/Write, Address (A7-A1) x010010
Name ESJAM ESCEN ES64 EQZMON SBIST PLCKE Description Disables Jammi Elastic Store Read Clock bit-ti adjustment over/underfl ow). Centers pointer difference (depending depth-clears automatically). Increases depth from bits. reserved-set normal operation. Configures Receiver Equalizer Moni Mode Application Starts Built-In Self Test. This available only LXT361- LXT360, this PCLKE sets RPOS/RNEG valid rising edge RCLK. PCLKE sets RPOS/RNEG valid falling edge RCLK When JA6HZ changes bandwidth Jitter Attenuation Loop from (default)
JA6HZ
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Interrupt Clear Register Read/Write, Address (A7-A1) x010011
Name CLOS CNLOOP CAIS CQRSS CDFMO CESO CESU Clears/Masks Interrupt. Clears/Masks NLOOP Interrupt. Clears/Masks Interrupt. Clears/Masks QRSS Interrupt. reserved-set normal operation. Clears/Masks DFMO. Clears/Masks Overfl Interrupt. Clears/Masks Underflow Interrupt. Function1
Leavi these bits masks associated interrupt.
Table Transition Status Register Read Only, Address (A7-A1) x010100
Name TLOS TNLOOP TAIS TQRSS TDFMO ESOVR ESUNF Function Loss Signal (LOS) changed since last clear interrupt occurred. NLOOP changed since last clear NLOOP interrupt occurred. changed since last clear interrupt occurred. QRSS changed since last clear QRSS interrupt occurred1. reserved-ignore. DFMO changed since last clear DFMS interrupt occurred. overflow status sticky bit2. underfl status sticky
QRSS transiti indicates receive QRSS pattern sync loss. simple error QRSS pattern reported transition. Trippi overflow underflow indicator sets ESOVR/ESUNF status bit(s). Readi Transi tion Status Register clears these bits. Setting CESO CESU Interrupt Clear Register masks these interrupts.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Performance Status Register Read Only, Address (A7-A1) x010101
Name NLOOP QRSS DFMO BIST Loss Signal (LOS) Status. Network Loop (NLOOP) Status. Alarm Indicator (AIS) Status. QRSS Pattern Detect Status. reserved-ignore. Open Indicati Built-In Test Status. reserved-ignore Function
Table Equalizer Status Register Read Only, Address (A7-A1) x010110
Name LATN4 LATN5 LATN6 LATN7 reserved-ignore (Least Signi ficant reserved-ignore reserved-ignore reserved-ignore Receive Line Attenuation Indicators. Convert this binary output decimal number multi determine approximate cable attenuation seen receiver. instance, LATN7-4 1010 DEC), then recei seeing signal attenuated approximately (2.9 cable. Function
6-80
LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Control Register Read/Write, Address (A7-A1) x010111
Name CODEV Function Enables detecti HDB3 code violati along with bipolar violati ZEROVs enabled). Enables detection four consecutive zeros HDB3 coding violation) along with bipolar violation ZEROVs enabled). Changes detecti threshold from consecutive zeros (for operation) consecuti zeros operation) 2048 consecutive zeros ther envi ronment. Mode, changes "clear condition" criterion from 12.5% marks density (default) receipt consecuti marks. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading. reserved-set normal operation; ignore when reading.
ZEROV LOS2048
COL32CM
Serial Port Operation (LXT360 Only)
LXT360 operates Host Mode when MODE High. Figure shows data structure. registers accessible through 16-bit word: 8-bit Command/Address byte (bits A1-A7) subsequent 8-bit data byte (bits D0-7). determines whether read write operati occurs. A6-1 Command/Address byte address specific registers (the address decoder ignores A7). data byte depends both value address register Command/Address byte. Host Mode provides atched interrupt output (INT). change state followi bits Performance Status Register will drive Low: LOS, NLOOP, AIS, QRSS, DFMO. interrupt will also occur when there elasti store overflow underfl When interrupt occurred, output pulled Low. output stage each consists only l-down device, each requires external pull-up resistor. interrupt cleared when interrupt condition longer exists, host processor writes respective interrupt causing bit(s) Interrupt Register. Leaving these interrupt status bits masks that interrupt.
Table CLKE Settings
CLKE Output RPOS RNEG High RPOS RNEG Clock RCLK RCLK SCLK RCLK RCLK SCLK Valid Edge Rising Rising Falling Falling Falling Rising
Host Mode also allows control serial data recei data output timing. clock edge (CLKE) signal determi when outputs valid, Serial Clock (SCLK) RCLK shown Table
6-81
LXT360/361 Integrated T1/E1 LH/SH Transceivers Parallel Port Operation (LXT361 Only)
LXT361 address/control pins control pins compatible with both Intel Motorola address/data buses. Figures timing diagram each bus. device automatically detects timing based Intel Motorola microprocessor specifications. maximum recommended processor speed Intel device MHz; Motorola device, 16.78 MHz. Table summarizes control status registers LXT361. Tables through identify explain bits control registers. LXT361 provides latched interrupt output (INT). change state following bits Performance Status Register will drive Low: LOS, NLOOP, AIS, QRSS, DFMO. When interrupt occurred, output pulled Low. output stage consists only pull-down device, each requires external pull-up resistor. interrupt cleared when interrupt condition longer exists, host processor writes respective interrupt causing bit(s) Interrupt Register. Leaving these interrupt status bits masks that interrupt. received data output valid rising edge RCLK, when CR3.PCLKE data output valid falling edge RCLK when CR3.PCLKE There five read/write three read-only registers. Only bits A6-1 address byte valid. (The address decoder ignores bits A0.) Tables through show register address bits A7-1, without regard
Figure LXT360 Serial Interface Data Structure
SCLK ADDRESS COMMAND BYTE INPUT DATA BYTE
(SDO remains high impedance) READ WRITE
DON'T CARE
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
APPLICATION INFORMATION
NOTE application information design only. Table shows specificati transmit return loss applications. (The G.703/CH specifi cation ecommuni cations Ministry specification.) Tables through show transmit return values short- long-haul applications. Table shows receive return loss values.
Table Transmit Return Loss (2.048 Mbit/s-Long-Haul) High Return
Loss Configuration
EC4-1 1001 Xfrmr/ 1:2/ 1.53/ Rload (pF) Return Loss (dB)
Table Transmit Return Loss Requirements
Frequency Band 51-102 102-2048 2048 3072 Return Loss G.703/CH
Table Transmit Return Loss (2.048 Mbit/s-Long-Haul)
EC4-1 1010 Xfrmr/ 1:2/ Rload (pF) Return Loss (dB)
Table Transmit Return Loss (2.048 Mbit/s-Short-Haul)
EC4-1 1000 Xfrmr/Rt 1:2/ Rload (pF) 1:2.3/ Return Loss (dB)
Table Transmit Return Loss (1.544 Mbit/s-Long- Short-Haul)
EC4-1 Refer Table Xfrmr/Rt 1:2/9.1 1:1.151/ Rload (pF) Return Loss (dB)
1:1.15 transmit transformer keeps total transceiver power pati level, 0.47 ocki capacitor must placed TTIP TRING.
Table Transformer Specifications LXT360/LXT361
Tx/Rx Frequency Turns Ratio Primary Inductance (minimum) Leakage Inductance (max) 0.80 0.80 0.80 1.10 Interwinding Capacitance (max) (maximum) 0.90 1.70 0.70 1.20 0.70 1.20 1.10 1.10 Dielectric1 Breakdown (minimum) 1500 VRMS 1500 VRMS2 1500 VRMS2 1500 VRMS2
1.544 2.048 1.544/2.048
1:1.15
1.544/2.048
Some ETSI applications require dielectric breakdown tage. Some applications require transformers with center (Long-Haul applications current E1/T1 loop).
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Recommended Transformers LXT360/LXT361
Tx/Rx Turns Ratio 1:1.53 1:1.15 Part Number PE-68663 PE-65388 PE-65770 16Z5952 PE-65351 PE-65771 0553-5006-IC 66Z-1308 671-5832 67127370 67130850 TD61-1205G 16Z5946 1:2.3 PE-65558 8006-155 671-5792 PE-64936 PE-65778 67130840 67109510 TD61-1205D 16Z5936 16Z5934 HALO (combination Tx/Rx set) Vitec Schott Corp HALO (combination Tx/Rx set) Vitec Pulse Engineering Fil-Mag Midcom Pulse Engineering Bell-Fuse Fil-Mag Midcom Schott Corp Vitec Pulse Engineering Manufacturer Pulse Engineering
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
NOTE Figure shows typical LXT360 application either environment. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely. Excessive capacitance will distort transmitted signals.
Figure Typical T1/E1 LXT360 Hardware Mode Application
2.048MHz/ 1.544 MCLK TAOS LLOOP RLOOP TCLK TPOS TNEG T1/E1 Framer RCLK RPOS RNEG TCLK TPOS TNEG MODE TRSTE RCLK RPOS RNEG TRING NLOOP TVCC TGND RRING RTIP JASEL From CMOS Control Logic
LXT360
TTIP
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
NOTE Figure shows application using LXT360 Host Controlled Mode. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely. Excessive capacitance will distort transmitted signals.
Figure Typical T1/E1 LXT360 Host Mode Application
2.048MHz/ 1.544 MCLK TCLK TPOS TNEG T1/E1 Framer RCLK RPOS RNEG MODE TRSTE RCLK RPOS RNEG TCLK TPOS TNEG CLKE SCLK Host
LXT360
TTIP
NLOOP TVCC TGND RRING TRING RTIP
6-86
LXT360/361 Integrated T1/E1 LH/SH Transceivers
NOTE Figure shows application using LXT361. Tables through select transformers T2), resistors capacitors (Cl) needed this application. NOTE application includes surge protection, such varistor sidactor TTIP/TRING lines, also require reducing value capacitor eliminating completely.
Figure 9Typical T1/E1 LXT361 Application
2.048MHz/ 1.544 MCLK ALE/AS TCLK TPOS T1/E1 TNEG Framer RCLK RPOS RNEG TCLK TPOS TNEG RCLK RPOS RNEG RD/DS WR/R/W
(Intel Motorola)
AD0-7
LXT361
TTIP
TVCC TGND RRING TRING RTIP
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
TEST SPECIFICATIONS
NOTE minimum maximum values Tables Figures through represent performance spcifications LXT360 LXT361 guaranteed test, except where noted design.
Table Absolute Maximum Ratings
Parameter supply (reference GND) Input voltage, Input current, Ambient operating temperature Storage Temperature VCC, TVCC TSTG CAUTION
Operation these limits permanently damage device. Normal operation these extremes guaranteed.
TVCC must differ more than during operation. TGND must differ more than during operation. Transient currents will cause latch-up. TTIP, TRING, TVCC, TGND withstand continuous currents
-0.3
Units
Table Operating Conditions/Characteristics
Parameter Supply Ambient Operati Temperature Total Power Dissipation3 Short Haul VCC, TVCC Long Haul Short Haul/ Long Haul 4.75 Typ1 5.25 Units 100% mark density mark density 100% mark density mark density 100% mark density mark density Test Conditions
Typical figures design only; guaranteed subject production testing. TVCC must differ more than Power dissipation driving load over operating range operation load operation. Includes power dissipation devi load. Digital levels within supply rails gital outputs drivi capacitive load.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table LXT360 Digital Characteristics
Parameter level input voltage (pins 1-4, 23-25) level input voltage (pins 1-4, 23-25) level output voltage (pins 6-8, level output voltage
±1.2
Units
Test Conditions
IOUT IOUT
(pins 6-8,
level input voltage (pins 26-28) drange input voltage (pins 26-28) level input voltage (pins 26-28) Input leakage current Three-state leakage current (all outputs) TTIP/TRING leakage current (pins
Idle Power Down
Functionality depends mode. Host Mode Hardware Mode description Output drivers will output CMOS logic levels CMOS loads. alternati supplying these they left open.
Table LXT361 Digital Characteristics
Parameter level input voltage (pins 1-5, 9-12, 23-28) level input voltage
Units
Test Conditions
(pins 1-5, 9-12, 23-28)
level output voltage (pins 6-8, 11,23, level output voltage (pins 6-8, 11,23, Input leakage current
IOUT
Functionality pins depends mode. Host Mode descri Output drivers will output CMOS logic levels CMOS loads.
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LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Analog Characteristics
Parameter Recommended output load TTIP/TRING Output Pulse Amplitudes DSX-1, CEPT (ITU) Jitter added transmitter2 kHz3 Broad Band Recei sensitivity (T1) Mode (EC1 Long-Haul) Mode (EC1 Long-Haul) Mode (EC4 Short-Haul) Recei Sensitivity 1024 line loss) Mode (EC4-1 1000) Short-Haul/12 Mode (EC4-1 1001 EC4-1 1010) Long-Haul/43 Allowable consecutive zeros before (T1) Allowable consecutive zeros before (E1) Input jitter tolerance (T1) Input jitter tolerance (E1)
Typ1
0.02 0.025 0.025 0.05
Units
Test Conditions
Table Gain Setting
13.6
13.6
selectable data port line (G.823) line AT&T 62411
Jitter attenuation curve corner frequency Recei Return Loss (E1) 2.048 2.048 3.072
Typical figures design only; guaranteed subject production testing. Input signal TCLK jitter-free. Jitter Attenuator receive path sabled. Guaranteed characterization; subject production testing. Circuit attenuates jitter dB/decade above corner frequency.
6-90
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure 2.048 Pulse (See Table
(244+25)
(244-
100%
NOMINAL PULSE
(244-25)
(244+244)
Table 2.048 Pulse Mask Specifications
Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse Ratio positive negative pulse amplitudes center Ratio positive negative pulse amplitudes nomi amplitude ±0.30 95-105 95-105 Coax 2.37 ±0.237 95-105 95-105 Unit
6-91
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure
Normalized Amplitude
1.544 Pulse (DS1 DSX-1) (See Table
Normalized Amplitude
-0.5 Time
Unit Intervals)
DSX-1
-0.5 Time
Unit Intervals)
-0.5
-0.5
Table 1.544 Pulse Mask Corner Point Specifications
Template (per ANSI 403-1995) Minimum Curve Time (UI) -0.77 -0.23 -0.23 -0.15 0.15 0.23 0.23 0.46 0.61 0.93 1.16 Amplitude -0.05 -0.05 0.50 0.90 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05 Maximum Curve Time (UI) -0.77 -0.39 -0.27 -0.27 -0.12 0.27 0.34 0.77 1.16 Amplitude 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 DSX-1 Template (per ANSI 102-1993) Minimum Curve Time (UI) -0.77 -0.23 -0.23 -0.15 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Amplitude -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 Maximum Curve Time (UI) -0.77 -0.39 -0.27 -0.27 -0.27 0.27 0.35 0.93 1.16 Amplitude 0.05 0.05 0.80 0.80 1.15 1.05 1.05 -0.07 0.05 0.05
6-92
LXT360/361 Integrated T1/E1 LH/SH Transceivers Table Master Transmit Clock Timing Characteristics Operation) (Figure
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG hold time MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT Typ1 1.544 1.544 ±100 Units Notes must supplied
Typical figures design only; guaranteed subject production testing.
Table Master Transmit Clock Timing Characteristics Operation) (Figure
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG hold time MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT Typ1 2.048 2.048 ±100 Units Notes must supplied
Typical figures design only; guaranteed subject production testing.
Figure Transmit Clock Timing
TCLK
tSUT
TPOS TNEG
6-93
LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table Receive Timing Characteristics Operation (See Figure
Parameter Recei clock duty cycle Recei clock pulse width Recei clock pulse width Recei clock pulse low1,3 RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold RLCKd tPWH tPWL Typ1 Units
Typical figures design only; guaranteed subject production testing. RCLK duty cycle dths will vary according extent received pulse jitter displacement. RCLK duty cycles worst case jitter conditions. Worst case conditi guaranteed design only.
Table Receive Timing Characteristics Operation (See Figure
Parameter Recei clock duty cycle Recei clock pulse width Recei clock pulse width Recei clock pulse low1,3 RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold RLCKd tPWL Typ1 Units
Typical figures design only; guaranteed subject production testing. RCLK duty cycle widths vary according extent received pulse jitter splacement. RCLK duty cycles worst case jitter conditions (0.4 clock displ acement 1.544 MHz.) Worst case conditi guaranteed design only.
6-94
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure Receive Clock Timing
RCLK
tPWH tSUR
tPWL
RPOS RNEG
LXT360 Host Mode-CLKE LXT361 CR3.PCLKE
tSUR
Parameter Load
RPOS RNEG
LXT360 Host Mode-CLKE= Hardware Mode LXT361 CR3.PCLKE
Table LXT360 Serial Timing Characteristics (See Figures
Parameter Rise/fall time-any digital output SCLK setup time SCLK hold time SCLK time SCLK high time SCLK rise fall time falling edge SCLK rising edge Last SCLK edge rising edge inactive time SCLK valid time SCLK falling edge rising edge high-Z tCDH tCCH tCWH tCDV tCDZ Typ1 Units
Typical figures design only; guaranteed subject production testing.
6-95
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure LXT360 Serial Data Input Timing Diagram
tCDH DATA BYTE tCWH
SCLK
tCDH
CONTROL BYTE
Figure LXT360 Serial Data Output Timing Diagram
CLKE SCLK CLKE High SCLK tCDZ tCCH tCDZ tCCH
6-96
LXT360/361 Integrated T1/E1 LH/SH Transceivers Table LXT361 Intel Parallel Timing Characteristics (See Figure
Parameter width Address valid ling edge falling edge address hold falling edge falling edge falling edge falling edge ling edge falling edge ling edge ling edge pulse width falling edge data valid Data hold time after sing edge rising edge rising edge rising edge address valid hold time after rising edge width Data setup before rising edge Data hold time after rising edge sing edge rising edge hold time after rising edge TLHLL TAVLL TLLAX TLLRL TLLWL TCLRL TCLWL TRLRH TRLDV TRHDX TRHLH TRHAV TRHCH TWLWH TDVWH TWHDX TWHLH TWHCH Units Test Conditions
TWHCH TRHCH
Figure LXT361 Timing Diagram Intel Address/Data
TCLWL TCLRL
TLLRL TLHLL TLLWL TLLAX TAVLL AD0-7_R TRLDV TRLRH
TRHLH TWHLH TRHAV TRHDX
TWLWH AD0-7_W TDVWH TWHDX
6-97
LXT360/361 Integrated T1/E1 LH/SH Transceivers
Table LXT361 16.78 Motorola Parallel Timing Characteristics
(See Figure
Parameter rising edge rising edge high pulse width Address setup falling edge ling edge Address valid hold time ling edge falling edge ling edge falling edge pulse ling edge data Data hold time after rising edge falling edge ling edge Data setup before rising edge Data hold time after rising edge hold time after sing edge hold time after rising edge Symbol TDSHASH TASHASL TAVASL TASLAX TASLDSL TCSLDSL TDSLDSH TDSLDV TDSHDX TRWLDSL TDVDSH TDXDSH TDSHRWH TDSHCSHV Units Test Conditions
Figure
LXT361 Timing Diagram Motorola Address/Data
TCSLDSL TDSHCSH
TASHASL TAVASL
TASLDSL TASLAX TDSLDSH
TDSHASH TDXDSH TDVDSH TDSHRWH
R/W_Read AD0-7_Read R/W_Write AD0-7_Write
TRWLDSL
TDSLDV
TDSHDX
6-98
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure Jitter Tolerance (Typical)
Typical Jitter Tolerance
1000
Jitter
LXT360/LXT361Device Typical Jitter Tolerance Loop Mode
62411
1990
Frequency
Typical Jitter Tolerance
1000
LXT360/LXT361Device Typical Jitter Tolerance
Loop Mode
Jitter
G.823
Template
Slope equivalent dB/decade
Frequency
6-99
LXT360/361 Integrated T1/E1 LH/SH Transceivers Figure Jitter Attenuation (Typical)
G.736 Template
Attenuation
-19.5 -19.5 LXT360/LXT361 Device Performance
Frequency
Figure Jitter Attenuation (Typical)
62411 Slope equivalent dB/decade
Attenuation
33.8 62411 Template LXT360/ LXT361 Device Performance Slope equivalent dB/decade
Frequency
6-100

LXT360/361 Integrated T1/E1 LH/SH Transceivers DS1/DSX-1/CSU NTU/

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