SCBS240A JUNE 1992 REVISED JULY 1994 B-Port Outputs Have Equivale

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SCBS240A JUNE 1992 REVISED JULY 1994 B-Port Outputs Have Equivale

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SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
B-Port Outputs Have Equivalent Series Resistors, External Resistors Required Members Texas Instruments Widebus Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Protection Exceeds 2000 MIL-STD-883C, Method 3015; Exceeds Using Machine Model Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C Distributed Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes Layout Bus-Hold Data Inputs Eliminates Need External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT162260 PACKAGE SN74ABT162260 PACKAGE (TOP VIEW)
description
ABT162260 12-bit 24-bit multiplexed D-type latches used applications where separate data paths must multiplexed onto, demultiplexed from, single data path. Typical applications include multiplexing and/or demultiplexing address data information microprocessor bus-interface applications. These devices also useful memory-interleaving applications.
LE1B LE2B
OE2B LEA2B 2B10 2B11 2B12 1B12 1B11 1B10 LEA1B OE1B
Three 12-bit ports (A1-A12, 1B1-1B12, 2B1-2B12) available address and/or data transfer. output-enable (OE1B, OE2B, OEA) inputs control transceiver functions. OE1B OE2B control signals also allow bank control direction. Address and/or data information stored using internal storage latches. latch-enable (LE1B, LE2B, LEA1B, LEA2B) inputs used control data storage. When latch-enable input high, latch transparent. When latch-enable input goes low, data present inputs latched remains latched until latch-enable input returned high. B-port outputs, which designed sink include series resistors reduce overshoot undershoot. Active bus-hold circuitry provided hold unused floating data inputs valid logic level. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver.
Widebus EPIC-B trademarks Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 1994, Texas Instruments Incorporated
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
description (continued)
SN74ABT162260 available TI's shrink small-outline package (DL), which provides twice count functionality standard small-outline packages same printed-circuit-board area. SN54ABT162260 characterized operation over full military temperature range 55°C 125°C. SN74ABT162260 characterized operation from 40°C 85°C. Function Tables
(OEB INPUTS LE1B LE2B OUTPUT
(OEA INPUTS LEA1B LEA2B OE1B OE2B OUTPUTS Active Active Active Active
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
logic diagram (positive logic)
LE1B LE2B LEA1B LEA2B OE2B
OE1B
Other Channels
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Voltage range applied output high state power-off state, Current into output state, SN54ABT162260 port) SN74ABT162260 port) port Input clamp current, Output clamp current, Maximum power dissipation 55°C still air) (see Note package Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils. more information, refer Package Thermal Considerations application note 1994 Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note
SN54ABT162260 /VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Power-up ramp rate port port Outputs enabled SN74ABT162260 UNIT
Operating free-air temperature NOTE Unused floating control inputs must held high low.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS port port Control inputs ports II(hold) IOZPU IOZPD Ioff ICEX ports 0.55 0.55* -100 0.55 0.55 25°C -1.2 SN54ABT162260 -1.2 SN74ABT162260 -1.2 UNIT
Outputs high Outputs high Outputs Outputs disabled
ICC#
input Other inputs
11.5 products compliant MIL-STD-883, Class this parameter does apply. typical values This parameter characterized tested. parameters IOZH IOZL include input leakage current. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
25°C Pulse duration, LE1B, LE2B, LEA1B, LEA2B high Setup time, data before LE1B, LE2B, LEA1B, LEA2B Hold time, data after LE1B, LE2B, LEA1B, LEA2B SN54ABT162260 SN74ABT162260 UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT162260 SN74ABT162260 UNIT
(1B) (2B)
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT OUTPUTS Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP HOLD TIMES Data Input
Input (see Note tPLH Output
tPHL tPHL tPLH
Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH
tPLZ tPHZ
Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT162260, SN74ABT162260 12-BIT 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS 3-STATE OUTPUTS
SCBS240A JUNE 1992 REVISED JULY 1994
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1995, Texas Instruments Incorporated

SCBS240A JUNE 1992 REVISED JULY 1994 B-Port Outputs Have Equivale

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