Improved System Accuracy Microprocessor Compatible Easily Interfaced R

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Improved System Accuracy Microprocessor Compatible Easily Interfaced R

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DG428/429
Improved System Accuracy Microprocessor Compatible Easily Interfaced Reduced Crosstalk High Throughput Improved Reliability
Single Ch/Differential Latchable Analog Multiplexers
Features
rDS(on): Charge Injection: Board Compatible Address Latches High Speed tTRANS: Break Before Make Power Consumption:
Applications
Data Acquisition Systems Automatic Test Equipment Avionics Military Systems Communication Systems Microprocessor Controlled Analog Systems Medical Instrumentation
Description
DG428/DG429 analog multiplexers have on-chip address control latches simplify design microprocessor based applications. Break-before-make switching action protects against momentary crosstalk adjacent input signals. DG428 selects eight single-ended inputs common output, while DG429 selects four differential inputs common differential output. channel conducts current equally well both directions. state each channel blocks voltages power supply rails. enable (EN) function allows user reset multiplexer/demultiplexer switches stacking several devices. control inputs, address (Ax) enable (EN) compatible over full specified operating temperature range. silicon-gate CMOS process enables operation over wide range supply voltages. absolute maximum voltage rating extended Additionally, single supply operation also allowed epitaxial layer prevents latchup. On-board TTL-compatible address latches simplify digital interface design reduce board space bus-controlled systems such data acquisition systems, process controls, avionics, ATE.
Updates this applications note obtained facsimile calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70063.
Functional Block Diagrams Configurations
P-35401-Rev. (05/02/94)
DG428/429
DG428 Dual-In-Line PLCC View
Latches Decoders/Drivers
DG428
Latches Decoders/Drivers
View
Functional Block Diagrams Configurations (Cont'd)
DG429
Dual-In-Line
DG429 PLCC
View
Latches Decoders/Drivers
Latches Decoders/Drivers
View
Truth Table DG428 8-Channel Single-Ended Multiplexer Switch Latching
Maintains previous switch condition
Truth Table DG429 Differential 4-Channel Multiplexer Switch Latching
Maintains previous switch condition
Reset
Reset
P-35401-Rev. (05/02/94)
None (latches cleared)
DG428/429
None (latches cleared)
Transparent Operation
None
Transparent Operation
None
Logic Logic Don't Care
Ordering Information Temp Range
85_C 125_C
DG428 Part Number
DG428DJ DG428DN DG428AK DG428AK/883
Ordering Information Temp Range
85_C 125_C
DG429 Part Number
DG429DJ DG429DN DG429AK DG429AK/883
Package
18-Pin Plastic 20-Pin PLCC 18-Pin CerDIP
Package
18-Pin Plastic 20-Pin PLCC 18-Pin CerDIP
P-35401-Rev. (05/02/94)
DG428/429
Absolute Maximum Ratings
Voltage Referenced Digital Inputsa, (V-) (V+) whichever occurs first Current (Any Terminal)
(Pulsed Duty Cycle Max) Storage Temperature Suffix) 150_C (DJ, Suffix) 125_C Power Dissipation (Package)b 18-Pin Plastic DIPc 18-Pin CerDIPd 20-Pin PLCCe
Peak Current, Notes: Signals exceeding will clamped internal diodes. Limit forward diode current maximum current ratings. leads soldered welded board. Derate mW/_C above 75_C. Derate mW/_C above 75_C. Derate mW/_C above 75_C.
Specificationsa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Greatest Change rDS(on) Between Channelsg Source Leakage Current VANALOG rDS(on) DrDS(on) IS(off) DG428 Full Room Full Room Room Full Room Full Room Full Room Full Room Full "0.0 "0.0 "0.0 "0.0 "0.0 -0.5 -100 -100 -0.5 -100 -100
Suffix
125_C
Suffix
85_C
Symbol
Tempb Typc
Mind Maxd Mind Maxd
Drain Leakage Current
ID(off)
DG429
Drain Leakage Current
ID(on)
DG428
DG429
Digital Control
Logic Input Current Input Voltage High Logic Input Current Input Voltage Logic Input Capacitance Full Full Full Room 0.01 0.01 -0.01
Dynamic Characteristics
P-35401-Rev. (05/02/94)
Transition Time Break-Before-Make Interval Enable Write Turn-On Time Enable Reset Turn-Off Time Charge Injection Isolation Source Capacitance Drain Capacitance Drain Capacitance tTRANS tOPEN tON(EN,
DG428/429
Figure Figure Figures Figures VGEN RGEN Figure VRMS, DG428 DG429 DG428 DG429 Room Full Full Room Full Room Full Room Room Room Room Room Room Room
tOFF(EN,
OIRR CS(off) CD(off) CD(on)
P-35401-Rev. (05/02/94)
DG428/429
Specificationsa (Cont'd)
Test Conditions Unless Otherwise Specified Parameter Symbol
Suffix
125_C
Suffix
85_C
Tempb Typc
Mind Maxd Mind Maxd
Minimum Input Timing Requirements
Write Pulse Width Data time Data Hold Time Reset Pulse Width Figure Figure Full Full Full Full
Power Supplies
Positive Supply Current Negative Supply Current Room Room -0.00
Specificationsa Single Supply
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance rDS(on) Matchg Source Leakage Current VANALOG rDS(on) DrDS(on) IS(off) -500 DG428 Full Room Room Room Full Room Full Room Full Room Full Room Full "0.0 "0.0 "0.0 "0.0 "0.0 -0.5 -100 -100 -0.5 -100 -100
Suffix
125_C
Suffix
85_C
Symbol
Temp
Typc
Unit
Drain Leakage Current
ID(off)
DG429
Drain Leakage Current
ID(on)
DG428
DG429
Digital Control
Logic Input Current Input Voltage High Logic Input Current Input Voltage Full Full Full
Dynamic Characteristics
P-35401-Rev. (05/02/94)
Transition Time Break-Before-Make Interval Enable Write Turn-On Time Enable Reset Turn-Off Time Charge Injection Isolation tTRANS tOPEN tON(EN,
DG428/429
Figure Figure Figures Figures VGEN RGEN Figure VRMS, Room Full Room Full Room Full Room Full Room Room
tOFF(EN,
OIRR
Specificationsa Single Supply (Cont'd)
Test Conditions Unless Otherwise Specified Parameter Symbol
Suffix
125_C
Suffix
85_C
Temp
Typc
Unit
Minimum Input Timing Requirements
Write Pulse Width Data Time Data Hold Time Reset Pulse Width Figure Figure Full Full Full Full
Power Supplies
Positive Supply Current Notes: Refer PROCESS OPTION FLOWCHART (Section 1994 Data Book FaxBack number 7103). Room 25_C, Full determined operating temperature suffix. Typical values DESIGN ONLY, guaranteed subject production testing. algebraic convention whereby most negative value minimum most positive maximum, used this data sheet. Guaranteed design, subject production test. input voltage perform proper function. DS(on) DS(on) 100% DS(on)
DS(on)
Room
P-35401-Rev. (05/02/94)
DG428/429
Typical Characteristics
P-35401-Rev. (05/02/94)
rDS(on) Drain-Source On-Resistance
DG428/429
rDS(on) Supply Voltage
rDS(on) Drain-Source On-Resistance Drain Voltage -40_C 25_C -55_C 125_C 85_C
Temperature
Drain Voltage
rDS(on) Drain-Source On-Resistance
Single Supply rDS(on) Supply
Leakage Currents Analog Voltage
ID(off) ID(on)
Current (pA)
IS(off) ID(on), ID(off)
Drain Voltage
VS,VD Source, Drain Voltage
Leakages Temperature
Switching Times Power Supply Voltage
Leakage Current
Time (ns) (off) ID(on), ID(off)
tTRANS
tON(EN) tOFF(EN)
Temperature (C_)
Supply Voltage
P-35401-Rev. (05/02/94)
DG428/429
Typical Characteristics (Cont'd)
P-35401-Rev. (05/02/94)
Switching Times Single Supply
Charge (pC) Time (ms) tTRANS tOFF
DG428/429
Charge Injection Analog Voltage
Positive Supply
Source Voltage
Off-Isolation Frequency
-140 -120 -100 OIRR (dB) Frequency (Hz) Supply Current (ma)
Supply Current Switching Frequency
IGND
Frequency (Hz)
Switching Times Temperature
Time (nS) tTRANS
Input Switching Threshold Supply Voltage
tOFF
Temperature (C_)
VSUPPLY Supply Voltage
P-35401-Rev. (05/02/94)
DG428/429
Schematic Diagram (Typical Channel)
VREF
Level Shift Decode/ Drive
Latches RESET
Figure
Detailed Description
internal structure DG428/DG429 includes logic interface with input protection circuitry followed latch, level shifter, decoder finally switch constructed with parallel p-channel MOSFETs (see Figure input, subject "Minimum Input Timing Requirements" table.
input protection logic lines control lines shown Figure minimizes susceptibility that encountered during handling operational transients.
Following latches signals level shifted decoded provide proper drive levels CMOS switches. This level shifting ensures full on/off switch operation analog signal level between supply rails.
logic interface CMOS logic input with supply voltage from internal reference voltage. output input inverter feeds data input type latch. level sensitive latch continuously places input signal output when input low, resulting transparent latch operation. soon returns high latch holds data last present
used enable address latches during pulse. hard wired logic supply channels will always used (except during reset) tied address decoding circuitry memory mapped operation. used master reset. latches cleared regardless state other latch control line. used transfer state address control lines their latches, except during reset when (see Truth Tables).
P-35401-Rev. (05/02/94)
DG428/429
Switch Output tOFF(RS)
Timing Diagrams
(A2)
Figure
Figure
Test Circuits
+2.4 Logic Input
DG428 DG429
(A2) Switch Output
tOPEN
Figure Break-Before-Make
P-35401-Rev. (05/02/94)
DG428/429
DG428 Switch Output S4a, +2.4
Logic Input
+2.4
tTRANS
tTRANS
DG429
Figure Transition Time
Test Circuits (Cont'd)
P-35401-Rev. (05/02/94)
DG428/429
DG428
+2.4
Logic Input tON(EN) tOFF(EN)
Switch Output
+2.4
DG429
S4a,
Figure Enable tON/tOFF Time
+2.4
(A2) Remaining Switches
Switch Output tON(WR)
DG428
DG429
Figure Write Turn-On Time tON(WR)
P-35401-Rev. (05/02/94)
DG428/429
Test Circuits (Cont'd)
+2.4
(A2) Remaining Switches
tOFF(RS) Switch Output
DG42 DG429
Figure Reset Turn-Off Time tOFF(RS)
(A2)
measured voltage error charge injection. charge coulombs
Figure Charge Injection
Applications
Interfacing
DG428/DG429 minimize amount interface hardware between microprocessor system analog system being controlled measured. internal compatible latches give these multiplexers write-only memory, that they programmed stay particular switch state (e.g., switch until microprocessor determines necessary turn different switches turn switches (see Figure 10). input latches become transparent when held low; therefore, these multiplexers operate direct command coded switch state this mode DG428 identical popular DG408. same true DG429 versus popular DG409.
P-35401-Rev. (05/02/94)
During system power-up, would low, maintaining eight switches state. After returned high DG428 maintains switches state.
DG428/429
Applications (Cont'd)
When system program performs write operation address assigned DG428, address decoder provides active signal which gated with WRITE (WR) control signal. this time data DATA (that will determine which switch close) stabilizing. When signal returns high state, (positive edge) input latches DG428 save data from DATA BUS. coded information latches decoded appropriate switch turned
latch allows switches turned under program control. This becomes useful when more DG428s cascaded build 16-line larger multiplexers.
Analog Inputs
Data
DG428
Processor System RESET WRITE Address Address Decoder Analog Output
Figure Interface
P-35401-Rev. (05/02/94)

Improved System Accuracy Microprocessor Compatible Easily Interfaced R

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