Bandwidth, Rail-to-Rail Gain Bandwidth Product (typ.) Supply Curr

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Bandwidth, Rail-to-Rail Gain Bandwidth Product (typ.) Supply Curr

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MCP6271/2/3/4/5
Bandwidth, Rail-to-Rail
Gain Bandwidth Product (typ.) Supply Current: (typ.) Supply Voltage: 2.0V 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40°C +125°C Available Single, Dual Quad Packages Single with Chip Select (CS) (MCP6273) Dual with Chip Select (CS) (MCP6275)
Description
Microchip Technology Inc. MCP6271/2/3/4/5 family operational amplifiers amps) provide wide bandwidth current. This family gain bandwidth product (GBWP) phase margin. This family also operates from single supply voltage 2.0V, while drawing (typ.) quiescent current. Additionally, MCP6271/2/3/4/5 supports rail-to-rail input output swing, with common mode input voltage range This family operational amplifiers designed with Microchip's advanced CMOS process. MCP6275 chip select line (CS) dual amps 8-pin package manufactured cascading amps (the output connected non-inverting input chip select line puts device Power mode. MCP6271/2/3/4/5 family operates Extended Temperature Range -40°C +125°C, with power supply range 2.0V 5.5V.
Applications
Automotive Portable Equipment Photo Diode Pre-amps Analog Filters Notebooks PDAs Battery-Powered Systems
Available Tools
SPICE Macro Model www.microchip.com) FilterLab® Software www.microchip.com)
Package Types
MCP6271 PDIP, SOIC, MSOP
VIN_
MCP6272 PDIP, SOIC, MSOP
VOUTA VINA_ VOUTB VINB_ VINB+
Typical Applications
VIN+
VOUT VINA+
MCP6273 PDIP, SOIC, MSOP
VOUT VIN_ VIN+ VOUT
MCP6274 PDIP, SOIC, TSSOP
VOUTA VINA_ VINA+ VINB_ VOUTB VINB+
VOUTD
VIND_ VIND+
VINC+ VOUTC
MCP6275
Cascaded Gain with Chip Select
MCP6275 PDIP, SOIC, MSOP
VOUTA VINB+ VINA_
VOUTB
VINB
VINA+
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MCP6271/2/3/4/5
ELECTRICAL CHARACTERISTICS FUNCTION TABLE
Name VIN+, VINA+, VINB+, VINC+, VIND+ VIN_, VINA_, VINB_, VINC_, VIND_ VOUT, VOUTA, VOUTB, VOUTC, VOUTD VOUTA/VINB+ Function Non-inverting Inputs Inverting Inputs Positive Power Supply Negative Power Supply Outputs Internal Connection Chip Select Output non-inverting input (MCP6275)
Absolute Maximum Ratings
.7.0V Inputs Outputs 0.3V 0.3V Difference Input Voltage |VDD VSS| Output Short Circuit Current .continuous Current Input Pins Current Output Supply Pins .±30 Storage Temperature.-65°C +150°C Junction Temperature (TJ) .+150°C Protection Pins (HBM/MM) kV/400V Notice: Stresses above those listed under "Maximum Ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operational listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VDD/2 VOUT VDD/2. Parameters Input Offset Input Offset Voltage Input Offset Voltage (Extended Temperature) Input Offset Temperature Drift Power Supply Rejection Input Bias Current Impedance Input Bias Current Temperature Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode (Note Common Mode Input Range Common Mode Rejection Ratio Common Mode Rejection Ratio VCMR CMRR CMRR Note -0.3V 2.5V, -0.3V 5.3V, ZDIFF ±1.0 ±1.0 1013||6
Units
Conditions
VOS/TA PSRR
-3.0 -5.0
±1.7
+3.0 +5.0
(Note -40°C +125°C, (Note
µV/°C -40°C +125°C, (Note ||pF ||pF (Note Note +85°C (Note +125°C (Note Note Note Note
Note
MCP6275 VINB- MCP6275 specified only. This specification VOUTA/VINB+ MCP6275 does apply. common mode (VCM) range MCP6295 maximum voltage limit VOUTA/VINB+ specified VOL.
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ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VDD/2 VOUT VDD/2. Parameters Open-Loop Gain Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current Amplifier VOL, VOUT 0.2V 0.2V, VSS, Note Units Conditions
Note
MCP6275 VINB- MCP6275 specified only. This specification VOUTA/VINB+ MCP6275 does apply. common mode (VCM) range MCP6295 maximum voltage limit VOUTA/VINB+ specified VOL.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2 Parameters Response Gain Bandwidth Product Phase Margin Unity Gain Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density µVp-p nV/Hz fA/Hz GBWP V/µs Units Conditions
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +2.0V +5.5V GND. Parameters Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note: °C/W °C/W °C/W °C/W °C/W °C/W +125 +150 Note Units Conditions
Junction Temperature (TJ) must exceed Absolute Maximum specification +150°C.
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MCP6271/2/3/4/5
MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2 Parameters Specifications Logic Threshold, Input Current, High Specifications Logic Threshold, High Input Current, High Current Amplifier Output Leakage Dynamic Specifications (Note Valid Amplifier Output, Turn-on Time High Amplifier Output High-Z Hysteresis Note VDD, V/V, VDD/2, VOUT VDD/2, 5.0V High VDD, V/V, VDD/2, VOUT VDD/2 ICSH -0.7 0.01 ICSL 0.01 Units Conditions
tOFF VHYST
0.01
input condition (VIN) specified applies both MCP6275. dynamic specification tested output (VOUTB).
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Note:
TYPICAL PERFORMANCE CURVES
graphs tables provided following this note statistical summary based limited number samples provided informational purposes only. performance characteristics listed herein tested guaranteed. some graphs tables, data presented outside specified operating range (e.g., outside specified power supply range) therefore outside warranted range.
Note: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2
Percentage Occurrences
Percentage Occurrences
Samples
Samples -40°C +125°C
-3.0
-2.4
-1.8
-1.2
-0.6
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Percentage Occurrences
Percentage Occurrences
Samples
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-2: +85°C.
Input Bias Current with
FIGURE 2-5: +125°C.
Input Bias Current with
Input Offset Voltage (µV)
-100 -0.4 -0.2 +125°C +85°C +25°C -40°C
Input Offset Voltage (µV)
-100 -0.5 +125°C +85°C +25°C -40°C
Common Mode Input Voltage
Common Mode Input Voltage
FIGURE 2-3: Input Offset Voltage Common Mode Input Voltage with 2.0V.
FIGURE 2-6: Input Offset Voltage Common Mode Input Voltage with 5.5V.
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Input Offset Voltage Drift (µV/°C)
Input Offset Voltage Drift.
Samples +125
MCP6271/2/3/4/5
Note: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2
10,000
Input Offset Voltage (µV)
-100 2.0V 5.5V
Input Bias, Offset Currents (pA)
Representative Part
5.5V 1,000
Input Bias Current Input Offset Current
Output Voltage
Ambient Temperature (°C)
FIGURE 2-7: Output Voltage.
Input Offset Voltage
FIGURE 2-10: Input Bias, Input Offset Currents Ambient Temperature.
CMRR PSRRPSRR+
5.0V
CMRR, PSRR (dB)
PSRR, CMRR (dB)
CMRR
PSRR
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
100k
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-8: CMRR, PSRR Frequency with 5.0V.
FIGURE 2-11: Temperature.
CMRR, PSRR Ambient
Input Bias, Offset Currents (pA)
Input Bias, Offset Currents (nA)
Input Offset Current +85°C 5.5V Input Bias Current
-0.5 -1.0
+125 5.5V Input Bias Current
Input Offset Current
Common Mode Input Voltage
Common Mode Input Voltage
FIGURE 2-9: Input Bias, Input Offset Currents Common Mode Input Voltage with +85°C.
FIGURE 2-12: Input Bias, Input Offset Currents Common Mode Input Voltage with +125°C.
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Note: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2
1000
Ouput Voltage Headroom (mV)
Quiescent Current (µA/amplifier)
+125°C +85°C +25°C -40°C
0.01
Power Supply Voltage
Output Current Magnitude (mA)
FIGURE 2-13: Quiescent Current Power Supply Voltage.
Gain Phase
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
FIGURE 2-16: Output Voltage Headroom Output Current Magnitude.
Gain Bandwidth Product 5.5V Phase Margin 2.0V 5.5V
Gain-Bandwidth Product (MHz)
Open-Loop Gain (dB)
Open-Loop Phase
-120 -150 -180 -210 100k 100M
1.E+08 1.E-01
2.0V
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-14: Frequency.
Open-Loop Gain, Phase
FIGURE 2-17: Gain Bandwidth Product, Phase Margin Ambient Temperature.
Falling Edge, 5.5V Falling Edge, 2.0V
Maximum Output Voltage Swing (VP-P)
5.5V
Slew Rate (V/µs)
2.0V
Rising Edge, 5.5V Rising Edge, 2.0V
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
100k
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-15: Maximum Output Voltage Swing Frequency.
FIGURE 2-18: Temperature.
Slew Rate Ambient
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Phase Margin
MCP6271/2/3/4/5
Note: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2
1,000
Input Noise Voltage Density (nV/
Input Noise Voltage Density (nV/
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
100k
Frequency (Hz)
Common Mode Input Voltage
FIGURE 2-19: Frequency.
Input Noise Voltage Density
FIGURE 2-22: Input Noise Voltage Density Common Mode Input Voltage kHz.
Channel-to-Channel Separation (dB)
Ouptut Short Circuit Current (mA)
+125°C +85°C +25°C -40°C
Power Supply Voltage
Frequency (kHz)
FIGURE 2-20: Output Short-Circuit Current Power Supply Voltage.
FIGURE 2-23: Channel-to-Channel Separation Frequency (MCP6272 MCP6274).
Op-Amp shuts here
5.5V
Quiescent Current (µA)
Quiescent Current (µA)
Op-Amp toggles On/Off here Hysteresis swept high
Op-Amp turns here Hysteresis swept high swept high
swept high
Chip Select Voltage
Chip-Select Voltage
FIGURE 2-21: Quiescent Current Chip Select (CS) Voltage with 2.0V (MCP6273 MCP6275 only).
FIGURE 2-24: Quiescent Current Chip Select (CS) Voltage with 5.5V (MCP6273 MCP6275 only).
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Note: Unless otherwise indicated, +25°C, +2.0V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2
+1V/V 5.0V -1V/V 5.0V
Output Voltage
Output Voltage
Time µs/div)
Time µs/div)
FIGURE 2-25: Pulse Response.
Large Signal Non-inverting
FIGURE 2-28: Response.
Large Signal Inverting Pulse
+1V/V
-1V/V
Output Voltage mV/div)
Time µs/div)
Output Voltage mV/div)
Time µs/div)
FIGURE 2-26: Pulse Response.
Small Signal Non-inverting
FIGURE 2-29: Response.
Small Signal Inverting Pulse
Chip-Select, Output Voltages
Chip-Select, Output Voltages
Voltage
2.0V +1V/V
Voltage
5.5V +1V/V
VOUT Output
VOUT
Output High-Z
-5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0
Output High-Z
Output
Time µs/div)
Time µs/div)
FIGURE 2-27: Chip Select (CS) Amplifier Output Response Time with 2.0V (MCP6273 MCP6275 only).
FIGURE 2-30: Chip Select (CS) Amplifier Output Response Time with 5.5V (MCP6273 MCP6275 only).
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APPLICATION INFORMATION
MCP6271/2/3/4/5 family amps manufactured using Microchip's state-of-the-art CMOS process, specifically designed low-cost, low-power general-purpose applications. supply voltage, quiescent current wide bandwidth makes MCP6271/2/3/4/5 ideal battery-powered applications.
MCP6271
VOUT
Rail-to-Rail Input
MCP6271/2/3/4/5 amps designed prevent phase reversal when input pins exceed supply voltages. Figure shows input voltage exceeding supply voltage without phase reversal.
Maximum expected Minimum expected
FIGURE 3-2: Resistor (RIN).
Input Current Limiting
Input, Output Voltage
Rail-to-Rail Output
5.0V
VOUT
output voltage range MCP6271/2/3/4/5 (min.) (max.) when connected VDD/2 5.5V. Refer Figure 2-16 more information.
MCP6273/5 Chip Select (CS)
Time ms/div)
FIGURE 3-1: MCP6271/2/3/4/5 Show Phase Reversal.
input stage MCP6271/2/3/4/5 uses differential input stages parallel. operates common mode input voltage (VCM) other high VCM. With this topology, device operates with above below VSS. Input Offset Voltage measured ensure proper operation. Input voltages that exceed input voltage range (VSS 0.3V 0.3V 25°C) cause excessive current flow into input pins. Current beyond cause reliability problems. Applications that exceed this rating must externally limited with resistor, shown Figure 3-2.
MCP6273 MCP6275 single dual amps with chip select (CS), respectively. When pulled high, supply current drops (typ) flows through VSS. When this happens, amplifier output into high-impedance state. pulling low, amplifier enabled. left floating, amplifier operate properly. Figure shows output voltage supply current response pulse.
toff Hi-Z -170
VOUT
Hi-Z
IVSS
-0.7
-0.7
FIGURE 3-3: Timing Diagram Chip Select (CS) MCP6273 MCP6275.
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MCP6271/2/3/4/5
Cascaded Dual Amps (MCP6275) Capacitive Loads
Driving large capacitive loads cause stability problems voltage-feedback amps. load capacitance increases, feedback loop's phase margin decreases closed-loop bandwidth reduced. This produces gain peaking frequency response, with overshoot ringing step response. unity-gain buffer most sensitive capacitive loads, though gains show same general behavior. When driving large capacitive loads with these amps (e.g., when +1), small series resistor output (RISO Figure 3-5) improves feedback loop's phase margin (stability) making output load resistive higher frequencies. bandwidth will generally lower than bandwidth with capacitive load.
MCP6275 dual with chip select (CS). chip select line available what would non-inverting input standard dual (pin This feature provided connecting output non-inverting input shown Figure 3-4. chip select line, which connected microcontroller line, puts device Power mode. Refer Section "MCP6273/5 Chip Select (CS)".
VOUTA/VINB+ VINA- VINA+ MCP6275 VINB-
VOUTB
RISO VOUT
MCP6271
FIGURE 3-4:
Cascaded Gain Amplifier. FIGURE 3-5: Output Resistor, RISO stabilizes large capacitive loads.
Figure gives recommended RISO values different capacitive loads gains. x-axis normalized load capacitance (CL/GN), where circuit's noise gain. non-inverting gains, Signal Gain equal. inverting gains, 1+|Signal Gain| (e.g., gives V/V).
1,000 Recommended
issue note from this configuration that output loaded input impedance input offset current (IOS) input impedance typically 10136 specified specification table (Refer Section "Capacitive Loads" further details regarding capacitive loads). +85°C +125°C (VDD 5.5V) sinks into output This shown Figures 2-12. common mode input range these amps specified data sheet However, since output limited from rails with load), non-inverting input range limited common mode input range
1,000 10,000 Normalized Load Capacitance; (pF)
FIGURE 3-6: Recommended RISO values Capacitive Loads.
After selecting RISO your circuit, double-check resulting frequency response peaking step response overshoot. Modify RISO's value until response reasonable. Bench evaluation simulations with MCP6271/2/3/4/5 SPICE macro model very helpful.
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Supply Bypass
3.8.1
Application Circuits
ACTIVE FULL-WAVE RECTIFIER
With this family operational amplifiers, power supply (VDD single supply) should have local bypass capacitor (i.e., 0.01 within good, high-frequency performance. also needs bulk capacitor (i.e., larger) within provide large, slow currents. This bulk capacitor shared with other parts.
Surface Leakage
applications where input bias current critical, printed circuit board (PCB) surface leakage effects need considered. Surface leakage caused humidity, dust other contamination board. Under humidity conditions, typical resistance between nearby traces 1012. difference would cause current-to-flow. This greater than MCP6271/2/3/4/5 family's bias current 25°C typ.). easiest reduce surface leakage guard ring around sensitive pins traces). guard ring biased same voltage sensitive pin. example this type layout illustrated Figure 3-7. VIN- VIN+
MCP6271/2/3/4/5 family amplifiers used applications such Active Full-Wave Rectifier Absolute Value circuit, shown Figure 3-8. amplifier feedback loops this active voltage rectifier circuit eliminate diode drop problem that exists passive voltage rectifier. This circuit behaves follower (the output follows input) long input signal more positive than reference voltage. input signal more negative than reference voltage, however, circuit behaves inverting amplifier. Therefore, output voltage will always above reference voltage, regardless input signal.
MCP6272
VOUT
VREF
Guard Ring
MCP6272
VREF
FIGURE 3-7: Inverting Gain.
Example Guard Ring Layout
Inverting (Figure 3-7) Transimpedance Amplifiers (convert current voltage, such photo detectors): Connect guard ring non-inverting input (VIN+). This biases guard ring same reference voltage (e.g., VDD/2 ground). Connect inverting (VIN-) input with wire that does touch surface. Non-inverting Gain Unity-Gain Buffer: Connect non-inverting (VIN+) input with wire that does touch surface. Connect guard ring inverting input (VIN-). This biases guard ring common mode input voltage.
Input
Output
VREF
VREF
time
time
FIGURE 3-8:
Active Full-wave Rectifier.
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3.8.2 NON-INVERTING INTEGRATOR 3.8.3
non-inverting integrator shown Figure easy build. saves over typical Miller Integrator plus inverting amplifier configuration. phase accuracy this integrator depends matching input feedback resistors, capacitor's time constants. used provide feedback frequencies 1/(2 RC).
CASCADED AMPS APPLICATIONS
MCP6271 VOUT
MCP6275 provides flexibility power mode dual amps 8-pin package. MCP6275 eliminates added cost space battery-powered application using single amps with chip select lines 10-pin device with chip select line each amp. only inherent limitation this device that amps internally cascaded. Therefore, this device cannot used circuits that require active passive elements between amps. However, there several applications where this configuration with chip select line becomes suitable. circuits below show possible applications this device.
3.8.3.1
Load Isolation
With cascaded configuration, used isolate load from applications where driving capacitive resistive loads feedback loop (such integrator filter circuit) have sufficient source current drive load. this case, used buffer.
FIGURE 3-9:
Non-Inverting Integrator.
VOUTB
MCP6275
FIGURE 3-10: Buffer. 3.8.3.2
Isolating Load
Cascaded Gain
Figure 3-11 shows cascaded gain circuit configuration with chip select. amps configured non-inverting amplifier configuration. this configuration, important note that input offset voltage amplified gain shown below: Where: VOSA VOSB gain gain offset voltage offset voltage
Therefore, recommended that most gain with with relatively small gain, unity-gain buffer.
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VOUT
VOUT
MCP6275
FIGURE 3-11: Configuration. 3.8.3.3
Cascaded Gain Circuit
FIGURE 3-13: Compensation. 3.8.3.5
Integrator Circuit with Active
Difference Amplifier
Figure 3-12 shows configured difference amplifier with chip select. this configuration, recommended that well-matched resistors (0.1%) used increase common mode rejection ratio (CMRR). used provide additional gain isolate load from difference amplifier.
VIN2 VIN1 VOUT
Second-Order with extra pole-zero pair
Figure 3-14 second-order multiple feedback lowpass filter with chip select. Filterlab® software from Microchip determine values second-order filter. used pole-zero pair using
VOUT
MCP6275
MCP6275
FIGURE 3-12: 3.8.3.4
Difference Amplifier Circuit.
Integrator with Active Compensation Chip Select
FIGURE 3-14: Second-Order Multiple Feedback Low-Pass Filter with Extra PoleZero Pair Chip Select.
Figure 3-13 uses active compensator compensate non-ideal characteristics introduced higher frequency integration. alternative passive element (such resistor) compensation. However, quality compensation would constant since characteristics amplifier vary over temperature process. This circuit uses unity-gain buffer isolate integration capacitor from drives capacitor with low-impedance source. Since both amplifiers matched very well, provides higher quality integration.
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3.8.3.6 Second-Order Sallen-Key with Extra Pole-Zero Pair 3.8.3.7 Capacitorless Second Order Low-Pass filter with Chip Select
Figure 3-15 second-order Sallen-Key low-pass filter with chip select. Filterlab® software from Microchip determine values second-order filter. used pole-zero pair using
low-pass filter shown Figure 3-16 does require external capacitors uses only three external resistors, while amp's GBWP sets corner frequency. used circuit gain. used avoid gain-peaking frequency response, needs (lower values need selected R3). Note that amplifier bandwidth varies greatly over temperature process. This configuration, however, provides lowcost solution applications with high bandwidth.
VOUT
MCP6275
FIGURE 3-15: Second Order Sallen-Key Low-Pass Filter with Extra Pole-Zero Pair Chip Select.
VREF
VOUT
FIGURE 3-16: Capacitorless Second-Order Low-Pass Filter with Chip Select Circuit.
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DESIGN TOOLS
Microchip provides basic design tools needed MCP6271/2/3/4/5 family amps.
SPICE Macro Model
latest version SPICE Macro Model MCP6271/2/3/4/5 available site www.microchip.com. This model intended initial design tool that works well amp's linear region operation room temperature. model file information capabilities. Bench testing very important part design cannot replaced with simulations. Also, simulation results using this macro model need validated comparing them data sheet specifications characteristic curves.
FilterLab® Software
FilterLab software innovative tool that simplifies analog active-filter (using amps) design. Available cost from site (www.microchip.com), FilterLab active-filter software design tool provides full schematic diagrams filter circuit with component values. also outputs filter circuit SPICE format, which used with macro model simulate actual filter performance.
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PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP XXXXXX YWWNNN Example: 6271 406256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP6271 E/P256 0406
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW
Example: MCP6271 E/SN0406
Legend:
XX.X
Customer specific information* Year code (last digits calendar year) Week code (week January week `01') Alphanumeric traceability code
Note:
event full Microchip part number cannot marked line, will carried over next line thus limiting number available characters customer specific information.
Standard marking consists Microchip part number, year code, week code, traceability code (facility code, mask rev#, assembly code). marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
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Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6274) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP6274-E/P 0409057
14-Lead SOIC (150 mil) (MCP6274)
Example:
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP6274ESL 0409057
14-Lead TSSOP (MCP6274)
Example:
XXXXXX YYWW
6274ST 0409
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8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Number Pins .026 Pitch .043 Overall Height .030 .033 .037 Molded Package Thickness .000 .006 Standoff .193 TYP. Overall Width .118 Molded Package Width .118 Overall Length .016 .024 .031 Foot Length Footprint (Reference) .037 Foot Angle Lead Thickness .003 .006 .009 Lead Width .009 .012 .016 Mold Draft Angle Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side.
Units Dimension Limits
INCHES
MILLIMETERS* 0.65 0.75 0.85 0.00 4.90 3.00 3.00 0.40 0.60 0.95 0.08 0.22
1.10 0.95 0.15
0.80 0.23 0.40
JEDEC Equivalent: MO-187
Drawing C04-111
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MCP6271/2/3/4/5
8-Lead Plastic Dual In-line (PDIP)
Number Pins Pitch Seating Plane Molded Package Thickness Base Seating Plane Shoulder Shoulder Width Molded Package Width Overall Length Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Spacing Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
INCHES* .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430
MILLIMETERS 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-001 Drawing C04-018
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MCP6271/2/3/4/5
8-Lead Plastic Small Outline (SN) Narrow, (SOIC)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
.053 .052 .004 .228 .146 .189 .010 .019 .008 .013
INCHES* .050 .061 .056 .007 .237 .154 .193 .015 .025 .009 .017
.069 .061 .010 .244 .157 .197 .020 .030 .010 .020
MILLIMETERS 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0.20 0.23 0.33 0.42
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 0.25 0.51
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-012 Drawing C04-057
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DS21810C-page
MCP6271/2/3/4/5
14-Lead Plastic Dual In-line (PDIP)
Number Pins Pitch Seating Plane .140 .170 Molded Package Thickness .115 .145 Base Seating Plane .015 Shoulder Shoulder Width .300 .313 .325 Molded Package Width .240 .250 .260 Overall Length .740 .750 .760 Seating Plane .125 .130 .135 Lead Thickness .008 .012 .015 Upper Lead Width .045 .058 .070 Lower Lead Width .014 .018 .022 Overall Spacing .310 .370 .430 Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-001 Drawing C04-005
Units Dimension Limits
INCHES* .100 .155 .130
MILLIMETERS 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92
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MCP6271/2/3/4/5
14-Lead Plastic Small Outline (SL) Narrow, (SOIC)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
.053 .052 .004 .228 .150 .337 .010 .016 .008 .014
INCHES* .050 .061 .056 .007 .236 .154 .342 .015 .033 .009 .017
.069 .061 .010 .244 .157 .347 .020 .050 .010 .020
MILLIMETERS 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0.20 0.23 0.36 0.42
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 0.25 0.51
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .010" (0.254mm) side. JEDEC Equivalent: MS-012 Drawing C04-065
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MCP6271/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) (TSSOP)
Number Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Mold Draft Angle Bottom Controlling Parameter Significant Characteristic
Units Dimension Limits
INCHES .026 .035 .004 .251 .173 .197 .024 .006 .010
.033 .002 .246 .169 .193 .020 .004 .007
.043 .037 .006 .256 .177 .201 .028 .008 .012
MILLIMETERS* 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0.09 0.15 0.20 0.19 0.25 0.30
Notes: Dimensions include mold flash protrusions. Mold flash protrusions shall exceed .005" (0.127mm) side. JEDEC Equivalent: MO-153 Drawing C04-087
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MCP6271/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
order obtain information, e.g., pricing delivery, refer factory listed sales office. PART Device Temperature Range Package Examples:
Device: MCP6271: MCP6271T: MCP6272: MCP6272T: MCP6273: MCP6273T: MCP6274: MCP6274T: MCP6275: MCP6275T: Single Operational Amplifier Single Operational Amplifier (Tape Reel) (SOIC, MSOP) Dual Operational Amplifiers Dual Operational Amplifiers (Tape Reel) (SOIC, MSOP) Single Operational Amplifier with Chip Select Single Operational Amplifier with Chip Select (Tape Reel) (SOIC, MSOP) Quad Operational Amplifiers Quad Operational Amplifiers (Tape Reel) (SOIC, TSSOP) Dual Operational Amplifier with Chip Select Dual Operational Amplifier with Chip Select (Tape Reel) (SOIC, MSOP) Extended Temperature, SOIC package. MCP6271-E/MS: Extended Temperature, MSOP package. MCP6271-E/P: Extended Temperature, PDIP package. MCP6271T-E/SN: Tape Reel, Extended Temperature, SOIC package. Extended Temperature, SOIC package. MCP6272-E/MS: Extended Temperature, MSOP package. MCP6272-E/P: Extended Temperature, PDIP package. MCP6272T-E/SN: Tape Reel, Extended Temperature, SOIC package. Extended Temperature, SOIC package. MCP6273-E/MS: Extended Temperature, MSOP package. MCP6273-E/P: Extended Temperature, PDIP package. MCP6273T-E/SN: Tape Reel, Extended Temperature, SOIC package. MCP6274-E/P: MCP6274T-E/SL: Extended Temperature, 14LD PDIP package. Tape Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. MCP6273-E/SN: MCP6272-E/SN: MCP6271-E/SN:
Temperature Range:
-40°C +125°C
Package:
Plastic MSOP, 8-lead Plastic (300 Body), 8-lead, 14-lead Plastic SOIC, (150 Body), 8-lead Plastic SOIC (150 Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead
MCP6274-E/SL: MCP6274-E/ST:
Extended Temperature, SOIC package. MCP6275-E/MS: Extended Temperature, MSOP package. MCP6275-E/P: Extended Temperature, PDIP package. MCP6275T-E/SN: Tape Reel, Extended Temperature, SOIC package.
MCP6275-E/SN:
Sales Support
Data Sheets Products supported preliminary Data Sheet have errata sheet describing minor operational differences recommended workarounds. determine errata sheet exists particular device, please contact following: Your local Microchip sales office Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision silicon Data Sheet (include Literature using. Customer Notification System Register site (www.microchip.com/cn) receive most current information products.
2004 Microchip Technology Inc.
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MCP6271/2/3/4/5
NOTES:
DS21810C-page
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2004 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. your responsibility ensure that your application meets with your specifications. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2004 Microchip Technology Inc.
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DS21810C-page
WORLDWIDE SALES SERVICE
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05/28/04
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