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Design Guide LXT914 Quad Ethernet Repeater with LXT901/4/7 Motoro


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Design Guide LXT914 Quad Ethernet Repeater
with LXT901/4/7 Motorola MC68EN360
General Description
This applicati note describes method integrating LXT914 Quad Ethernet Repeater into archi tectures using MC68EN360 (QUICC) devi also includes design notes MC68EN360 LXT901/7 found Applicati Note users Level devices also QUICC interface. LXT914 advanced feature allows integration repeater function with existing QUICC/ LXT901/7 designs. QUICC/LXT90X/LXT914 device combination demonstrates Level One's commi tment supplyi highl integrated solutions meet customers' ever increasing requi rements advanced products.
QUAD XFMRs 1:SQRT2 QUAD RJ-45
LXT914 Advanced Feature
Three operating modes Selectable interface (DTE/MAU) Four integrated 10BASE-T transcei vers Integrated transmi receive filters Seven integrated vers Synchronous Asynchronous nter-repeater backplane operati Inter-repeater backplane supports glueless cascading repeater devi maximum port count Seri port interface tial port configuration Packaged both 68-pin PLCC 100-pin PQFP
Application Overview
LXT914 Flexible Quad Ethernet Repeater used increase connectivity your current future designs, including Routers, Bridges, Print Servers, etc. singl port Ethernet design upgraded multi-port repeated network simply easily using LXT914 device with advanced feature set. LXT914's advanced feature includes three modes selectable nterface (DTE/MAU). LXT914 AUISEL allows designer select interface mode operation. mode allows connection interface LXT901/4/7 with interface LXT914. This application will increase connectivity product from port ports. LXT914 advanced feature also allows growth from managed fully managed soluti
LXT914 Integrated Ethernet Repeater Block Diagram MC68EN360 SCC1 clk1-4 clk1-4
LXT914 QUAD Ethernet Repeater LXT901 LXT904 LXT907 Port (MAU Mode)
*AUISEL
13-7
Design Guide LXT914 Quad Ethernet Repeater
DESIGN REQUIREMENTS LXT90X Motorola QUICC
LXT901, LXT904 LXT907 devices each avai lable 44-pin PLCC package. There functional differences between three devices, each product features required this application. LXT907, example, uses DSQE function, allowi designer make programmable opti design. LXT901 uses UTP/ media ection. These device-specific options apply port which unused this applicati LXT904 device singl port- only port required application. Refer Level data sheet specific device your individual requirements. LXT901/4/7 device should fixed mode operati This fixed mode operation reduces number required programmable pins. mode selected operation with LXT914 Autosel disabled, disabled, PAUI (for only operation). actual connecti between LXT901/4/7 LXT914 shown Figures which detai interface opti ons: capacitive coupling isolation transformers, respectively. Capaciti coupling used like-biased devi ces. Some devices will require transformers. circuitry voltage biasing lines requires isolation when transmitting between devi ces. Either option requires 78.7 terminati resistors both sides transformer capacitive coupling shown Figures NOTE Some existing designs requi reprogramming. programmable pins should follows: AUTOSEL Low: Auto Port Select disabled Low: Link Integri Test disabled PAUI High: Port selected Low: Controller Mode ected Low: Controller Mode ected
following pins LXT901/4/7 connect MC68EN360 SCC1 signals.
Table Connections QUICC SCC1
LXT90X LXT90X Signal Name RCLK TCLK UTP(901) DSQE(907) Motorola QUICC MC68EN360 SCC1 Signal CLK1-41 CLK1-41 PI/O12 PI/O22 PI/O32 PI/O32
desi must provide separate ocks TCLK RCLK. clocks QUICC will Please refer Motorol specifi cation correct connecti desired results. These pins should programmable output pins with inputs. Check pin's state reset power compatibility Level devices.
13-8
Design Guide LXT914 Quad Ethernet Repeater
Setting QUICC Parameters
Refer Motorola MC68EN360 Quad Integrated Communi cations Controller User's Manual settings requi operate QUICC properl Here some points aware when setting QUICC's internal registers: SCC1 connection, another parallel port another remote connecti (Onl SCC1 Ethernet communicati capability.) Bypass both Phase -Locked Loop (DPLL) Manchester Encodi ng/Decodi functi Ethernet operation (This integrated into LXT901/4/7). (Time Invert) high QUICC data LXT901 LXT907 devi rising edge clock pulse. This improves data setup time Mbps speed used Ethernet. General Mode Register (GSMR). MODE bits (0-3) both Transparent ceiver (TRX) Transparent Transmitter (TTX), bits Normal Operation, Transparent Operation. signal them same mode. recommend setting: this mode QUICC does manipulate protocols data stream. Transm FIFO Length (TFL) Receive FIFO Width (RFW) bits bits (Ethernet operation) repeating (1,0,1,0,.) pattern preamble. GSMR bits 19-20 Transmit Preamble Pattern (TPP) bits.
LXT914 Configuration
following complete list settings shown Figure Some these settings optional will have select setti best product. LOC/EXT: this High Local anagement. (Use External Management meet requirement managed port statistics, protocol RMON operati with devi ce.) A/SY Select synch ronou High eliminate need external clock source. Asynchronous Synchronous modes operati determi relationshi between System Clock Clock. clock nternally generated Asynchronous mode AUISEL/LEDJM: Pull this High this applicati (This external driver used input select mode port.) LEDM1/0: these possi modes. available modes Tabl confi guration, Mode LEDJM available PLCC package. DSQE: sabl High disabl function enable function. FPS: positi High (1). SDI: this default setti internal setup register used here. (Use external EEPROM customize port setti ngs. Refer LXT914 data sheet further informati on.) SCLKIO, SENO, SENI: Leave remaining seri management pins floati TEST: this (0).
Figure Capacitive Coupling Interface
Figure Isolation Transformer Interface
78.7 78.7 78.7
Capacitors
78.7 78.7 78.7
78.7 78.7 78.7
Transformers
78.7 78.7 78.7
13-9
Design Guide LXT914 Quad Ethernet Repeater
Table Modes Available LXT914
Condition (LEDM0, LEDTP LEDAUI LEDCF
Inter-Repeater (IRB)
connects multi LXT914 devices single repeated segment. Each repeater device distributes recovered retimed data other repeaters simultaneously. This simul taneous rebroadcast lows multiple devi singl large repeated segment. IRENA, IRDAT, IRCOL, IRCFS: These four signals must each pulled through singl resistor. IRDEN: This signal controls transceivers synchronous mode operati synchronous mode required managed soluti
MODE Steady High Blink High Steady Blink Link MJLP
Packet
Packet
Collision
Table Four Port Figure
MJLP Partition Packet Packet MJLP Partiti Partition Collision Oscillator system clock) LEDs, user defi Description caps Coupling only capacitors 24.9 resistor resistors resistors 12.4 resistors resistors XFMR, coupling XFMR (quad) 1:1.41 XFMR (quad)
MODE Steady High Blink High Steady Blink Link Partiti
Collision
MODE Steady High Blink High Steady Blink Link Packet Packet
13-10
Design Guide LXT914 Quad Ethernet Repeater
Layout Requirements
Twisted-Pair Interface
four twisted-pair output circui identical. Each TPDOP/TPDON output pair 24.9 resistor series each output capacitor across output lines. These signal directly transformer creating necessary termination cable. TPDIP/TPDIN signals have resistor across differential pairs terminate signal from line. culate impedance output line interface, formula: (24.9 24.9 Table lists avai lable quad single port transformers manufacturers their part numbers. This nformation valid printing date this document. Before committing specific component, designers should review specifi cations devi used design. layout twisted-pair ports criti complex designs. differential pairs directly from device discrete termination components (located close transformers). transformer isolation voltage rating should protect circuitry from static voltages across connec-
tors cables. signals running from transformers connector should close pairs directly connector. careful cross transmit receive pairs. avoid problem receive pairs component side transmi pairs solder side. layout should have ground power planes from transformers connectors. receive transmit signal should only traces area. Place chassis ground connectors near edge PCB, away from signals, connecting connector shield within etch chassis ground.
RBIAS Pins
RBIAS resistor LXT901/4/7 devices should placed close possible with vias between devi resistor (SMT). other side shoul share with GND1 (pin 23). There should other signal running through under area. RBIAS signal sets levels output drivers device. Emissions common mode noise entering device here will seen output signals. LXT914 device with 12.4 resistor directl connected ground signals from pins should come directl device surround resistor forming partition between RBIAS resistor other signals PCB.
Table Manufacturers Magnetics List
Manufacturer Quad Transm Quad Receive Tx/Rx Pairs
Bell Fuse Fil-Mag HALO
S553-5999-02 23Z338 TD54-1006L1 TG54-1006N2
S553-5999-03 23Z339 TD01-1006L1 TG01-1006N2 TD42-2006Q TD43-2006K TG42-1406N1 TG43-1406N TG44-S010NX
(Octal) Kappa Nanopulse VALOR TP4003P 5976 EPE6009 PT4116 TP497P101 5977 EPE6010 PT4117
PT4069N1 PT4068N1 ST7011S2 ST7010S2
13-11
Design Guide LXT914 Quad Ethernet Repeater
13-12
USED REPEATER EXPANSION 8,12,16 PORTS
IRENA IRDAT IRDEN IRCFS IRCOL
DRIVERS
QUAD RJ-45 TXATXA+ RXARXA+ TXBTXB+ RXBRXB+ TX1:1.41X4 TXCTXC+ RXCRXC+
20MHz_CLOCK
SERIAL MANAGEMENT MODE SELECTION
MC68EN360
A/SYNC LOC/EXT TPDON1 TPDOP1 TPDON2 TPDOP2 TPDON3 TPDOP3 TPDON4 TPDOP4 TPDIN1 TPDIP1 TPDIN2 TPDIP2 TPDIN3 TPDIP3 TPDIN4 AUICIN TPDIP4 RBIAS 12.4K 24.9 24.9 120pf 24.9 120pf 24.9 24.9 120pf 24.9 24.9 120pf 24.9 DSQE SECTP2 SECTP3 SECTP4 TEST AUISEL TERMINATIONS AUICIN AUIDOP AUIDON AUICIP .1UF COUPLE 12.4K AUICIP RTS/LEDM0 LEDM1 LEDCF LEDTP1 LEDTP2 LEDTP3 LEDTP4 TPIN TPIP TPONA TPONB TPOPA TPOPB USED
SCLKIO SENO CS/SENI
CLK1-4 CLK1-4 RCLK TCLK UTP/DSQE RCMPT RJAB LEDR LEDC LEDT/PDN LEDL
PI/O1 PI/O2 PI/O3
STATUS OUTPUTS
PAUI VCC1 VCC2 RBIAS GND2 GND1 AUTOSEL TEST
RX1:1X4
TXDTXD+ RXDRXD+
Figure QUICC-LXT901/4/7-LXT914 Application Schematic

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