Cost VMEbus Interface Controller Family Mbyte second block transf

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Cost VMEbus Interface Controller Family Mbyte second block transf

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CY7C960 CY7C961
Cost VMEbus Interface Controller Family
Mbyte second block transfer rates VME64 transactions provided, including A64/D64, A40/MD32 transfers Auto Slot CR/CSR space standard (Rev VMEbus transactions implemented VMEbus Interrupter local required Programmable from VMEbus, serial PROM, local DRAM controller, including refresh
chip controller Local controller Flexible VMEbus address scheme User configured VMEbus response TQFP 10x10mm (CY7C960) TQFP 14x14mm (CY7C961)
capability whereby CY7C961 commanded move data master. CY7C961 packaged outline. CY7C960 contains circuitry needed control large DRAM arrays
local circuitry without inter vention local CPU. There isters read write, complex mand blocks constructed
Functional Description
CY7C960 Slave VMEbus Interface Controller provides board designer
memory. CY7C960 simply fetches configuration parameters during power reset period. CY7C960 responds After reset
with integrated, full featured VME64 interface. This device
grammed handle every transaction fined VME64 specification.
appropriately
VMEbus activity controls local cuitry transparently.
CY7C961 based upon CY7C960: additional features include Remote
CY7C960 Logic Block Diagram
STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN*
REGION[3:0]
AM[5:0]
REGION/ TABLE POWER RESET GENERATOR
CY7C964 CONTROLLER
LOCAL ADDRESS CONTROLLER
LA[7:1] LWORD
SYSRESET* DS0* DS1* DTACK* WRITE* IRQ* IACK* IACKIN* IACKOUT*
TIMING GENERATOR
CHIP SELECT OUTPUT PATTERN TABLE
CS[5:0]
CONTROL INTERFACE REFRESH CONTROLLER INTERRUPT INTERFACE DRAM CONTROLLER
DATA BYTE LANE DECODER
DATA BYTE ENABLE CONTROLLER
DBE[3:0] LACK*
LOCAL CONTROL CIRCUIT
LDEN* PREN* SWDEN*
LIRQ*
RAS* CAS*
c960
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600
December 1994 Revised March 1996
CY7C960 CY7C961
REGION[3:0] SELECTLM REGION/ TABLE POWER RESET GENERATOR
STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN* MWB* LADO LAEN321 VMECNT LOCAL ADDRESS CONTROLLER CHANNEL REGISTERS TIMING GENERATOR CHIP SELECT OUTPUT PATTERN TABLE CONTROLLER DATA BYTE ENABLE DATA BYTE CONTROLLER LANE DECODER LOCAL CONTROL CIRCUIT
c960
CY7C961 Logic Block Diagram
AM[5:0]
CY7C964 CONTROLLER
LA[7:1] LWORD
SYSRESET* DS0* DS1* DTACK* WRITE* BBSY* BERR* BGIN* BGOUT* IRQ* IACK* IACKIN* IACKOUT*
LD[7:0]
CS[5:0]
CONTROL INTERFACE
DBE[3:0] LACK* LBERR* LDEN* PREN* SWDEN*
REFRESH CONTROLLER INTERRUPT INTERFACE LOCK CONTROLLER
DRAM CONTROLLER
CY7C960 Configuration
TQFP View
CAS*/CS5 ROW/CS2
PREN* SWDEN* RAS*/CS4
COL/CS3
LIRQ*
DBE0
LACK* LIRQ* LDEN* REGION3/CS2 REGION2 WRITE* REGION1 REGION0 DENIN* IRQ* DS1* LWORD DENIN1* LAEN c960 LADI STROBE ABEN* DTACK* DS0* SYSRESET* LEDO LEDI DENO* IACKOUT* IACKIN* IACK*
DBE1 DBE2 DBE3
RAS* CAS*
CY7C960 CY7C961
CY7C961 Configuration
TQFP View
CAS*/CS5
PREN* SWDEN* RAS*/CS4
ROW/CS2
COL/CS3
DBE0
DBE1
LACK* LIRQ* LDEN* REGION3/CS2 BERR* VMECNT REGION2 WRITE* REGION1 REGION0 DENIN* c960 MWB* LADI STROBE BGIN* ABEN* DTACK* DS0* SYSRESET* LADO LEDO DENO* IACKOUT* IACKIN* BGOUT* IACK* LEDI SELECTLM* LBERR* IRQ* LAEN321 BBSY* DS1* LWORD DENIN1* LAEN
Functional Description (continued)
CY7C960 controls bridge between VMEbus local DRAM I/O. Once programmed, CY7C960 provides tivities such DRAM refresh local handshaking manner that requires additional local circuitry. VMEbus control signals connected directly CY7C960.
automatically CY7C960 response VMEbus local activity. more information desired, consult CY7C964
chapter
VIC64 Design Notes (available separately).
VMEbus transactions supported CY7C960 include D16, (incl. UAT), MD32, D64, A16, A24, A32, A40, single cycle block transfer reads writes, Read Modify Write cycles (incl. multiplexed), Address only (with with Handshake). CY7C960 functions VMEbus Inter
VMEbus address data signals connected companion address/data transceivers which controlled CY7C960. CY7C964 VMEbus Interface Logic Circuit ideal panion device: CY7C964 provides slice data address logic that been optimized VME64 transactions. addi
rupter, supports Auto Slot standard CR/CSR space. LOCK CY7C960 also handles LOCK cycles, although full support possible LOCK within constraints provided
tion providing specified drive strength timing VME64 transactions, CY7C964 contains circuitry
CY7C960 CY7C961.
pinout.
DBE2 DBE3
Full
support
needed multiplex address/data multiplexed transactions. contains counters latches needed during operations; also contains address comparators which used board's Slave Address Decoder.
local side, needed program CY7C960, manage transactions. programmable parameters
initialized through either VMEbus, serial PROM, some other local circuit. CY7C960 incorporates reliable power reset circuit, parameters self loaded device power after system reset. VMEbus used
application, four CY7C964 devices controlled single CY7C960. applications, CY7C960 controls
CY7C964 devices address latch. design CY7C960 makes unnecessary know details VMEbus transaction timing protocol.
provide parameters, VMEbus Master provides program ming information using protocol, described User's Guide, which compliant with Auto Slot protocol from VME64 specification. assist generating configuration file, Windows
complex VMEbus activities translated CY7C960 simple local cycles involving familiar control signals. Similarly, necessary understand operation companion vice, CY7C964: control sequences part generated
program available which guides user through process
based
CY7C960 CY7C961
selecting appropriate options. Contact your Sales Office further details. CY7C961 true superset CY7C960. Signal pins have been added control CY7C964 functions. Existing VMEbus input pins have been changed bidirectional mented complete master interface. data port chip lect signal (SELECTLM*) complete additions. VMEbus Slave, CY7C961 behaves every respect like CY7C960. simply more pins, master block transfer facil ity, (because addition BBSY* connection) full lock cycle support. From system perspective, CY7C961 master block transfer capability viewed channel that resides slave card, controlled over VMEbus more VMEbus masters programmed from local bus. CY7C961 master block facility provides block transfer demand" capability slave cards built around Cypress CY7C961/CY7C964 chipset. This facility allows many VMEbus masters write short series commands slave card, telling much data move, where from, where what transfer protocol while moving Blocks moved over VMEbus indivisible single cycles BLTs. protocol menu includes D16, D32, MD32, D64. A16, A24, A32, A40, address spaces specified. Burst lengths from bytes megabytes requested. Eight registers accessible from VMEbus make facility simple configure simple control. facility busy semaphore, VMEbus Interrupt completion ture with programmable Status/ID byte, built requester grant daisychain.
System Diagram Using CY7C960
LA[31:0] DRAM MEMORY DBE[3:0], LACK* RAS*, CAS*, ROW,
LIRQ* CS[2:0] SWDEN D[31:16] SWAP BUFFER LD[15:0]
DECODER
VCOMP LA[31:0]
REGION LA[7:1, LWORD]
CY7C964
CY7C964
CY7C964
CY7C964
CY7C960
A[7:1], LWORD*
D[31:24]
D[23:16]
AM[5:0]
A[31:24]
A[23:16]
A[15:8]
DATA
D[31:0]
ADDRESS
A[31:1], LWORD* INTERRUPT
IRQ* IACK* IACKIN* IACKOUT* SYSRESET*
DS1/0* DTACK WRITE*
D[15:8]
D[7:0]
c960
CY7C960 CY7C961
Related Documents
CY7C960 Family User's Guide
Ordering Information
CY7C960-AC CY7C960-NC CY7C961-NC
Ordering Code
Package Name
10x10 body Lead Plastic Thin Quad Flatpack 14x14 body Lead Plastic Thin Quad Flatpack
Package Type
Package Type
Commercial
Operating Range
Ordering Code
Package Name
A100
14x14 body Lead Plastic Thin Quad Flatpack Commercial
Operating Range
Windows trademark Microsoft Corporation.
Document 38-00250-B
Package Diagrams
Thin Quad Flatpack
CY7C960 CY7C961
Package Diagrams (continued)
Thin Quad Flatpack A100
CY7C960 CY7C961
Package Diagrams (continued)
Lead Plastic Thin Quad Flatpack
Cypress Semiconductor Corporation, 1995.
information contained herein subject change without notice.
Cypress Semiconductor Corporation assumes responsibility
circuitry other than circuitry embodied Cypress Semiconductor Corporation product. does convey imply license under patent other rights. Cypress Semicon ductor does authorize products critical components life support systems where malfunction failure product reasonably expected result significant injury user. inclusion Cypress Semiconductor products life support systems applications implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against damages.

Cost VMEbus Interface Controller Family Mbyte second block transf

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