CY82C690 Supports 3.3V Pentiumt class processors, Cyrix CPUs Dire

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CY82C690 Supports 3.3V Pentiumt class processors, Cyrix CPUs Dire

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Pentiumt hyperCachet Chipset Data Path/Integrated Cache hC-ZX Solution
CY82C690
Supports 3.3V Pentiumt class processors, Cyrix CPUs Directly interfaces with CY82C691 CY82C693 provide high performance three chip zero cache solution (hC-ZX) Provides data path between CPU, PCI, DRAM memory Direct interface with processor CY82C691 PCI/Cache/Memory Controller
3.3V operation Chip Deep FIFOs support Post Writing/Pre Reading data Supports Parity checking generation Provides Data steering size conversion Integrated microCache Pipelined BSRAM) Direct mapped associative cache mapping configurations
wraparound counter supporting Intel Burst Linear burst sequence Supports Level cache operation speed Fast Clock Data (TCO)=8.5 Synchronous self timed write cache BSRAM Direct interface with processor CY82C691 PCI/Cache/Memory Controller Packaged PQFP
System Block Diagram (hC-ZX, hC-VX, hC-DX solutions)
Address Intel Pentium Processor, Cyrix CY82C694 Expansion Cache Data
CY82C690
CY82C691
Control
CY82C692 CACHE
DRAM Address, DRAM Control
Cypress Clock CY2254ASC-2
DRAM
DRAM Data[32:63]
LOCAL
Data[0:31]
DRAM
DRAM Upper bytes
EPROM CY27C010 Flash BIOS
CY82C693/U
bytes
Standard DRAMs
(693U only)
devices
Pentium trademark Intel Corporation. hyperCache trademark Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
3901 North First Street
Jose 95134 408-943-2600 June 1996
CY82C690 Block Diagram
CY82C690
Interface Control upper bits DRAM (the bus) Data Interface Control
Data FIFO Control Logic SRAM Control Interface CY82C692 Control Interface
Upper
Upper DRAM
4Kx64 (32KB) Pipelined BSRAM
Bits
Lower Bits
Data FIFO Control Logic
CY82C692 Control Logic Data FIFOs Control Logic
Data Interface Control CY82C691 lower bits DRAM (the bus)
82C690
Lower DRAM CY82C691
SRAM Section Logic Block Diagram
ADSC ADSP BURST COUNTER ADDRESS REGISTER
CY82C690
A[13:0]
microCache Memory Array
BW[7:0] CE1A
BYTEWRITE REGISTERS ENABLE REGISTER ENABLE DELAY REGISTER
OUTPUT REGISTERS
INPUT REGISTERS Upper Bytes DQ[63:32] 82C690
Lower Bytes DQ[31:00]
Configuration
PQFP View
CY82C690
CY82C690
82C690
CY82C690 Reference Numerical Order Number)
CY82C690
Name
VSSQ CY10 CY11 CY12 CY13 CY14 CY15 DQ10 VDDQ VSSQ DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 VDDQ VSSQ DQ21 DQ22 DQ23 DQ24 DQ25 CY16 DQ26 CY17 DQ27
Name
CY18 DQ28 CY19 DQ29 CY20 DQ30 CY21 DQ31 CY22 VDDQ VSSQ CY23 CNTL4 CNTL5 CY24 CY25 CNTL6 CY26 CY27 CY28 CY29 CY30 CY31 CNTL7 CNTL8 CNTL9 CNTL10 CNTL11
Name
MD63 MD62 MD61 MD60 MD59 MD58 MD57 RESET MD56 MD55 VDDQ VSSQ MD54 DQ63 MD53 DQ62 MD52 DQ61 MD51 DQ60 MD50 DQ59 MD49 DQ58 MD48 DQ57 DQ56 DQ55 DQ54 DQ53 VDDQ VSSQ DQ52
Name
DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 VDDQ VSSQ DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 MD47 DQ36 MD46 DQ35 MD45 DQ34 MD44 DQ33 MD43 DQ32 MD42 VDDQ VSSQ MD41 MD40 ADSP ADSC MD39 MD38 MD37
Name
MD36 MD35 MD34 MD33 MD32 CNTL0 CNTL1 CNTL2 CNTL3 CE1A VDDQ
Introduction
System Overview
hyperCache
CY82C690
comprised same type BSRAM. cache sizes supported, with maximum bank.
family family three chipsets created
Reading/Post Writing
CY82C690 supports Reading/Post Writing operations through chip deep FIFOs that storage buffers. Read Post Write operations conducted Data always stored FIFO using these buffers logic,
provide flexible solutions today's designs.
Chipsets provide functions necessary implement 3.3V Pentium class processor based system with (Universal Serial Bus), (Peripheral Component
to/from chip FIFOs. closest target
Interconnect), buses.
(Industry Standard Architecture)
interface.
System designers exploit advantages
conjunction
with
chip
control
routing
buses while maintaining access large base cards marketplace. Cypress hyperCache family offers system designers several advantages. With only three chips, complete system implemented. Cache added with additional CY82C694 devices increments chipset solutions compatible provide flexible upgrade paths through board external cache modules. banks page mode DRAM further increase system designer's options. chipset also contains concurrent support, enhanced with support, integrated RTC, integrated peripheral control (Interrupts/ DMA), integrated keyboard controller. This chipset flexible enough provide system designer with many cost/performance/function options provide
CY82C690 able support concurrent transactions involving CPU, PCI, DRAM memory transactions. signals
controlling chip FIFOs generated from CY82C691 System Controller.
Parity Generation/Checking Logic
CY82C690 contains logic required parity generation checking. When enabled, CY82C690 will check/generate even byte parity DRAM data lines. done writes DRAM memory Generation will checking will
performed DRAM reads. parity error encountered, CY82C690 will assert directly CPU. Parity
generation/checking disabled throughCNTL11 (ENNMI).
Data Interface
CY82C690 interfaces data through 3.3V interface. chip logic divides this interface into
optimum solution given design.
CY82C690 Introduction
CY82C690 data path unit between DRAM hC-ZX chipset (zero cache solution).
words order accommodate size conversions concurrent transactions. Each word passes through
CY82C690 serves main functions: Provides data steering to/from three different interfaces (CPU bus, DRAM high bus, DRAM bus), Provides Level cache with integrated synchronous pipelined
deep FIFO three state buffers.
DRAM Interface
CY82C690 connects DRAM memory through
BSRAM.
With clock data valid time (TCO)=8.5
separate data interfaces, buses.
burst cycles supported frequencies MHz. CY82C690 contains several sets FIFOs that serve Reading/Post Writing buffers. These buffers controlled
connects lower bits data (and parity) both DRAM memory CY82C691 System Controller. interface contains wide, deep FIFOs order store Read/Post Write from data. FIFO controlled
signals (Control[11:0]) coming from CY82C691 System Controller. Reading/Post Writing feature enhances
Control[11:0]
CY82C691
System
Controller.
Additionally, transactions routed through CY82C691 System Controller. upper bits DRAM data transferred bus. dedicated interface that connects
system performance allowing concurrent transactions CPU, PCI, DRAM buses. CY82C690 also contains data parity generation/checking logic transactions to/from DRAM memory. 3.3V interface contains deep, wide FIFO. order This FIFO logically broken into FIFOs properly route data accommodate size
CY82C690 with upper bits DRAM data (and parity). interface contains wide deep FIFOs that used store Read/Post Write data destined upper memory. FIFO control conducted through Control[11:0].
conversions. data coming from going data must pass through FIFO.
Integrated Level Cache
CY82C690 contains integrated Level cache configured
DRAM interface divided between upper bits lower bits data. bus. upper bits (and parity)
4Kx64
synchronous
pipelined
Burst
SRAM device,
(BSRAM).
BSRAM
operates
separate
transferred
dedicated
independent from other functional blocks CY82C690. BSRAM used either direct mapped associative Level cache. Level cache expansion accomplished with either additional CY82C694s total eight cache), additional dedicated BSRAMs (synchronous pipelined). Each bank must comprised same type BSRAM. cache sizes
connection between CY82C690 upper bits DRAM memory. lower bits data (and parity) also serves data
transferred bus.
path connecting (via CY82C691) CPU. CY82C690 contains integrated Level cache configured 4Kx64 synchronous pipelined BSRAM.
BSRAM used either direct mappped associative cache. BSRAM controlled dedicated
supported. maximum banks cache allowed, with maximum bank. desired, BSRAM inside
control signals coming from CY82C691 System Controller. cache expanded with additional CY82C694s discrete must
CY82C690 also disabled. synchronous inputs BSRAM pass through registers controlled positive edge triggered single clock (CLK).
(Cypress's BSRAMs
16Kx64
pipelined
BSRAM)
additional bank
(synchronous
pipelined).
Each
synchronous inputs include addresses, data inputs, write inputs (BW[7:0], BWE), ADSC, ADSP chip enables (CE1A, CE2, CE3, CE4, CE5). data outputs pass through output registers controlled edge clock. Maximum access delay from clock rise (TCO) chip wraparound burst counter tures first address burst sequence automatically incre ments address rest burst access. CY82C690 supports secondary cache systems utilizing ther linear interleaved burst sequence. interleaved burst order supports Intel processors. linear burst quence suited processors such Cyrix burst user selectable, determined writing specified register during power Accesses initiated with either processor address strobe (ADSP) controller address strobe (ADSC). Address advancement through burst sequence trolled input. Byte write operations qualified with Byte Write Enable (BWE) Byte Write Select (BW0-7) inputs. Global Write Enable (GW) overrides byte write inputs writes data eight bytes. writes simplified with chip synchronous self timed write circuitry. Five synchronous chip selects (CS1A CS3, CS5, CS2, CS4) asynchronous output enable (OE) provide easy bank selection output three state control.
CY82C690
presented D0-D63 inputs written into corresponding address location core. CY82C690 provides byte write capability. Asserting theBWE signal together with apropriate Byte Write signal (one more BW[7:0]) will selec tively write only desired bytes. Bytes selected during byte write operation will remain unaltered. Synchronous self timed write mechanism also been provided simplify write operations. Since CY82C690 common device, Output Enable (OE) must deasserted HIGH before presenting data D0-D63 inputs. Doing will three state output drivers safety precaution, D0-D63 automatically three stated when ever write cycle detected, regardless state
Single Write Accesses Initiated ADSC
ADSC write accesses Pipelined mode initiated when lowing conditions satisfied: ADSC asserted LOW, ADSP deasserted HIGH, CS1A, CS5, CS4, asserted active, appropriate write inputs (GW, BWE, BW0-BW7) asserted active conduct write desired byte(s). ADSC triggered write accesses require single clock cycle complete. address presented A0-A13 loaded into address register address advancement logic while being livered core. input ignored during this cycle. data presented D0-D63 written into corresponding address location core. byte write conducted, only selected bytes written. Bytes selected during byte write operation will remain unaltered. Synchro nous self timed write mechanism also been provided simpli write operations. Since CY82C690 common device, Output Enable (OE) must deasserted HIGH before presenting data D0-D63 inputs. Doing will three state output drivers. safety precaution, D0-D63 automatically three stated when ever write cycle detected, regardless state
Single Read Accesses
This access initiated when following conditions satisfied clock rise: ADSP ADSC asserted LOW, CS1A, CS3, CS5, CS4, asserted active, HIGH, either HIGH BW0-BW7 HIGH. dress presented address inputs (A0-A13) stored into address advancement logic Address Register while being presented memory core. corresponding data allowed propagate input Output Registers SRAM tion. rising edge next clock data driven onto data D[63:00]. requested data will available after clock rise. When asynchronous Output Enable (OE) asserted LOW, data outputs from SRAM block controlled Enable Enable Delay isters. During first cycle initial read operation outputs remain three state condition, regardless state Output Enable (OE). This feature required order support pipelining without creating contention data when multiple banks cache used. Consecutive single read cycles supported.
Burst Sequences
CY82C690 provides wraparound counter, that implement either interleaved linear burst quence. interleaved burst sequence designed specifically support Intel Pentium applications. linear burst sequence designed support processors that follow linear burst sequence, such Cyrix burst order determined during boot writing specific configuration register. Asserting clock rise will automatically increment burst counter next address burst sequence. Both read write burst operations supported.
Single Write Accesses Initiated ADSP
ADSP triggered accesses initiated when both following conditions satisfied clock rise: ADSP asserted LOW, CS1A, CS3, CS5, CS4, asserted active. address presented A0-A13 loaded into address register address advancement logic while being delivered core. write signals (BW0-BW7, BWE) inputs ignored during this first cycle. ADSP triggered write accesses require clock cycles plete. write inputs (either with more BW[7:0]) asserted second clock rise, data
Intel Burst Sequence Linear Burst Sequence First Address Second Address Ax+1, Ax+1, Third Address Ax+1, Fourth Address Ax+1, Ax+1, First Address Second Address Ax+1, Third Address Ax+1,
CY82C690
Fourth Address Ax+1,
Cycle Descriptions
Next Cycle Unselected Unselected Unselected Unselected Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write Add. Used none none none none none none none none none External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current CS1A ADSP ADSC Writes Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write
X=Don't Care, 1=Logic HIGH, 0=Logic Note: Writes defined BWE, BW[7:0], Write Cycle Descrip tion table.
Write Cycle Descriptions
Function[2]
Read Read Write Byte Write Byte DQ[7:0] Write Byte DQ[15:8] Write Byte DQ[23:16] Write Byte DQ[31:24] Write Byte DQ[39:32] Write Byte DQ[47:40] Write Byte DQ[55:48] Write Byte DQ[63:56] Write Byte Write Byte Write Byte Write Byte Write Byte Write Byte Write Byte Write Byte Write Byte Write Byte
CY82C690
remainder follows same pattern above.
X=Don't Care, 1=Logic HIGH, 0=Logic
Notes:
SRAM always starts Read cycle when ADSP asserted, regard less state BWE, BW[7:0].
Descriptions
Name
RESET
CY82C690
Number
Description
This RESET input signal from CY82C693. known state invalidates write buffer entries. puts CY82C690 into
CPUCLK D[63:00]
107, 109. 111, 113, 115, 117, 119-123, 126-135, 138-142, 144, 146, 148, 150, 152, 154, 38-34, 31-22, 19-15,
clock input.
This runs synchronous CPU's external clock. These 3.3V signals.
data interface.
CY[31:00]
66,64, 207, 206, 202, 200, 198, 196, 194, 192, 190,
interfaces lower DRAM data bits.
also data path
pass data to/from CY82C691 routing bus.
MD[63:31]
101, 103, 106, 108, 110, 112, 114, 116, 118, 145, 147, 149, 151, 153, 155, 158, 160, 164, 166, 168, 170, 172, 174, 176,
interfaces upper DRAM data bits.
MP[7:0]
102, 143, 162,
Memory parity bits. DRAM data lines.
CY82C690 generates/checks even byte parity
maskable interrupt line CPU. error been detected.
Used inform that parity
A[13:0]
Address inputs cache BSRAM, sampled rising edge clock.
Global Write Enable input.
Used conduct global writes.
When asserted,
overrides byte writes, global write occurs. When used with CY82C691 CY82C693, this should tied HIGH through Byte Write Enable input. operations. BW[7:0]
resistor.
Used conjunction with BW[7:0]
conduct byte write
qualified with BWE.
When asserted, overrides
byte writes, global write occurs.
When used with CY82C691
CY82C693, this should tied through BW[7:0] 165, 167, 173, 175, 191, 189, 187, CE1A Chip enable ADSP mask.
resistor.
Byte write inputs cache BSRAM, synchronous, sampled rising edge clock.
Descriptions
Name
CY82C690
(continued)
Number
CE2, CE3, CE4, ADSC ADSP CONTROL [11:00]
VDDQ VSSQ
Supply Supply
Expansion decode inputs cache expansion. Used establish decode expansion position each CY82C690. Asynchronous Output Enable. Active LOW, used conjunction with Control[11:00] control three state buffers onto bus. Advance input signal BSRAM section only, active LOW, sampled rising edge clock. When detected active will cause chip burst counter increment next address burst sequence. This signal ignored ADSP ADSC asserted. Address input strobe from controller, active LOW, sampled rising edge clock. When asserted, address inputs captured address register. also loaded into burst counter. ADSC ignored when asserted with ADSP. Address input strobe from processor, active LOW, sampled rising edge clock. When asserted, address inputs captured address register. also loaded into burst counter. 80-78, Control inputs. These inter chip communication signals between 186, CY82C691 CY82C690. These signals used control FIFOs, logic, 184, 182, three stating, data steering inside CY82C690. CNTL[3:0] pass state information from 82C691 82C692. CNTL4 Primary Latch signal (PRILAT) CNTL5 Secondary Latch signal (SECLAT) CNTL6 Advance FIFO (ADVCPUF) CNTL7 Advance FIFO (ADVMDF) CNTL8 Advance FIFO (ADVCYF) CNTL9 SELDHDL CNTL10 SELCYDL CNTL11 Enable (ENNMI) 104, 3.3V power supply I/Os CY82C690. 124, 136, 156, 169, power supply core CY82C690. Ground I/Os CY82C690. 105, 125, 137, 171, Ground core CY82C690. Current into Outputs (LOW) Static Discharge Voltage >2001V (per 883, Method 3015) Latch Current >200
Operating Range
Ambient Range
203, 199, 205,
Description
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65_C +150_C Ambient Temperature with Power Applied -55_C +125_C Supply Voltage Relative -0.5V +7.0V Voltage Applied Outputs High State[3] -0.5V VDDQ 0.5V Input Voltage[3] -0.5V VDDQ 0.5V
Maximum Ratings
Com'l
Temperature
+70_C
3.3V +/-0.3V
VDDQ
Electrical Characteristics Over Operating Range
Parameter Description Test Conditions Min.
CY82C690
Max.
Unit
ISB1 ISB2
Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage[3] Input Load Current Output Leakage Current Output Short Circuit Current[5] Operating Supply Current Automatic Power Down Current-TTL Inputs Automatic Power Down Current-CMOS Inputs
Min., IOH=-4.0 Min., IOL=8.0
VDDQ
-0.3
Output
)0.3V
Disabled Com'l
VDD=Max., VOUT=GND VDD=Max., Iout=0mA, Max., Iout 0mA, fMAX =1/tCYC Max. VDD, VIH, VIL, fMAX[7]
-300
Max. 0.3V, -0.3V 0.3V, f=0[6,7]
Com'l Com'l
Capacitance[8]
Parameter Description Test Conditions Max. Unit
CIN: Addresses CIN: Other Inputs COUT
Notes:
Input Capacitance Output Capacitance
25_C, MHz, 3.3V
Minimum voltage equals -2.0V pulse durations less than instant case temperature. more than output should shorted time. Duration short circuit should exceed seconds. Inputs disabled, clock allowed speed.
signifies chip selects active during clock rise. Tested initially after design process changes that affect these parameters. Resistor values VDDQ=3.3V R1=317 R2=348
Test Loads Waveforms
OUTPUT
1.5V
VDDQ OUTPUT INCLUDING SCOPE
(b)[9]
82C690
3.0V
INPUT PULSES
82C690
Switching Characteristics
Parameter
tCYC tDOH tADS tADH tWES tWEH tADVS tADVH tCSS tCSH tCHZ tCLZ tEOHZ tEOLZ tEOV Clock Cycle Time Clock HIGH Clock Address Before Rise Address Hold After Rise Data Output Valid After Rise Data Output Hold After Rise ADSP ADSC Before Rise ADSP ADSC Hold After Rise BWE, BW[7:0] Before Rise BWE, BW[7:0] Hold After Rise Before Rise Hold After Rise Data Input Before Rise Data Input Hold After Rise Chip Select Chip Select Hold After Rise Clock High Z[11] Clock High Z[11] HIGH Output High HIGH Output Output Valid
[11,12]
CY82C690
Min.
Over Operating Range[10,11]
Description
Min.
Max.
Max.
Unit
10.0
[111]
[11,12]
Notes:
Unless otherwise noted, test conditions assume signal transition time less, timing reference levels 1.5V input pulse levels 3.0V output loading specified IOL/IOH load capaci tance. Shown test loads. tCHZ, tCLZ, tOEV tEOLZ, tEOHZ specified with load capaci tance part Test Loads. Transition measured from steady state voltage. given voltage temperature, tEOHZ min. less than tEOV min.
tEOHZ
tADS tCSS tCSH tADH tCYC tWES tADVS tWEH tADVH tADS tADH tDOE
deasserted suspends burst
signifies that chip selects (CS1, CS3, CS5, CS2, CS4) asserted active.
Note:
Switching Waveforms
Read Timing
BW0,
BWE,
DATA
ADSC
ADSP
ADD.
[13]
Don't Care
Undefined
tCLZ
Single Read
tEOLZ
tDOH
Burst Read
initial state
Burst counter wraps
Device Deselected
Outputs three state
immediately upon
being deselected
CY82C690
82C690
tADS tCSS Single tCSH tADH tEOHZ tCYC tWES tADVS tADS tWEH tADH tADVH Burst Write
suspends burst deasserted
Write Timing
Switching Waveforms (continued)
BWE,
Data
Data
ADSC
ADSP
ADD.
[13]
Write
initiated ADSP
initiated ADSC Burst Write
CY82C690
82C690
tEOHZ tADVS tADVH tEOLZ tEOV read immediately following write Write data (3a) forwarded outputs
tCSS tADS tCSH tCYC tADH tADS tADH tWES tWEH
Switching Waveforms (continued)
Read/Write Timing
BWE,
ADSC
CS[13]
ADSP
Data
ADD.
Data
deselected
SRAM
during first clock
Burst access
SRAM selected
data driven
CY82C690
82C690
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
CY82C690
CY82C690-XXX CY82C690-XXX
Lead Plastic Quad Flat Pack Lead Plastic Quad Flat Pack
Commercial Commercial
Document 38-00525
Cypress Semiconductor Corporation, 1995. information contained herein subject change without notice.
Cypress Semiconductor Corporation assumes responsibility
circuitry other than circuitry embodied Cypress Semiconductor Corporation product. does convey imply license under patent other rights. Cypress Semicon ductor does authorize products critical components life support systems where malfunction failure product reasonably expected result significant injury user. inclusion Cypress Semiconductor products life support systems applications implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against damages.

CY82C690 Supports 3.3V Pentiumt class processors, Cyrix CPUs Dire

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