Interfacing Atmel LV/BV EPROMs Mixed 3-Volt/5-Volt Data Interfaci

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Interfacing Atmel LV/BV EPROMs Mixed 3-Volt/5-Volt Data Interfaci

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CMOS EPROM
Interfacing Atmel LV/BV EPROMs Mixed 3-Volt/5-Volt Data
Interfacing Atmel Corporation's voltage (LV/BV) EPROMs common data with standard 5-volt devices achieved with relative ease simple guidelines followed. controlling data voltages currents, problems associated with latchup, electromigration battery damage eliminated. This application note describes each problem, along with recommended solutions, analyzes associated tradeoffs. Electromigration Metal interconnects semiconductors carefully sized ensure they wide enough safely carry amount current required design. interconnects physically open when these limits exceeded long time. Venting When battery overheats result dissipating excessive power) battery case open, allowing contents battery "vented" leaked outside world. This both messy potentially dangerous. Understanding issues related interfacing Atmel LV/BV EPROMs with standard 5-volt devices requires understanding EPROM output. output basically CMOS inverter constructed with p-channel pullup n-channel pull-down transistors (see Figure source p-channel n-well connected VCC. source nchannel substrate con-
CMOS EPROM Application Note
Background
Definition Terms: Latchup destructive phenomenon associated with CMOS-based semiconductors. Parasitic SCRs (silicon-controlled rectifiers p-n-p-n devices) exist inputs outputs. Once activated, conduct high current. current only turned disconnecting power supply.
Interfacing Atmel LV/BV EPROMs Mixed 3-Volt/5-Volt Data
Figure Atmel LV/BV CMOS EPROM Output Buffer
(continued)
0559A
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Background (Continued)
nected ground. important note that drain p-channel device n-well forms parasitic diode. parasitic diode between output LV/BV part supply, with diode cathode connected anode connected output node. Atmel LV/BV EPROM operated from 3-volt supply output node rises volts, parasitic junction forward biased volts will conduct current. This diode current will flow even though LV/BV EPROM output supposed tri-stated (high-Z) control signals. room temperature characteristic diode shown Figure y-axis graph, designated "IBUS," represents current flowing from into Atmel LV/BV EPROM output. x-axis, designated "VBUS," data voltage when supply level LV/BV EPROM exactly volts. example, voltage data volts, corresponding diode current into LV/BV part's output approximately VBUS increased volts, corresponding diode current just output increases would destructive over time. important note that LV/BV EPROM data sheets refer output voltage. data sheet section under "Absolute Maximum Ratings" specifically states that "Maximum output voltage 0.75VDC which exceeded certain precautions observed." What does this mean? means that, because effects demonstrated parasitic diode, voltages output pins excess 0.75 volts cause large currents flow into EPROM outputs short power supplies together (see Figure Each Atmel EPROM output designed withstand IBUS current less than without exposure electromigration, over without latchup. Since current capability latchup much larger than Figure Atmel LV/BV EPROM IBUS versus VBUS
amount current required induce electromigration, clear that electromigration requirement will dictate maximum IBUS current. balance this application note focuses ensuring system design that magnitude IBUS current into EPROM less than effects exceeding normal output voltage LV/BV supply (over-volting) will discussed detail here. Those characteristics should obtained from battery voltage regulator manufacturers.
Results
Clearly, most attractive design option select 5-volt driver devices which have strong output drive current (IOH) capability. example this type device 8096 microcontroller. characteristic shown Figure only concerned about much IBUS) 8096 supply into LV/BV EPROM above VBUS) volts. maximum current 8096 supply when above volts less than allowed safely enter LV/BV EPROM. Therefore, electromigration concern this case. However, allowing both power supplies couple across parasitic diode LV/BV EPROM still speed discharge 5-volt battery cause 3-volt battery overheat vent. Contrast 8096 example with output characteristics high-current output drive 74HC00 CMOS logic gate (Figure Note amount current available above 3-volt more than triple maximum safe IBUS current prevent electromigration. What actual IBUS will occur when such 74HC00 part (connected 5-volt supply) driving Atmel LV/BV EPROM (connected 3-volt supply)? answer obtained using graphical technique called load line analysis.
(continued)
Figure Parasitic Diode LV/BV Output Shorts 3-Volt 5-Volt Supplies
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CMOS EPROM
CMOS EPROM
Results (Continued)
With load line analysis, find maximum IBUS VBUS values situation. example, continue analysis 74HC00 part what actual IBUS current will load line created simply superimposing Atmel LV/BV EPROM IBUS versus VBUS curve (Figure with 74HC00 versus curve (Figure Figure resulting load line. place curves intersect called operating point gives IBUS value about data will then VBUS voltage about volts. This analysis confirms suspicion that using 74HC00 will safe. Recall that want IBUS value below prevent reliability damage LV/BV EPROM. Figure versus 8096 type curves used this load line analysis easily obtained conditions part. should beware curves obtained worst case conditions that system will encounter. Most data sheet specifications minimum values sometimes grossly understate real current drive capability part. When last time encountered CMOS part with only volts VOH? Such specification holdover from days when NMOS design considered fast Many data sheets provide output drive curves only typical conditions (i.e., temperature 25°C). Most data sheets also provide data only minimum output drive since most (continued) Figure versus 74HC00
Figure 74HC00 Load Line LV/BV EPROM
Figure LV/BV IBUS versus VBUS versus Temperature
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Results (Continued)
customers worried part enough current drive heavily loaded line. However, this mixed power supply design analysis need maximum output drive current 5-volt driven part. conditions that maximum output current would occur lowest temperature highest VCC, with only output driving. last condition parasitic resistance chip's package metal. That resistance will cause voltage drop inside chip that will decrease output current drive. parts with more than output, highest current will occur when internal voltage drop minimum when only output driving. variation with number outputs driving, VCC, temperature will exceed variations processing most chips today. have measure characteristics yourself data need. Atmel LV/BV EPROM IBUS versus VBUS characteristics will also need measured conditions giving highest current load line operating point. That current will depend strongly used LV/BV parts. higher LV/BV VCC, higher voltage before forward-biasing parasitic diode LV/BV part. load line analysis, LV/BV EPROM IBUS versus VBUS curve measured shifted right difference between LV/BV supply voltage used 3-volts. Increasing LV/BV will reduce IBUS quickly since 5-volt part decreases rapidly operating point moves right. worst case LV/BV IBUS versus VBUS curve will obtained highest temperature, lowest VCC, single output high. Figure shows LV/BV EPROM IBUS function VBUS range temperatures from -55°C 85°C. some applications, there requirements high output current 5-volt device alternate part available with limited IOH. following techniques useful that case. technique clamp with respect ground. Clamp that parasitic junction LV/BV part cannot forward biased. 3-volt zener diode with grounded anode cathode connected data provide protection mixed 3-volt/5-volt system (Figure 1N4370A- 1N746A-series zener diodes could used. trade-off power dissipated zeners. 3-volt zener shunting current will consume power. eight outputs, this could high which significant amount power waste battery environment. This will speed discharge 5-volt battery, does very good protecting 3-volt supply from over-volting possibly venting 3-volt battery). Another technique small series resistor each LV/BV part's outputs (Figure resistor will limit IBUS current. Figure uses 74HC00 example again show load line plot from Figure used quickly calculate value series resistance needed. want move IBUS operating point from
(continued)
Figure Zener Clamp Volts Figure Series Output Resistor Reduces IBUS
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CMOS EPROM
CMOS EPROM
Results (Continued)
original down circuit consists original 74HC00 pull-up circuit, represented original load line, series resistor. current resistor pull-up will same since they series should recommended safe level. Figure will points called which where LV/BV EPROM 74HC00 pull-up load lines intersect IBUS current level. difference between will voltage drop across series resistor when current flowing. series resistance Rseries then calculated formula: Rseries Idesired (4.55 3.85) ohms power dissipated each resistor would given Pseries Idesired Rseries ohms eight outputs, series resistor method only drains from 5-volt supply, which much less power than that wasted zener circuit. Notice that 3-volt supply will still over-volted 0.85 volts. still need determine that over-volting will cause excessive battery heating possible venting problem. resistor's effect signal speed will probably detrimental Figure Calculating Rseries 74HC since ohms needed this example just slightly higher than value used series transmission line termination. necessary place series resistors between high output drive part common data bus. That resistors only circuit when high output part driving bus, lower drive current parts will current-limited. Also, remember this example done room temperature 5-volt supply 74HC00. higher temperature, 74HC00 will have less current drive, parasitic LV/BV EPROM diode will start forward bias lower VBUS value. need several load line models before finding design that covers worst case temperature power supply conditions particular system.
Conclusion
Interfacing Atmel LV/BV EPROMs common data with standard 5-volt devices achieved output drives 5-volt powered parts controlled through careful device selection adding external components. problems avoid are: failure LV/BV part electromigration, battery venting LV/BV supply. Following these guidelines will allow design mixed power supply systems which exhibit sound component system reliability.
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Interfacing Atmel LV/BV EPROMs Mixed 3-Volt/5-Volt Data Interfaci

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