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Pentium® Processor Specification Update
Order Number: 243337-025
Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update.
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Specification Update should publicly available following last shipment date period time equal specific product's warranty period. Hardcopy Specification Updates will available year following Life (EOL). access will available three years following EOL. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com Copyright Intel Corporation 1999. Third-party brands names property their respective owners.
CONTENTS
REVISION HISTORY. PREFACE .viii Specification Update Pentium® Processors. GENERAL INFORMATION. ERRATA. DOCUMENTATION CHANGES SPECIFICATION CLARIFICATIONS SPECIFICATION CHANGES
PENTIUM® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date Revision 1997 June 1997 Version -001 -002 Description This document first Specification Update Pentium® processor. Added Erratum Update Erratum status Summary Table Changes. Added Documentation Change Table Documentation Change Added 300-MHz Pentium processor information. Added Erratum Added Specification Change Table Specification Changes Added Erratum Added Document Change Spec Changes Updated Erratum Added Errata Added Document Change Spec Clarification Added stepping information. Updated Spec Change Updated Errata S-spec table. Updated Erratum Added Specification Clarification Updated added notes S-spec table. Updated package information table. Updated Errata Added Errata Added notes Pentium processor markings. Updated Erratum Added Erratum Added Documentation Change Added Specification Change Updated S-spec table. Added stepping information. Added Errata Added processor markings. Corrected Errata steppings affected. Corrected typos summary table Errata Added Erratum Added Documentation Change Added boxed processor markings. Updated Documentation Changes section, Specification Clarifications section, Specification Changes section. Corrected Erratum Added Errata Added Documentation Changes Added Specification Clarification Added Specification Changes Added Mobile Pentium processor markings Pentium Mobile Modules markings. Updated Documentation Changes section, Specification Clarifications section, Specification Changes section. Updated S-spec table. Added steppings Summary Table Changes. Corrected Erratum Added Errata Added Documentation Change Updated Specification Change Added Specification Change Updated S-spec table. Updated Errata Added Errata through Corrected Documentation Change Updated Specification Change
July 1997 August 1997 September 1997
-003 -004 -005
October 1997 November 1997 December 1997 January 1998
-006 -007 -008 -009
January 1998 (Special Edition) February 1998
-010 -011
March 1998
-012
April 1998
-013
1998
-014
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision June 1998
Version -015
Description Updated S-spec Table. Updated Summary Table Changes. Updated Erratum Added Errata Added Documentation Changes through Added Specification Clarifications though Updated Specification Change Added Specification Change Added Pentium Processor Boxed Pentium Processor Line Markings. Updated Preface, Documentation Changes section, Specification Clarifications section, Specification Changes section. Updated S-spec Table. Updated Summary Table Changes. Added Errata Added Documentation Changes through Added Specification Clarifications through Added Specification Change Moved references Mobile Pentium processor Mobile Pentium® Processor Specification Update. Updated Sspec Table. Updated Summary Table Changes. Updated Errata Added Errata through Updated Specification Clarification Added Pentium OverDrive® processor markings. Updated S-spec table. Updated Errata Added Errata through Added Specification Changes Implemented numbering nomenclature. Updated S-spec table. Updated Errata A48. Added Errata A62, A64. Added Specification Change Added Specification Clarifications A17. Updated Specification Change Documentation Change A11, Erratum A44, Specification Change Pentium Processor Identification Information table. Added Erratum Documentation Change A18. Updated Specification Change Pentium Processor Identification Information table. Added Erratum A66. Updated status Errata through A29, A31, through A39, A42, A48, A54, A57, A60. Changed affected steppings Erratum A32. Updated Specification Change Pentium Processor Identification Information table. Added Errata through A69, Documentation Change through A21. Updated Processor Identification Information table. Added Erratum A70. Added Specification Change updated Pentium Processor Identification Information table. Added S-Spec definition. Removed Specification Changes, Specification Clarifications, Document Changes that have been incorporated into appropriate documentation. Renumbered remaining items.
July 1998
-016
August 1998
-017
September 1998
-018
October 1998
-019
November 1998
-020
December 1998
-021
January 1999
-022
February 1999 March 1999
-023 -024
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision April 1999
Version -025
Description Added Documentation Change updated Pentium Processor Identification Information table. Moved revised Mixed Steppings statement General Information section renumbered remaining items.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
PREFACE
This document update specifications contained Pentium® Processor Developer's Manual (Order Number 243341), Pentium® Processor MHz, MHz, MHz, datasheet (Order Number 243335), Pentium® Processor MHz, MHz, datasheet (Order Number 243657), Intel Architecture Software Developer's Manual Volumes (Order Numbers 243190, 243191, 243192, respectively). intended hardware system manufacturers software developers applications, operating systems, tools. contains Specification Changes, S-Specs, Errata, Specification Clarifications, Documentation Changes.
Nomenclature
S-Spec Number five digit code used identify products. Products differentiated their unique characteristics, e.g., core speed, cache size, package type, etc., described processor identification information table. Care should taken read notes associated with each S-Spec number. Specification Changes modifications current published specifications Pentium® processor. These changes will incorporated next release specifications. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications. Errata design defects errors. Errata cause Pentium processor's behavior deviate from published specifications. Hardware software designed used with given processor must assume that errata documented that processor present devices unless otherwise noted.
Identification Information
Pentium processor identified following values: Family1 0110 233-, 266-, 300, -MHz Model 0011
266-, 300-, 333-, 350-, 400-, 450- Model 0101
NOTES: Family corresponds bits [11:8] register after RESET, bits [11:8] register after CPUID instruction executed with register, generation field Device register accessible through Boundary Scan. Model corresponds bits [7:4] register after RESET, bits [7:4] register after CPUID instruction executed with register, model field Device register accessible through Boundary Scan. This Pentium® OverDrive® processor. Please note that although this processor CPUID 163xh, uses Pentium processor CPUID 065xh processor core.
Pentium processor's second level (L2) cache size determined following register contents: 512-Kbyte Unified Cache
NOTE: Pentium® processor, unified cache size corresponds value bits [3:0] register after CPUID instruction executed with register. Other Intel microprocessor models families move this information other positions otherwise reformat result returned this instruction; generic code should parse resulting token stream according definition CPUID instruction.
viii
Specification Update Pentium® Processors
PENTIUM® PROCESSOR SPECIFICATION UPDATE
GENERAL INFORMATION
Pentium® Processor Boxed Pentium® Processor Line Markings
Dynamic Mark Area
Speed Cache Voltage Identifier
Matrix Mark
S-Spec Serial
350/512E/100/2.2V SL28R FFFFFFFF-NNNN ©'97 PHILIPPINES
Country Assy
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Pentium® Processor Markings
Dynamic Mark Area
Matrix Mark
Intel UCC# Order Code (Product speed) Number Number (date, factory)
80522PXZZZLLL SYYYY FFFFFFFF-XXXX Country Origin
80523PXZZZLLL SYYYY FFFFFFFF-XXXX Country Origin
pentium
with MMXtechnology
Dynamic Mark Area
pentium
Hologram Location
NOTES: Speed (MHz). SYYYY S-spec Number. Level Cache Size Kilobytes). FFFFFFFF (Test Traceability XXXX Serialization Code.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Boxed Pentium® Processor Markings
Dynamic Mark Area
Matrix Mark C-Step Production Units B80522PZZZLLLE SYYYY FFFFFFFF-XXXX Country Origin
Intel UCC# Order Code (Product speed) Number Number (date, factory)
dA-Step Production Units B80523PZZZLLLE SYYYY 2.0V FFFFFFFF-XXXX Country Origin
pentium
with MMXtechnology
Dynamic Mark Area
pentium
Hologram Location
NOTES: Speed (MHz). Level Cache Size Kilobytes). Support Level Cache SYYYY S-spec Number. FFFFFFFF (Test Traceability XXXX Serialization Code.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Pentium® OverDrive® Processor Line Markings
Bottom View Pentium® OverDrive® Processor
NOTES: Label Markings FFFFFFF (Test Traceability DDDDDD Altered Assembly Number. Bottom Cover Markings PODP66X333 Product Code. SYYYY S-spec Number. VW.W Version Number.
NOTES: Attached heat sink user removable. power provided through external power connector, through processor socket.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications, Documentation Changes which apply Pentium processors. Intel intends some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations: CODES USED SUMMARY TABLE Doc: Fix: Fixed: NoFix: mark) (blank box): SUB: Specification Change, Erratum, Specification Clarification, Documentation Change applies given processor stepping. Intel intends update appropriate documentation future revision. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum. This item fixed does apply given stepping. APIC related erratum. This column refers errata Pentium® processor substrate.
Shaded: This item either modified from previous version document. Some Intel's Specification Updates will undergoing numbering methodology change reduce confusion when referring errata which affect specific product. Each Specification Update item will prefixed with capital letter distinguish product refers below details letters which will used current Intel microprocessor Specification Updates: Pentium® processor Mobile Pentium® processor Intel® Celeronprocessor Pentium® Xeonprocessor Pentium® processor Pentium® Xeonprocessor Intel® Mobile Celeronprocessor Specification Updates Pentium® processor, Pentium® processor, other Intel products will implementing such convention this time.
PENTIUM® PROCESSOR SPECIFICATION UPDATE Pentium® Processor Identification Information
Core Stepping Speed (MHz) Core/Bus 233/66 266/66 233/66 266/66 233/66 266/66 300/66 300/66 300/66 266/66 233/66 266/66 233/66 233/66 266/66 300/66 333/66 333/66 266/66 300/66 333/66 333/66 333/66 350/100 350/100 400/100 350/100 400/100 Size (Kbytes) TagRAM/ Stepping T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6/B0 T6P/A3 T6P/A3 T6P/A3 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 ECC/ Non-ECC non-ECC non-ECC non-ECC non-EC non-ECC non-ECC non-ECC non-ECC Processor Substrate Revision Package Revision SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00
S-Spec SL264 SL265 SL268 SL269 SL28K SL28L SL28R SL2MZ SL2HA SL2HC SL2HD SL2HE SL2HF SL2QA SL2QB SL2QC SL2KA SL2QF SL2K9 SL35V SL2QH SL2S5 SL2ZP SL2ZQ SL2S6 SL2S7 SL2SF SL2SH
CPUID 0633h 0633h 0633h 0633h 0633h 0633h 0633h 0633h 0634h 0634h 0634h 0634h 0634h 0634h 0634h 0634h 0650h 0650h 0650h 0651h 0651h 0651h 0651h 0651h 0651h 0651h 0651h 0651h
Notes
PENTIUM® PROCESSOR SPECIFICATION UPDATE Pentium® Processor Identification Information (Continued)
Core Stepping TdB0 Speed (MHz) Core/Bus 300/66 266/66 300/66 350/100 400/100 400/100 450/100 450/100 333/66 266/66 300/66 333/66 350/100 350/100 400/100 400/100 450/100 350/100 400/100 450/100 350/100 350/100 400/100 400/100 Size (Kbytes) TagRAM/ Stepping T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 C6C/A3 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/0 T6P-e/0 T6Pe/A0 ECC/ Non-ECC Processor Substrate Revision Package Revision SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC2 OLGA SECC 3.00 SECC2 OLGA SECC 2.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC2 PLGA SECC2 OLGA SECC2 OLGA SECC2 PLGA SECC2 OLGA SECC2 PLGA SECC2 PLGA
S-Spec SL2VY SL33D SL2YK SL2WZ SL2YM SL37G SL2WB SL37H SL2KE SL2W7 SL2W8 SL2TV SL2U3 SL2U4 SL2U5 SL2U6 SL2U7 SL356 SL357 SL358 SL37F SL3FN SL3EE SL3F9
CPUID 0651h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 1632h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h 0652h
Notes
PENTIUM® PROCESSOR SPECIFICATION UPDATE Pentium® Processor Identification Information (Continued)
Core Stepping Speed (MHz) Core/Bus 350/100 400/100 350/100 400/100 400/100 Size (Kbytes) TagRAM/ Stepping T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 T6P-e/A0 ECC/ Non-ECC Processor Substrate Revision Package Revision SECC 3.00 SECC 3.00 SECC 3.00 SECC 3.00 SECC2 OLGA
S-Spec SL38M SL38N SL36U SL38Z SL3D5
CPUID 0653h 0653h 0653h 0653h 0653h
Notes
NOTES: VCC_CORE specified +100/-70 Pentium® processors. TPLATE specified these Pentium processors with S.E.C. cartridge packages except s-specs SL28R SL2HA, SL2MZ, SL2QC which have TPLATE specification This boxed Pentium processor with attached heatsink. VCCCORE specified +100/-70 these Pentium processors. TPLATE specified these Pentium processors. TPLATE specified with (extended thermal plate) these Pentium processors. Cacheable address space supports these Pentium processors. These processors will shut down automatically THERMTRIP#. These boxed processors have packaging which incorrectly indicates support cache. These processors affected Erratum A57. TPLATE specified with (extended thermal plate) these Pentium processors. This boxed Pentium OverDrive® processor with attached heatsink. This TagRAM notation equivalent part number 82459AB. This TagRAM notation equivalent part number 82459AC. This TagRAM notation equivalent part number 82459AD. TCASE (MAX) specified these Pentium processors. These processors affected Erratum A67. TJUNCTION (MAX) specified these Pentium processors. These processors require dual reset BIOS. These parts will only operate specified core frequency ratio which they were manufactured tested. necessary configure core frequency ratios using A20M#, IGNEE#, LINT[1]/NMI LINT[0]/INTR pins during RESET. These parts require inputs from A20M#, IGNEE#, LINT[1]/NMI LINT[0]/INTR pins during RESET correct core frequency ratio. These parts require inputs from A20M#, IGNEE#, LINT[1]/NMI LINT[0]/INTR pins during RESET correct core frequency ratio.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
TdB0
Plans NoFix
ERRATA Data Operand Pointer incorrectly calculated after access which wraps 64-Kbyte boundary 16-bit code Differences exist debug exception reporting FLUSH# servicing delayed while waiting STARTUP_IPI 2-way systems Code fetch matching disabled debug register cause debug exception Double error read result BINIT# inexact-result exception flag Bfor will contain incorrect FROM restart fail after simultaneous Branch traps function BTMs also enabled Checker BIST failure mode signaled BINIT# assertion causes FRCERR assertion mode Machine check exception handler always execute successfully parity error gives MCACOD.LL LBER corrupted after some events BTMs corrupted during simultaneous cache line replacement System hang internal protocol violation Livelock condition cause system hang Mispredicted branch cause incorrect word MMXtechnology instructions Thermal sensor/THERMTRIP# does work Spurious machine check exception data parity error
NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix Fixed Fixed
Fixed
Fixed Fixed
PENTIUM® PROCESSOR SPECIFICATION UPDATE
TdB0
Plans Fixed Fixed
ERRATA Loss inclusion cause machine check exception Possible system hang when paging disabled reenabled from uncached memory performance counters miscount L2_RQSTS Erroneous signaling user mode protection violation Invalid operation signaled FIST instruction some range operands FLUSH# assertion disables machine check exception reporting EFLAGS incorrect after multiprocessor shootdown Delayed line invalidation issue during 2-way data ownership transfer Potential early deassertion LOCK# during split-lock cycles A20M# inverted after returning from Reset Reporting floating-point exception delayed EFLAGS discrepancy page fault after multiprocessor shootdown Near CALL creates unexpected address Deep sleep exit transition cause hang Built-in self test always gives nonzero result THERMTRIP# asserted specified Cache state corruption presence page A/D-bit setting snoop traffic Snoop cycle generates spurious machine check exception MOVD/MOVQ instruction writes memory prematurely Memory type undefined nonmemory operations Infinite snoop stall during initialization systems
Fixed Fixed Fixed
Fixed Fixed Fixed Fixed NoFix Fixed NoFix NoFix Fixed Fixed Fixed Fixed Fixed Fixed NoFix NoFix
PENTIUM® PROCESSOR SPECIFICATION UPDATE
TdB0
Plans Fixed
ERRATA protocol conflict with optimized chipsets Data Operand Pointer zero after power Reset MOVD following zeroing instruction cause incorrect result Premature execution load operation prior exception handler invocation Read portion instruction execute twice Test must high during power Intervening writeback occur during locked transaction MC2_STATUS model-specific error code machine check architecture error code reversed Mixed cacheability lock variables problematic systems with debug register causes debug exception Upper four entries usable with Mode Mode paging write reordered around cacheable write Incorrect memory type used when MTRRs disabled Misprediction program flow cause unexpected instruction execution System report false errors Full In-Order Queue cause infinite DBSY# assertion Data breakpoint exception displacement relative near call corrupt System functional with ratio Fault CMPS/SCAS operation cause incorrect RDMSR WRMSR invalid cause fault SYSENTER/SYSEXIT instructions implicitly load "null segment selector" registers
NoFix NoFix NoFix NoFix NoFix NoFix
A511 A521 A531 A541 A551 A561 A571 A581
NoFix NoFix NoFix Fixed
Fixed
NoFix
A591 A601 A611 A621
NoFix NoFix NoFix NoFix
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A631 A641 A651
TdB0
Plans NoFix NoFix
ERRATA PRELOAD followed EXTEST does load boundary scan data jump with D-bit cleared cause system hang Incorrect chunk ordering prevent execution machine check exception handler after BINIT# Resume Flag cleared after debug exception System address parity generator report false AERR#s Misaligned locked access APIC space results hang Potential loss data coherency during data ownership transfer Memory ordering based synchronization cause livelock condition systems APIC access cacheable memory causes SHUTDOWN 2-way systems hang catastrophic errors during determination Write mask (programmed EXTINT) will deassert outstanding interrupt
A661 A671 A681 A691 A701
NoFix NoFix NoFix NoFix NoFix
A1AP A2AP
NoFix NoFix
A3AP
NoFix
This number needs incremented when attempting correlate previous revision's numbering scheme where numbering nomenclature used. example, existing Pentium® processor Erratum equivalent previous Pentium processor Erratum
TdB0
Plans
DOCUMENTATION CHANGES S.E.C. cartridge mechanical specification corrections Stop-Grant state correction Correction Stop-Grant state definition 400MHz SECC2 PLGA part spec addition
TdB0
Plans
SPECIFICATION CLARIFICATIONS PWRGOOD inactive pulse width
PENTIUM® PROCESSOR SPECIFICATION UPDATE
TdB0
Plans
SPECIFICATION CHANGES System timings changes FRCERR removed from specification footnote PWRGOOD inactive pulse width PICCLK rise fall times System specifications (clock) Thermal design specification Non-GTL+ output leakage current change
Mixed Steppings Systems
Intel Corporation fully supports mixed steppings Pentium processors. following list processor matrix describes requirements support mixed steppings: While Intel done nothing specifically prevent processors operating differing frequencies from functioning within dual processor system, there uncharacterized errata that exist such configurations. Intel does support such configurations. mixed stepping systems, processors must operate identical frequencies (i.e., highest frequency rating commonly supported processors). While there known issues associated with mixing processors with differing cache sizes dual processor system, Intel done nothing specifically prevent such system configurations from operating, Intel does support such configurations since there uncharacterized errata that exist. mixed stepping systems, processors must same cache size. While Intel believes that certain customers wish perform validation system configurations with mixed frequency cache sizes, that those efforts acceptable option customers, customers would fully responsible validation such configurations. workarounds identified this following specification updates must properly applied each processor system. Certain errata specific multiprocessor environment identified Mixed Stepping Processor Matrix found this section. Errata processor steppings will affect system performance properly worked around. Also "Pentium® Processor Identification Package Information" section additional details which processors affected specific errata. mixed stepping systems, processor with lowest feature-set, determined CPUID Feature Bytes, must Bootstrap Processor (BSP). event feature-set, should resolved selecting processor with lowest stepping determined CPUID instruction.
following processor matrix, "NI" indicates that there currently known issues associated with mixing these steppings. number indicates that known issue been identified listed table following matrix. dual processor system using mixed processor steppings must assure that errata addressed appropriately each processor.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Platform Population Matrix Pentium® Processor with System Pentium® Processor Stepping 266-MHz 300-MHz 233-MHz 266-MHz 300-MHz 266-MHz 333-MHz 300-MHz 333-MHz 266-MHz 300-MHz 333-MHz
NOTE: Errata A17, listed Pentium® Processor Specification Update, problematic systems which Pentium® processor, model stepping. Please Pentium® Processor Specification Update further information. Mixing processors different frequencies supported.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Platform Population Matrix Pentium® Processor with System Pentium® Processor Stepping
Mixing processors different frequencies supported.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
ERRATA
Data Operand Pointer Incorrectly Calculated After Access Which Wraps 64-Kbyte Boundary 16-Bit Code
PROBLEM: Data Operand Pointer effective address operand associated with last
noncontrol floating-point instruction executed machine. 80-bit floating-point access (load store) occurs 16-bit mode other than protected mode which case access will produce segment limit violation), memory access wraps 64-Kbyte boundary, floating-point environment subsequently saved, value contained Data Operand Pointer incorrect.
IMPLICATION: 32-bit operating system running 16-bit floating-point code encounter this erratum, under
following conditions: operating system using segment greater than Kbytes size. application running 16-bit mode other than protected mode. 80-bit floating-point load store which wraps 64-Kbyte boundary executed. operating system performs floating-point environment store (FSAVE/FNSAVE/FSTENV/FNSTENV) after above memory access. operating system uses value contained Data Operand Pointer.
Wrapping 80-bit floating-point load around segment boundary this normal programming practice. Intel currently identified software which exhibits this behavior.
WORKAROUND: Data Operand Pointer used which 16-bit floating-point code, care must taken ensure that 80-bit floating-point accesses wrapped around 64-Kbyte boundary. STATUS: steppings affected Summary Table Changes beginning this section.
Differences Exist Debug Exception Reporting
PROBLEM: There exist some differences reporting code data breakpoint matches between that
specified previous Intel processors' specifications behavior Pentium processor, described below: CASE first case breakpoint MOVSS POPSS instruction, when instruction following causes debug register protection fault (DR7.gd already set, enabling fault). processor reports delayed data breakpoint matches from MOVSS POPSS instructions setting matching DR6.bi bits, along with debug register protection fault (DR6.bd). additional breakpoint faults matched during call debug fault handler, processor sets breakpoint match bits (DR6.bi) reflect breakpoints matched both MOVSS POPSS breakpoint debug fault handler call. Pentium processor only sets DR6.bd either situation, does DR6.bi bits. CASE second breakpoint reporting failure case, MOVSS POPSS instruction with data breakpoint followed store memory which crosses 4-Kbyte page boundary, breakpoint information MOVSS POPSS will lost. Previous processors retain this information across such page split.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
CASE they occur after MOVSS POPSS instruction, INTO, INT3 instructions zero DR6.Bi bits (bits through B3), clearing pending breakpoint information, unlike previous processors. CASE data breakpoint (System Management Interrupt) occur simultaneously, will serviced call handler, pending breakpoint will lost. CASE When instruction which accesses debug register executed, breakpoint encountered instruction, breakpoint reported twice.
IMPLICATION: When debugging when developing debuggers Pentium processor-based system, this
behavior should noted. Normal usage MOVSS POPSS instructions (i.e., following them with ESP) will exhibit behavior cases 1-3. Debugging conjunction with will limited case
WORKAROUND: Following MOVSS POPSS instructions with instruction when using breakpoints will avoid first three cases this erratum. workaround been identified cases STATUS: steppings affected Summary Table Changes beginning this section.
FLUSH# Servicing Delayed While Waiting STARTUP_IPI 2-way Systems
PROBLEM: 2-way system, application processor waiting startup inter-processor interrupt
(STARTUP_IPI), then will service FLUSH# assertion until received STARTUP_IPI.
IMPLICATION: After 2-way initialization protocol, only processor becomes bootstrap processor (BSP). other processor becomes slave application processor (AP). After losing arbitration, goes into wait loop, waiting STARTUP_IPI.
wake perform some tasks with STARTUP_IPI, then back sleep with initialization inter-processor interrupt (INIT_IPI, which same effect asserting INIT#), which returns wait loop. result possible loss cache coherency off-line processor intended service FLUSH# assertion this point. FLUSH# will serviced soon processor awakened STARTUP_IPI, before other instructions executed. Intel encountered operating systems that affected this erratum.
WORKAROUND: Operating system developers should take care execute WBINVD instruction before taken off-line using INIT_IPI. STATUS: steppings affected Summary Table Changes beginning this section.
Code Fetch Matching Disabled Debug Register Cause Debug Exception
PROBLEM: bits L0-3 G0-3 enable breakpoints local task global tasks, respectively. these bits set, breakpoint enabled, corresponding addresses debug registers DR0-DR3. least these breakpoints enabled, these registers disabled (i.e., disabled register (indicating breakpoint instruction execution), normally instruction fetch will cause instruction-breakpoint fault based match with address disabled register(s). However,
PENTIUM® PROCESSOR SPECIFICATION UPDATE
address disabled register matches address code fetch which also results page fault, instruction-breakpoint fault will occur.
IMPLICATION: While debugging software, extraneous instruction-breakpoint faults encountered breakpoint registers cleared when they disabled. Debug software which does implement code breakpoint handler will fail, this occurs. handler present, fault will serviced. Mixing data code exacerbate this problem allowing disabled data breakpoint registers break instruction fetch. WORKAROUND: debug handler should clear breakpoint registers before they become disabled. STATUS: steppings affected Summary Table Changes beginning this section.
Double Error Read Result BINIT#
PROBLEM: this erratum occur, following conditions must met:
Machine Check Exceptions (MCEs) must enabled. dataless transaction (such write invalidate) must occurring simultaneously with transaction which returns data normal read). read data must contain double-bit uncorrectable error.
these conditions met, Pentium processor will able determine which transaction erroneous, instead generating MCE, will generate BINIT#.
IMPLICATION: will reinitialized this case. However, since double-bit uncorrectable error occurred read, handler (which normally reached double-bit uncorrectable error read) would most likely cause same BINIT# event. WORKAROUND: Though ability drive BINIT# disabled Pentium processor, which would
prevent effects this erratum, overall system behavior would improve, since error which would normally cause BINIT# would instead cause machine shut down. other workaround been identified.
STATUS: steppings affected Summary Table Changes beginning this section.
Inexact-Result Exception Flag
PROBLEM: When result floating-point operation exactly representable destination format (1/3 binary form, example), inexact-result (precision) exception occurs. When this occurs, (bit status word) normally processor. Under certain rare conditions, this when this rounding occurs. However, other actions taken processor (invoking software exception handler exception unmasked) affected. This erratum only occur floating-point operation which causes precision exception immediately followed following instructions:
m32real m64real FSTP m32real FSTP m64real FSTP m80real FIST m16int FIST m32int
PENTIUM® PROCESSOR SPECIFICATION UPDATE
FISTP m16int FISTP m32int FISTP m64int
Note that even this combination instructions encountered, there also dependency internal pipelining execution state both instructions processor.
IMPLICATION: Inexact-result exceptions commonly masked ignored applications, happens frequently, produces rounded result acceptable most applications. status word always upon receiving inexact-result exception. Thus, these exceptions unmasked, floating-point error exception handler recognize that precision exception occurred. Note that this "sticky" bit, i.e., once inexact-result condition, remains until cleared software. WORKAROUND: This condition avoided inserting instructions between floating-point
instructions.
STATUS: steppings affected Summary Table Changes beginning this section.
Bfor Will Contain Incorrect FROM
PROBLEM: system management interrupt (SMI) will produce Branch Trace Message (BTM), BTMs enabled. However, FROM field B(used determine address instruction which being executed when serviced) will have been updated SMI, field will report same FROM previous BTM. IMPLICATION: Bwhich issued will contain correct FROM EIP, limiting usefulness BTMs debugging software conjunction with System Management Mode (SMM). WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
Restart Fail After Simultaneous
PROBLEM: instruction (IN, INS, INS, OUT, OUTS, OUTS) being executed, data this instruction becomes corrupted, Pentium processor will signal machine check exception (MCE). instruction directed device which powered down, processor also receive assertion SMI#. Since MCEs have higher priority, processor will call handler, SMI# assertion will remain pending. However, upon attempting execute first instruction handler, SMI# will recognized processor will attempt execute handler. handler completed successfully, will attempt restart instruction, will have correct machine state, call handler. IMPLICATION: simultaneous SMI# assertion occur instructions above. handler attempt restart such instruction, will have corrupted state handler call, leading failure restart shutdown processor. WORKAROUND: system implementation must support both MCEs, first thing handler
code (when restart performed) should check pending MCE. there pending, handler should immediately exit instruction allow machine check exception handler execute. there not, handler proceed with normal operation.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Branch Traps Function BTMs Also Enabled
PROBLEM: branch traps branch trace messages (BTMs) enabled alone, both function expected. However, both enabled, only BTMs will function, branch traps will ignored. IMPLICATION: branch traps branch trace message debugging features cannot used together. WORKAROUND: branch trap functionality desired, BTMs must disabled. STATUS: steppings affected Summary Table Changes beginning this section.
A10.
Checker BIST Failure Mode Signaled
PROBLEM: system running functional redundancy checking (FRC) mode, checker master-checker pair encounters hard failure while running built-in self test (BIST), checker will tri-state outputs without signaling IERR#. IMPLICATION: Assuming master passes BIST successfully, will continue execution unchecked, operating without functional redundancy. However, necessary pull-up FRCERR will cause FRCERR signaled. operation master depends implementation FRCERR. WORKAROUND: successful detection BIST failure checker pair, FRCERR
signal, instead IERR#.
STATUS: steppings affected Summary Table Changes beginning this section.
A11.
BINIT# Assertion Causes FRCERR Assertion Mode
PROBLEM: pair Pentium processors running functional redundancy checking (FRC) mode,
catastrophic error condition causes BINIT# asserted, checker master-checker pair will enter shutdown. next transaction from master will then result assertion FRCERR.
IMPLICATION: initialization assertion BINIT# occurs result catastrophic error condition which precludes continuing reliable execution system. Under normal circumstances, masterchecker pair would remain synchronized execution BINIT# handler. However, this erratum, FRCERR will signaled. System behavior then depends system specific error recovery mechanisms. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A12.
Machine Check Exception Handler Always Execute Successfully
PROBLEM: asynchronous machine check exception (MCE), such BINIT# event, which occurs during
access that splits 4-Kbyte page boundary leave some internal registers indeterminate state. Thus, handler code always successfully asynchronous occurred previously.
IMPLICATION: always result successful execution handler. However, asynchronous MCEs usually occur upon detection catastrophic system condition that would also hang processor. Leaving MCEs disabled will result condition which caused asynchronous instead causing processor enter shutdown. Therefore, leaving MCEs disabled improve overall system behavior.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: workaround which would guarantee successful handler execution under this condition been identified. STATUS: steppings affected Summary Table Changes beginning this section.
A13.
Parity Error Gives MCACOD.LL
PROBLEM: Cache Reply Parity (CRP) error, Cache Address Parity (CAP) error, Cache Synchronous Error (CSER) occurs access Pentium processor's cache, resulting Machine Check Architectural Error Code (MCACOD) will logged with `01' field. This value indicates cache error; value should `10', indicating cache error. Note that errors have correct value `10' logged. IMPLICATION: cache access error, other than error, will improperly logged cache error MCACOD.LL. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A14.
LBER Corrupted After Some Events
PROBLEM: last branch record (LBR) last branch before exception record (LBER) used determine source destination information previous branches exceptions. contains source destination addresses last branch exception, LBER contains similar information last branch taken before last exception. This information typically used determine location branch which leads execution code which causes exception. However, after catastrophic condition which results assertion BINIT# re-initialization buses, value LBER corrupted. Also, after either CALL which results fault software interrupt, LBER will updated same value, when LBER should have been updated. IMPLICATION: LBER registers used only debugging purposes. When this erratum occurs, LBER will contain reliable address information. value LBER should used with caution when debugging branching code; values LBER same, then LBER value incorrect. Also, value LBER should relied upon after BINIT# event. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A15.
BTMs Corrupted During Simultaneous Cache Line Replacement
PROBLEM: When Branch Trace Messages (BTMs) enabled such message generated, Bcorrupted when issued cache line data brought into data cache simultaneously. Though line being stored cache stored correctly, corruption occurs data, information Bmay incorrect internal collision data line BTM.
IMPLICATION: Although BTMs entirely reliable this erratum, conditions necessary this boundary condition occur have only been exhibited during focused simulation testing. Intel currently observed this erratum system level validation environment. WORKAROUND: None identified this time.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
A16.
System Hang Internal Protocol Violation
PROBLEM: Pentium processor-based systems hang internal protocol violation. When
snoopable transaction issued cache line being accessed modified state, processor must deliver system updated copy cache line. When processor attempts deliver most date copy implicit writeback, data transfer transaction fails DBSY# signal remains asserted until next RESET#. This causes system hang indefinitely. order encounter this erratum, following sequence events must occur: snoopable transaction (transaction issued system bus. processor contains and/or caches data this line modified state. Another snoopable transaction (transaction issued processor contains this line only cache modified state. Both these transactions issued either chipset, processor which case they self-snoop type), another processor (2-way systems), combination thereof. nonsnoopable transaction then issued (transaction which address bits A15-A5 same those transaction Transaction followed snoopable transaction (transaction completion data transfer phase transaction must line with snoop response phase transaction This data transfer phase transaction must occur after ADS# transaction line with completion internal cache transaction. internal cache transaction must miss targeting line eviction, internal cache transaction must such that retried.
result this sequence transactions causes processor lock after delivering data transaction prior delivering data transaction Since this data never delivered, DBSY# does deassert system hangs.
IMPLICATION: Pentium processor cause system hang above listed sequence events
occurs. This sequence necessary condition erratum, multiple variations this sequence which also cause this erratum also possible. probability encountering this erratum increases with queue depth greater than 2-way systems.
WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A17.
Livelock Condition Cause System Hang
PROBLEM: "livelock" situation could occur 2-way Pentium processor-based systems, when depth with failure signature such that processor arbitrates system fails drive transaction when gains ownership bus. processor then relinquishes ownership another requester, rearbitration performs same repetitive actions. This course action continues until RESET# asserted. failure signature 2-way systems such that both processors require execution explicit writeback cycle both processors request this transaction. However, when time comes drive writeback transaction, internal request been suspended internal blocking condition. After internal blocking condition gone away original writeback request
PENTIUM® PROCESSOR SPECIFICATION UPDATE
reasserted. However, time ownership been regained, blocking condition recurred, thus suppressing writeback request before transaction driven system bus. writeback which waiting system must issued before internal blocking condition removed. writeback never issued because recurring blocking condition. This causes "infinite loop" situation develop, processor essentially stops executing code.
IMPLICATION: This erratum observed occur when both processors configured depth
Intel commercial system testing.
WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A18.
Mispredicted Branch Cause Incorrect Word MMXTechnology Instructions
PROBLEM: After MMXtechnology instruction executed, stack registers should marked
valid word. more first three instructions mispredicted branch technology instructions form "opcode reg, mem" including MOVD MOVQ, word incorrectly modified. Some word bits remain invalid. This word will remain incorrect until events occur: MMXtechnology instruction executed four more instructions after branch target, technology instruction following type executed: technology instruction form "opcode reg, reg" MOVD MOVQ EMMS
following examples code that will encounter this erratum.
Example
EMMS target: PADDW mm0, [edi] FSTENV this example, word stored memory FSTENV will incorrect. "reg, mem" format instruction target mispredicted taken
Example
EMMS target mispredicted taken
PENTIUM® PROCESSOR SPECIFICATION UPDATE
target: PADDW mm0, [edi] FUCOMPP FWAIT this example, FUCOMPP instruction will cause Numeric Invalid Operation Exception stack fault exception unmasked. depends word, also violates coding guideline against mixing floating-point MMXtechnology instructions
IMPLICATION: When writing code that mixes technology instructions where target branch technology instruction with memory operand, word incorrect. Software that expects stack register valid after technology instruction utilizes this information affected.
floating-point instructions intermixed, floating-point instructions raise floating-point stack exception. this exception unmasked, application will receive unexpected numeric exception. result application dependent. floating-point stack exception masked, floating-point instruction will compute with indefinite operand instead register contents. either case result application dependent. Applications that follow Intel Technology Coding Guidelines against intermixing floatingpoint technology code affected this erratum. floating-point word saved immediately after affected technology instruction, erroneous value will stored. Program behavior application dependent. This also cause debuggers temporarily display incorrect word contents.
WORKAROUND: following must applied work around this erratum:
Follow Intel MMXtechnology guidelines Intel Architecture Optimization Manual writing technology programs. Specifically, intermix technology instructions floating-point instructions instruction basis. possible that some word bits invalid prior branch, avoid using technology instructions form "opcode reg, mem", except MOVD, MOVQ, within first three instructions target branch. FSAVE instruction save floating-point stack registers least registers valid during context switch. Before transition from technology code floating-point code that does meet Intel Technology Guidelines Intel Architecture Optimization Manual, execute nonsusceptible technology instruction such MOVD eax, mm0. Floating-point instructions should depend technology instructions word bits valid.
STATUS: steppings affected Summary Table Changes beginning this section.
A19.
Thermal Sensor/THERMTRIP# Does Work
PROBLEM: THERMTRIP# feature Pentium processor which asserts when core reaches
certain temperature during operation specified Pentium® Processor MHz, MHz, MHz, datasheet. Pentium processor assert THERMTRIP# temperature lower higher than specified trippoint TJUNCTION. When THERMTRIP# asserted, processor shut down causing execution halted.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: When running Pentium processor, Pentium processor core reach temperature
causing processor assert THERMTRIP# early. Once THERMTRIP# been asserted, processor shut down this erratum. execution after SHUTDOWN will halted. This erratum only exhibited when TPLATE above Maximum Specification (see Pentium® Processor MHz, MHz, MHz, datasheet (Order Number 243335) details specifications).
WORKAROUND: Avoid operation Pentium processor outside thermal specifications defined
Pentium® Processor MHz, MHz, MHz, datasheet. monitor THERMTRIP# (pin A15).
STATUS: steppings affected Summary Table Changes beginning this section.
A20.
Spurious Machine Check Exception Data Parity Error
PROBLEM: Pentium processor signal unrecoverable Machine Check Exception (MCE) event that Instruction Fetch Unit (IFU) detects mismatch when verifying instruction parity. execution code which modifies current instruction sequence that already fetched into processor cause instruction given address appear differently depending when fetched time relative being modified. Thus, speculatively prefetched instruction have been modified such that differs from copy same instruction resident instruction cache. This discrepancy copy located speculative prefetch portion, different copy instruction cache) sensed IFU. When detects that instruction stream been modified, flushes pipeline attempts restart instruction stream. interim, recognizes disparate instructions described above, signals data parity error. data parity error signaled before instruction stream chance restart. This will cause operating system that enabled shut down. incorrect code executed processor this situation (even disabled). Note that this erratum occurs under specific address dependencies timing events. IMPLICATION: Executing such sequence modifying code without proper synchronization always result predictable program behavior. processor's signaling data parity error then result unexpected system halt above conditions MCEs enabled. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A21.
Loss Inclusion Cause Machine Check Exception
PROBLEM: Pentium processor signal unrecoverable Machine Check Exception (MCE) consistency checking mechanism event that Instruction Fetch Unit (IFU) detects differences consistency code instruction streaming buffers against code resident instruction cache, i.e., loss inclusion. When application code makes operating system call, processor transitions execution privilege levels. code call already resident level cache, then processor prefetch code while identifying cache line(s) eventual eviction make space code. Upon return from call, processor continues execution application code user level. processor, deep speculation branch prediction, attempt execute instructions from previously prefetched kernel code starting attempting replace victim line with kernel code buffer internal IFU. detects that current application insufficiently privileged execute kernel code suppresses eviction previously selected victim line. Despite having detected this condition, does replace this victim line with kernel line. processor attempts restart execution current application code refetching original victim line longer finds instruction cache. detects this loss inclusion, signals this generating MCE. MCEs enabled, this event cause operating system shutdown. Note that this erratum occurs under specific address dependencies timing events.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: occurrence conditions above lead signal loss inclusion generating MCE. MCEs enabled system, then operating system shut down upon noticing resulting system failure. MCEs disabled, then unpredictable application behavior theoretically possible, although current validation shown execution continue normally. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A22.
Possible System Hang When Paging Disabled Reenabled from Uncached Memory
PROBLEM: paging disabled then later reenabled while executing code from
page marked uncachable Page Table Entry (PCD=1) located memory mapped Write Back Write Through processor MTRRs, processor could internally enter state resulting system hang.
IMPLICATION: Operating systems that enable disable paging with above described memory configurations could hang. Intel observed this erratum date laboratory testing commercially available operating systems applications. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A23.
Performance Counters Miscount L2_RQSTS
PROBLEM: L2_RQSTS performance counter that counts number cache access requests. This
counter increments each incoming cache request. some cases, request cannot serviced Cache. This request then retried later time when request serviced cache. When this happens, L2_RQSTS counter counts initial cache request retried cache request, thereby counting same request twice.
IMPLICATION: L2_RQSTS counter contain larger erroneous number cache requests this erratum. This erratum does affect functionality Pentium processor. This erratum only affects performance counter specified. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A24.
Erroneous Signaling User Mode Protection Violation
PROBLEM: Pentium processor attempts access page physical memory marked present
(Present clear), page fault exception (#PF) generated. Before proceeding, there narrow internal timing window where processor verifies that other higher priority fault conditions present. During this time, possible another agent allocate page directory page table entry (PDE/PTE) corresponding same linear address original access, writing values into PDE/PTE with Access (A-bit) Dirty (D-bit) cleared. When original processor completes checking other fault conditions, re-examines recently modified PDE/PTE, finds that been cleared. Internal hardware correctly signals this scenario condition which processor should respond setting bit, erroneously reports generic paging protection violation. Instead attempting appropriate bit, this event reported Int14 with exception code 0x05, i.e., user mode protection violation.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: occurrence this scenario will result erroneous signaling user mode protection violation instead page fault result application termination depending operating system behavior response user mode protection violation. Intel only observed this erratum date laboratory testing multi-processor systems. WORKAROUND: Operating systems which allocate PTEs PDEs should Access (A-bit) Dirty (D-bit) workaround this erratum. Alternatively, operating system's Int14 handler determine protection violation condition truly exists, none found, return without further action. STATUS: steppings affected Summary Table Changes beginning this section.
A25.
Invalid Operation Signaled FIST Instruction Some Range Operands
PROBLEM: certain, large, negative, floating-point operands, only three four possible processor
rounding modes, instructions FIST[P] m16int FIST[P] m32int detect that operand large that will into target data size. consequence, expected Invalid Operation exception response this situation correctly provided, Invalid Operation flag Floating Point status word specified Intel Architecture Software Developer's Manual, Volume Instruction Reference. Under failing conditions, noted below, precision exception (#PE) flag will also incorrectly set. erratum occurs only when following conditions met: FIST[P] instruction either 32-bit operation; 64-bit operations unaffected. Either nearest zero' `up' rounding modes being used. round `down' mode unaffected this erratum. sign floating-point operand negative. floating-point operand being converted significantly more negative than described integer size being targeted. ACTUAL EXPECTED RESPONSE
Actual Response
When required conditions encountered, processor provides following response: Return MAXNEG value (8000h FIST16 80000000h FIST32) memory. (Invalid Operation) Floating Point status word flag invalid operand. (precision error) Floating Point status word set. exception handler invoked. case FISTP instruction Operand will have been popped from floating-point stack.
Expected Response
expected processor response when invalid operation exception masked Return MAXNEG value (8000h FIST16 80000000h FIST32) memory. (Invalid Operation) Floating Point status word flag overflow. (precision error) Floating Point status word set.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
expected processor response when invalid operation exception unmasked return result memory. Keep original operand intact stack. (Invalid Operation) Floating Point status word flag overflow. (precision error) Floating Point status word set. Vector user numeric exception handler.
IMPLICATION: Erroneous operation results when operand large that will into target data size. operands affected this erratum significantly outside factor range that correctly, converted integer value. figure below corresponding table identifies normal range integer numbers (between starting point operands affected this erratum. Discrete failing operands will present range between point maximum negative number that 1023 represented processor double precision format). Note below gives qualitative description nature discrete failing values. Software that does rely Invalid Operation exception flag being signaled either exception software polling impacted this erratum.
1023
1023
Range potentially affected numbers. number this range affected
Range valid Integer
16-bit Operation
-32,768.0
+32,767.0 +2,147,483,647.0
-98304.0 -6,442,450,944.0
32-bit Operation
-2,147,483,648.0
WORKAROUND: software workarounds will avoid occurrence this erratum:
Range checking performed prior execution FIST[P] instruction will prevent overflow condition from occurring, already implemented coding style. Software presence MAXNEG result integer indicate that range conversion have occurred. Note possible alternative FIST64 instruction store converted operand memory access lower bits required integer. Even though this mechanism will signal attempted range conversion with target, currently many compilers today. Note values affected this erratum those which contain exponent value within affected range, specific pattern specific offset within mantissa, least nonzero right above pattern. offset within mantissa function floating-point exponent value. specific pattern 0x8000 FIST16 0x80000000 FIST32. This means that given exponent within range, mantissa value every possible mantissa values exhibits erratum FIST16, mantissa value every possible mantissa values exhibits erratum FIST32.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Examples affected values FIST16, 80-bit binary notation (not exhaustive list) means pattern, means nonzero pattern)
sign exponent 100000000010100 100000000010101 100000000010110 mantissa
Examples affected values FIST32, 80-bit binary notation (not exhaustive list) means pattern, means nonzero pattern)
sign exponent 100000000100011 100000000100100 100000000100101 mantissa
STATUS: steppings affected Summary Table Changes beginning this section.
A26.
FLUSH# Assertion Disables Machine Check Exception Reporting
PROBLEM: Upon FLUSH# assertion, Machine Check Exception generation disabled. Once
FLUSH# asserted, processor disables MCA, clearing associated MCi_CTL control register "0"s. This operation invisible software being executed.
IMPLICATION: Errors that should reported reported from time that FLUSH#
signal asserted until time that MCi_CTL register written back "1"s. other errors will continue logged normal.
WORKAROUND: Platform specific code (e.g., BIOS system management software) potential
driving device assert FLUSH# pin. platform specific code asserts FLUSH# pin, this code should enhanced detect that Exceptions globally enabled (via register CR4.MCE). code should then write "0"s MCi_CTL registers clear spurious entries then write "1"s MCi_CTL registers order re-enable exception reporting. Hardware devices systems that require error reporting which could assert FLUSH# should assert FLUSH#.
STATUS: steppings affected Summary Table Changes beginning this section
A27.
EFLAGS Incorrect After Multiprocessor Shootdown
PROBLEM: When Pentium processor executes read-modify-write arithmetic instruction with memory
destination, possible page fault occur during execution store memory operand after read operation completed before write operation completes. this case EFLAGS value pushed onto stack page fault handler reflective status EFLAGS register after instruction would have completed execution rather than that before executed under certain circumstances. This class instruction will initially perform load operation that side effect ensuring that final store portion instruction will successfully complete. load ensures this bringing page table information page containing data into DTLB. This page entry could evicted from DTLB speculative loads from other instructions that same DTLB, before store
PENTIUM® PROCESSOR SPECIFICATION UPDATE
executed. DTLB eviction will require least three load operations that have linear address bits 15:12 equal each other address bits 31:16 different from each other close physical proximity arithmetic operation. very small window time between page eviction store execution, page table entry page permissions tightened (e.g., from Present Present, from Read/Write Read Only, etc.) operating system main memory another processor (with corresponding synchronization subsequent flush), store will generate DTLB miss call OS's page fault handler. EFLAGS register have already been updated arithmetic portion instruction before entry page fault handler. under these circumstances fault handler elects restart instruction, re-execution generate incorrect result. Instructions affected this erratum memory destination forms ADC, SBB, (instructions that flag, carry, input instruction). should noted that locked version these instructions impacted this erratum.
IMPLICATION: This scenario only occur multiprocessor system running under operating system that
implements "lazy" shootdown. Lazy shootdown occurs when processor makes changes page tables memory, then signals other processors remove page entry from their without multiprocessor synchronization being performed. date, Intel observed this erratum laboratory testing commercially available software applications. multiprocessor system arithmetic flags EFLAGS register memory stack image, contain incorrect data read-modify-write arithmetic instruction encounters page fault. Page Fault handler software that uses resulting EFLAGS incorrect information. original instruction restarted page fault handler, instruction produce incorrect results based prior modifications EFLAGS register.
WORKAROUND: Software locked form ADC, SBB, instructions avoid this erratum. Operating systems should ensure that processor currently accessing page that scheduled have page permissions tightened, e.g., moved from Present Present have page fault handler that handle incorrect state. Intel working with Multiprocessor Operating System vendors ensure that level workaround implemented required. STATUS: steppings affected Summary Table Changes beginning this section.
A28.
Delayed Line Invalidation Issue During 2-Way Data Ownership Transfer
PROBLEM: 2-way systems, each processor attempt modify different portion same cache line, referenced line discussion below. When this erratum occurs (with following example given 2-way system with processors noted `P0' `P1'), each processor contains shared copy line both their caches. Each processor must issue invalidation cycle before that processor definitively source results internal write portion line other processors.
There exists narrow timing window when, wins external invalidation race gains ownership rights line sequence invalidation traffic, have completed pending invalidation own, currently valid shared copy line During this window, possible internal opportunistic write portion line (while awaiting ownership rights) occur with original shared copy line still resident P1's cache. Such internal modification permissible subject delaying broadcast such changes until line ownership actually been gained. However, processor must ensure that internal re-read line returns with data order actually written; this case, this should data written case this erratum, internal re-read uses data which written
IMPLICATION: Multiprocessor threaded application synchronization that implemented operating systemprovided synchronization constructs affected this erratum. Applications which rely upon usage locked semaphores rather than memory ordering also unaffected. Uniprocessor systems affected this erratum. Intel identified, date, commercially available application operating system software which affected this erratum. erratum does occur, delayed line invalidation that occurs naturally
PENTIUM® PROCESSOR SPECIFICATION UPDATE
fact that processor will necessarily invalidation race allows narrow timing window exist where processor re-read line that just wrote internally, return with stale data that present from previous shared state rather than data written more recently another processor.
WORKAROUND: Deterministic barriers beyond which program variables will modified achieved
usage locked semaphore operations, this scheme been shown effectively work around this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
A29.
Potential Early Deassertion LOCK# During Split-Lock Cycles
PROBLEM: During split-lock cycle there four transactions: ADS# partial read), ADS# partial read), ADS# partial write), ADS# partial write). this erratum, LOCK# deassert clock after ADS# split-lock cycle instead after assertion corresponding ADS# been sampled. following sequence events required this erratum occur:
lock cycle occurs (split nonsplit). Five more transactions (assertion ADS#) occur. split-lock cycle occurs BNR# toggles after ADS# (partial write) split-lock cycle. This turn delays assertion ADS# split-lock cycle. BNR# toggling this time could most likely happen when depth When these events occur, LOCK# will deasserted next clock after ADS# split-lock cycle.
IMPLICATION: This affect chipset logic which monitors behavior LOCK# deassertion. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A30.
A20M# Inverted After Returning From Reset
PROBLEM: This erratum seen when software causes following events occur:
assertion A20M# real address mode. After entering 1-Mbyte address wrap-around mode caused assertion A20M#, there assertion SMI# intended cause Reset remove power processor. Once handler, software saves state save area nonvolatile memory from which restored some point future. Then software asserts RESET# removes power processor. After exiting Reset completion power-on, software asserts SMI# again. Once handler, then retrieves state save which saved event above copies into current state save map. Software then asserts A20M# executes instruction. After exiting handler, polarity A20M# inverted.
IMPLICATION: this erratum occurs, A20M# will behave with polarity opposite from what expected (i.e.,
1-Mbyte address wrap-around mode enabled when A20M# deasserted, does occur when A20M# asserted).
WORKAROUND: Software should save A20M# signal state nonvolatile memory before assertion
RESET# power down condition. After coming Reset power SMI# should asserted again. During restoration state save described event above, entire should restored, except byte offset 7F18h. This should retain value assigned when
PENTIUM® PROCESSOR SPECIFICATION UPDATE
state save created event handler should then restore original value A20M# signal.
STATUS: steppings affected Summary Table Changes beginning this section.
A31.
Reporting Floating-Point Exception Delayed
PROBLEM: Pentium processor normally reports floating-point exception instruction when next floating-point technology instruction executed. assertion FERR# and/or interrupt corresponding exception delayed until floating-point technology instruction after which expected trigger exception, following conditions met:
floating-point instruction causes exception. Before another floating-point MMXtechnology instruction, following occurs: subsequent data access occurs page which been marked accessed, Data referenced which crosses page boundary, possible page-fault condition detected which, when resolved, completes without faulting.
instruction causing event above followed MOVQ MOVD store instruction.
IMPLICATION: This erratum only affects software which operates with floating-point exceptions unmasked.
Software which requires floating-point exceptions visible next floating-point technology instruction, which uses floating-point calculations data which then used technology instructions, delay reporting floating-point instruction exception some cases. Note that mixing floating-point technology instructions this recommended.
WORKAROUND: Inserting WAIT FWAIT instruction reading floating-point status register) between
floating-point instruction MOVQ MOVD instruction will give expected results. This already recommended practice software.
STATUS: steppings affected Summary Table Changes beginning this section.
A32.
EFLAGS Discrepancy Page Fault After Multiprocessor Shootdown
PROBLEM: This erratum occur when Pentium processor executes following read-modifywrite arithmetic instructions page fault occurs during store memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, XADD. this case, EFLAGS value pushed onto stack page fault handler reflect status register after instruction would have completed execution rather than before following conditions required store generate page fault call operating system page fault handler:
store address entry must evicted from DTLB speculative loads from other instructions that same DTLB before store completed. DTLB eviction requires least three load operations that have linear address bits 15:12 equal each other address bits 31:16 different from each other close physical proximity arithmetic operation. page table entry store address must have permissions tightened during very small window time between DTLB eviction execution store. Examples page permission tightening include from Present Present from Read/Write Read Only, etc. Another processor, without corresponding synchronization flush, must cause permission change.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: This scenario only occur multiprocessor platform running operating system that performs "lazy" shootdowns. memory image EFLAGS register page fault handler's stack prematurely contains final arithmetic flag values although instruction completed. Intel identified operating systems that inspect arithmetic portion EFLAGS register during page fault observed this erratum laboratory testing software applications. WORKAROUND: workaround needed upon normal restart instruction, since this erratum
transparent faulting code results correct instruction behavior. Operating systems ensure that processor currently accessing page that scheduled have page permissions tightened have page fault handler that ignores incorrect state.
STATUS: steppings affected Summary Table Changes beginning this section.
A33.
Near CALL Creates Unexpected Address
PROBLEM: documented, CALL instruction saves procedure linking information procedure stack jumps called procedure specified with destination (target) operand. target operand specifies address first instruction called procedure. This operand immediate value, general purpose register, memory location. When accessing absolute address indirectly using stack pointer (ESP) base register, base value used value register before instruction executes. However, when accessing absolute address directly using base register, base value used value after return value pushed stack, value register before instruction executed. IMPLICATION: this erratum, processor transfer control unintended address. Results unpredictable, depending particular application, range from effect unexpected termination application exception. Intel observed this erratum only focused testing environment. Intel observed commercially available operating system, application, compiler that makes generates this instruction. WORKAROUND: other seven general purpose registers unavailable use, necessary
CALL register, first push onto stack, then perform indirect call using (e.g., CALL [ESP]). saved version should popped stack after call returns.
STATUS: steppings affected Summary Table Changes beginning this section.
A34.
Deep Sleep Exit Transition Cause Hang
PROBLEM: Under normal operating conditions, when system enters power conservation mode, enters System Management Mode (SMM), puts processor Stop Grant State, followed Sleep State then enter Deep Sleep State. Upon resume event, processor exits Deep Sleep remains execution space until handler completes system resume cycle.
prior entering Deep Sleep, system space, possible processor exit Deep Sleep state begin making accesses `normal' memory space instead staying space. converse also possible, i.e., processor `normal' space prior entering Deep Sleep state, processor exit Deep Sleep make accesses space instead.
IMPLICATION: Systems execute incorrect code after exiting Deep Sleep, accesses incorrect address space. This produce unpredictable behavior, most likely hanging system. WORKAROUND: Avoid entering Deep Sleep. table below offers possible state transitions:
PENTIUM® PROCESSOR SPECIFICATION UPDATE
System State Name ACPI Equivalent
Processor State Transition Normal Stop Grant Stop Grant Sleep Deep Sleep ACPI Equivalent
Possible Solutions Description Stop Grant/Sleep only; Deep Sleep Suggested Solution None necessary BIOS specify latency time >1000 ACPI FACP table (P_LVL3_LAT, worst case hardware latency state). BIOS prevent from entering state defining object ACPI DSDT table. Ensure that cache always flushed.
Active Active
Powered Suspend
Stop Grant Deep Sleep
Reset only flush cache without resetting bus, i.e., POS_CCL state (POS with Context Lost) instead state.
STATUS: steppings affected Summary Table Changes beginning this section.
A35.
Built-in Self Test Always Gives Nonzero Result
PROBLEM: Built-in Self Test (BIST) Pentium processor does give zero result indicate passing test. Regardless pass fail status, BIST result register after running BIST set. IMPLICATION: Software which relies zero result indicate passing BIST will indicate BIST failure. WORKAROUND: Mask BIST result register when analyzing BIST results. STATUS: steppings affected Summary Table Changes beginning this section.
A36.
THERMTRIP# Asserted Specified
PROBLEM: THERMTRIP# signal Pentium processor which asserted when core reaches critical temperature during operation detailed processor specification. Pentium processor assert THERMTRIP# until much higher temperature than specified reached. IMPLICATION: THERMTRIP# feature functional Pentium processor. Note that this erratum
only occur when processor running with TPLATE temperature over maximum specification
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: Avoid operation Pentium processor outside thermal specifications defined
processor specifications.
STATUS: steppings affected Summary Table Changes beginning this section.
A37.
Cache State Corruption Presence Page A/D-bit Setting Snoop Traffic
PROBLEM: operating system uses Page Access and/or Dirty feature implemented Intel architecture there significant amount snoop traffic bus, while processor setting Access and/or Dirty processor inappropriately change single cache line modified state. IMPLICATION: occurrence this erratum result cache incoherency, which cause parity errors, data corruption (with parity error), unexpected application operating system termination, system hangs. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A38.
Snoop Cycle Generates Spurious Machine Check Exception
PROBLEM: processor incorrectly generate Machine Check Exception (MCE) when processes snoop access that does data cache. internal logic error, this type snoop cycle still check data parity undriven data lines. processor generates spurious machine check exception result this unnecessary parity check. IMPLICATION: spurious machine check exception result unexpected system halt Machine Check
Exception reporting enabled operating system.
WORKAROUND: possible BIOS code contain workaround this erratum. This workaround would
erratum, however, data parity error will still reported.
STATUS: steppings affected Summary Table Changes beginning this section.
A39.
MOVD/MOVQ Instruction Writes Memory Prematurely
PROBLEM: When instruction encounters fault, faulting instruction should modify system state. However, when technology store instructions MOVD MOVQ encounter following events, possible store committed memory even though should canceled:
CR0.EM (Emulation bit), then store could happen prior triggered invalid opcode exception. floating-point Top-of-Stack TOS) zero, then store could happen prior executing processor assist routine that sets zero. there unmasked floating-point exception pending, then store could happen prior triggered unmasked floating-point exception. CR0.TS (Task Switched bit), then store could happen prior triggered Device Available (DNA) exception.
MOVD/MOVQ instruction restarted after handling above events, then store will performed again, overwriting with expected data. instruction will restarted after event instruction will definitely restarted after events instruction restarted after event depending specific exception handler.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: This erratum causes unpredictable behavior application MOVD/MOVQ instructions
used manipulate semaphores multiprocessor synchronization, these instructions used write uncacheable memory memory mapped that side effects, e.g., graphics devices. This erratum completely transparent applications that have these characteristics. When each above conditions analyzed: Setting CR0.EM forces floating-point/MMXinstructions handled software emulation. MOVD/MOVQ instruction, which instruction, would considered invalid instruction. Operating systems typically terminates application after getting expected invalid opcode fault. equal case only occurs when MOVD/MOVQ store first instruction technology routine previous floating-point routine clean floating-point states properly when exited. Floating-point routines commonly leave prior exiting. store executed first instruction technology routine following floating-point routine, software would implementing instruction level intermixing floating-point instructions. Intel does recommend this practice. unmasked floating-point exception case only occurs store first technology instruction technology routine previous floating-point routine exited with unmasked floating-point exception pending. Again, store executed first instruction technology routine following floating-point routine, software would implementing instruction level intermixing floating-point instructions. Intel does recommend this practice. Device Available (DNA) exceptions occur naturally when task switch made between tasks that either floating-point instructions and/or instructions. this erratum, event exception, data from prior task temporarily stored present task's program state.
WORKAROUND: instructions manipulate semaphores multiprocessor synchronization.
MOVD/MOVQ instructions write directly devices doing triggers user visible side effects. prevent data from being stored task's program state cleansing explicitly after every task switch. Follow Intel's recommended programming paradigms Intel Architecture Optimization Manual writing technology programs. Specifically, floating-point instructions. When transitioning technology routine, begin with instruction that does depend prior state either technology registers floating-point registers, such load PXOR mm0, mm0. sure that clear before using instructions.
STATUS: steppings affected Summary Table Changes beginning this section.
A40.
Memory Type Undefined Nonmemory Operations
PROBLEM: Memory Type field nonmemory transactions such Special Cycles undefined. Although Memory Type attribute nonmemory operations logically should (and usually does) manifest itself this feature designed into implementation therefore inconsistent. IMPLICATION: agents decode non-UC memory type nonmemory transactions. WORKAROUND: agents must consider transaction type determine validity Memory Type field
transaction.
STATUS: steppings affected, Summary Table Changes beginning this section.
A41.
Infinite Snoop Stall During Initialization Systems
PROBLEM: possible snoop traffic generated system while processor executing cache initialization routine cause initializing processor hang.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: (2-way) system which does suppress snoop traffic while caches being initialized
hang during this initialization sequence.
WORKAROUND: System BIOS create execution environment which allows processors initialize their caches without system generating snoop traffic bus.
Below pseudo-code fragment, designed explicitly processor system, that uses serial algorithm initialize each processor's cache: Suppress_all_I/O_traffic() while Obtain current value This forces both Temp into cache. Note that Temp could also maintained general purpose register. Temp logical_proc_APIC_id wait_10_usecs_delay_loop(); this time delay, required worst case, allows barrier semaphore settle shared state. Initialize cache else while (Temp This algorithm prevents snoop traffic from other processors, which would otherwise cause initializing processor hang. algorithm assumes that cache enabled (the Temp variables must cached each processor). Also, Memory Type Range Register (MTRR) data segment must (writeback) memory type.
STATUS: steppings affected Summary Table Changes beginning this section.
A42.
Protocol Conflict With Optimized Chipsets
PROBLEM: "dead" turnaround cycle with agent driving address, address parity, request command,
request parity signals must occur between processor driving these signals chipset driving them after asserting BPRI#. Pentium processor does follow this protocol. Thus, system uses chipset third party agent which optimizes arbitration latency (reducing clocks when observes active (low) ADS# signal inactive (high) LOCK# signal same clock that BPRI# asserted (driven low)), Pentium processor cause contention during unlocked exchange.
IMPLICATION: This violation exchange protocol when using reduced arbitration latency cause system-level setup timing violation address, address parity, request command, request parity signals system bus. This result system hang assertion AERR# signal, causing attempted corrective action shutdown system, system hardware software dictate. possibility failure contention caused this erratum increased processor's internal active pullup these signals clock after signals longer being driven processor.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: chipset third party agents used with Pentium processor optimize their
arbitration latency described above, action required. Pentium processor, action required. agents that have implemented this optimization, following GTL+ Layout Guidelines Pentium® Processor Intel 440BX AGPset UP-SET (single-ended termination) with both processors installed, action required. following cases additional guidelines UP-DET (dualended termination) DP-DET with only processor populated.
AGPset
Figure Dual Ended Termination (DET) UP-DET topologies (see Figure trace length must between 1.5" 4.5" while using termination resistor.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
440BX AGPset
Figure Dual Ended Termination (DET)
topologies (see Figure installed with processor termination card, must less than equal 4.5". Additionally, platforms with processor installed, termination card should placed longer leg.
STATUS: steppings affected Summary Table Changes beginning this section.
A43.
Data Operand Pointer Zero After Power Reset
PROBLEM: Data Operand Pointer, specified, should reset zero upon power Reset
processor. this erratum, Data Operand Pointer nonzero after power Reset.
IMPLICATION: Software which uses Data Operand Pointer count value being zero after power Reset without first executing FINIT/FNINIT instruction will incorrect value, resulting incorrect behavior software. WORKAROUND: Software should follow recommendation Section Intel Architecture Software
Developer's Manual, Volume System Programming Guide (Order Number 243192). This recommendation states that will used, software-initialization code should execute FINIT/FNINIT instruction following hardware reset. This will correctly clear Data Operand Pointer zero.
STATUS: steppings affected Summary Table Changes beginning this section.
A44.
MOVD Following Zeroing Instruction Cause Incorrect Result
PROBLEM: incorrect result calculated after following circumstances occur:
register been zeroed with either reg, instruction reg, instruction,
PENTIUM® PROCESSOR SPECIFICATION UPDATE
value moved with sign extension into same register's lower bits; signed integer multiply performed same register's lower bits, This register then copied MMXtechnology register using MOVD instruction prior other operations sign-extended value. Specifically, sign incorrectly extended into bits 16-31 technology register. Only technology register affected this erratum. erratum only occurs when following steps occur order shown. erratum occur with intervening instructions that modify sign-extended value between steps EAX, EAX, MOVSX MOVSX byte <memory address> MOVSX MOVSX word <memory address> IMUL implicit, opcode IMUL byte <memory address> implicit, opcode IMUL (opcode IMUL word <memory address> (opcode IMUL (opcode IMUL word <memory address>, (opcode IMUL (opcode IMUL 1024 (opcode IMUL word <memory address>, 1024 (opcode IMUL 1024 (opcode MOVD MM0, Note that values immediate byte/words merely representative (i.e., 1024) that value range size affected. Also, note that this erratum occur with "EAX" replaced with 32-bit general purpose register, "AX" with corresponding 16-bit version that replacement. "BL" "BX" replaced with 8-bit 16-bit general purpose register. IMUL (opcode instructions specific register only. example, forced contain instructions. Since four types MOVSX IMUL instructions instruction modify only bits 15:8 sign extending lower bits EAX, bits 31:16 should always contain This implies that when MOVD copies MM0, bits 31:16 should also Under certain scenarios, bits 31:16 replicas (the 16th bit) This noticeable when value after MOVSX, IMUL instruction negative, i.e., When positive (bit MOVD will always produce correct answer. negative (bit MOVD produce right answer wrong answer depending point time when MOVD instruction executed relation MOVSX, IMUL instruction.
IMPLICATION: effect incorrect execution will vary from unnoticeable, code sequence discarding incorrect bits, application failure. technology-enabled application which MOVD used manipulate pixels, possible more pixels exhibit wrong color position momentarily. also possible computational application that uses MOVD instruction manner described above produce incorrect data. Note that this data cause unexpected page fault general protection fault. WORKAROUND: There possible workarounds this erratum:
Rather than using MOVSX-MOVD, IMUL-MOVD CBW-MOVD pairing handle variable time, sign extension capabilities (PSRAW, etc.) within MMXtechnology operating multiple variables. This would result higher performance well. Insert another operation that modifies copies sign-extended value between MOVSX/IMUL/CBW instruction MOVD instruction example below:
PENTIUM® PROCESSOR SPECIFICATION UPDATE
EAX, EAX, EAX) MOVSX other MOVSX, other IMUL instruction) *MOV EAX, MOVD MM0, *Note: EAX, used here fairly generic. Again, 32-bit register.
STATUS: steppings affected Summary Table Changes beginning this section.
A45.
Premature Execution Load Operation Prior Exception Handler Invocation
PROBLEM: This erratum occur with following situations:
instruction that performs memory load causes code segment limit violation, waiting floating-point instruction MMXinstruction that performs memory load floating-point exception pending, instruction that performs memory load either CR0.EM (Emulation set), floating-point Top-of-Stack TOS) equal exception pending. above circumstances occur possible that load portion instruction will have executed before exception handler entered.
IMPLICATION: normal code execution where target load operation write back memory there
impact from load being prematurely executed, from restart subsequent re-execution that instruction exception handler. target load uncached memory that system sideeffect, restarting instruction cause unexpected system behavior repetition side-effect.
WORKAROUND: Code which performs loads from memory that side-effects effectively workaround this
behavior using simple integer-based load instructions when accessing side-effect memory ensuring that code written such that code segment limit violation cannot occur part reading from side-effect memory.
STATUS: steppings affected Summary Table Changes beginning this section.
A46.
Read Portion Instruction Execute Twice
PROBLEM: When Pentium processor executes read-modify-write (RMW) arithmetic instruction, with
memory destination, possible page fault occur during execution store memory operand after read operation completed before write operation completes. memory targeted instruction (uncached), memory will observe occurrence initial load before page fault handler again instruction restarted.
IMPLICATION: This erratum effect memory targeted instruction side-effects. however, load targets memory region that side-effects, multiple occurrences initial load lead unpredictable system behavior. WORKAROUND: Hardware software developers write device drivers custom hardware that have side-effect style design should simple loads simple stores transfer data from device. Then, memory location will simply read twice with additional implications. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A47.
Test Must High During Power
PROBLEM: processor uses PWRGOOD signal ensure that voltage sequencing issues arise; assertions should cause processor change behavior until this signal asserted, when power supplies clocks processor valid stable. However, TESTHI signal voltage level when core power supply comes will cause processor enter invalid test state. IMPLICATION: this erratum occurs, system boot normally however, cache initialized. WORKAROUND: Ensure that (VCC2.5) power supply ramps before (VCCCORE) power plane. ramps after core, pull TESTHI (VCC2.5) with 100K resistor. internal pull-up will keep signal from being asserted during power motherboard designs, recommended that TESTHI pulled (VCCCORE) using 1K-10K resistor. STATUS: steppings affected Summary Table Changes beginning this section.
A48.
Intervening Writeback Occur During Locked Transaction
PROBLEM: During transaction which LOCK# signal asserted (i.e., locked transaction), there potential explicit writeback caused previous transaction complete while locked. explicit writeback will only issued processor which locked bus, lock signal will deasserted until locked transaction completes, atomicity lock compromised this erratum. Note that explicit writeback expected cycle, memory ordering violations will occur. This erratum however, violation lock protocol. IMPLICATION: chipset third-party agent (TPA) which tracks transactions such that locked
transactions only consist read-write read-read-write-write locked sequence, with transactions intervening, lose synchronization state intervening explicit writeback. Systems using chipsets TPAs which accept intervening transaction will affected.
WORKAROUND: tracking logic devices system should allow occurrence intervening transaction during locked transaction. STATUS: steppings affected Summary Table Changes beginning this section.
A49.
MC2_STATUS Model-Specific Error Code Machine Check Architecture Error Code Reversed
PROBLEM: Intel Architecture Software Developer's Manual, Volume System Programming Guide,
documents that MCi_STATUS MSR, bits 15:0 contain (machine-check architecture) error code field, bits 31:16 contain model-specific error code field. However, MC2_STATUS MSR, these bits have been reversed. MC2_STATUS MSR, bits 15:0 contain model-specific error code field bits 31:16 contain error code field.
IMPLICATION: machine check error decoded incorrectly this erratum MC2_STATUS
taken into account.
WORKAROUND: When decoding MC2_STATUS MSR, reverse error fields. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A50.
Mixed Cacheability Lock Variables Problematic Systems
PROBLEM: This errata only affects multiprocessor systems where lock variable address marked cacheable
processor uncacheable others. processors which have marked uncacheable stall indefinitely when accessing lock variable. stall only encountered processor lock variable cached, attempting execute cache lock. processor which that address cached cached only. Other processors, meanwhile, issue back back accesses that same address bus.
IMPLICATION: systems where processors either cache locks consistent locks uncacheable
space will encounter this problem. however, lock variable's cacheability varies different processors, several processors attempting perform lock simultaneously, indefinite stall experienced processors which have marked uncacheable locking variable conditions above satisfied). Intel only encountered this problem focus testing with artificially generated external events. Intel currently identified commercial software which exhibits this problem.
WORKAROUND: Follow homogenous model memory type range registers (MTRRs), ensuring that
processors have same cacheability attributes each region memory; locks whose memory type cacheable processor, uncacheable others. Avoid page table aliasing, which produce nonhomogenous memory model.
STATUS: steppings affected Summary Table Changes beginning this section.
A51.
With Debug Register Causes Debug Exception
PROBLEM: When mode, instruction executed debug registers, general-protection exception (#GP) should generated, documented Intel Architecture Software Developer's Manual, Volume System Programming Guide, Section 14.2. However, case when general detect enable flag (GD) set, observed behavior that debug exception (#DB) generated instead. IMPLICATION: With debug-register protection enabled (i.e., set), when attempting execute
debug registers mode, debug exception will generated instead expected general-protection fault.
WORKAROUND: general, operating systems when they mode.
generally used debuggers. debug exception handler should check that exception occur mode before continuing. exception occur mode, exception directed general-protection exception handler.
STATUS: steppings affected Summary Table Changes beginning this section.
A52.
Upper Four Entries Usable With Mode Mode Paging
PROBLEM: Page Attribute Table (PAT) contains eight entries, which must initialized considered when setting memory types Pentium processor. However, Mode Mode paging, upper four entries function correctly 4-Kbyte pages. Specifically, seven page table entries that translate addresses 4-Kbyte pages should used upper three-bit index determine entry that specifies memory type page. When Mode (CR4.PSE and/or Mode (CR4.PAE) enabled, processor forces this zero when determining memory type regardless value page table entry. upper four entries function correctly 2-Mbyte 4-Mbyte large pages (specified page directory entry those translations).
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: Only lower four entries useful translations when Mode paging used. Mode paging (4-Kbyte pages only), eight entries used. eight entries used large pages Mode paging. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
A53.
Write Reordered Around Cacheable Write
PROBLEM: After write occurs (uncacheable) region memory, there exists small window opportunity where subsequent write transaction targeted memory region reordered front write targeted region cacheable memory. This erratum only occur during following sequence transactions:
write memory mapped occurs, write memory mapped cacheable which present Shared Invalid state cache occurs, During snoop cacheable line, another store memory occurs.
IMPLICATION: this erratum occurs, second write will observed prior Invalidate
Line (BIL) Read Invalidate Line (BRIL) transaction cacheable write. This presents small window opportunity fast bus-mastering device which triggers action based second write arbitrate gain ownership prior completion cacheable write, possibly retrieving stale data.
WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A54.
Incorrect Memory Type Used When MTRRs Disabled
PROBLEM: Memory Type Range Registers (MTRRs) disabled without setting CR0.CD disable caching, Page Attribute Table (PAT) entries left their default setting, which includes memory type (PCD Addendum-Intel Architecture Software Developer's Manual, Volume System Programming Guide, details), data entries will cached memory type were writeback (WB). Also, page tables memory type other than UC-, then effective memory type used will that specified page tables PAT. regions memory normally forced MTRRs (such video region) incorrectly cached speculatively accessed.
Even CR0.CD correctly when MTRRs disabled left default state, then retries order retirement accesses occur, contrary strong ordering expected these transactions.
IMPLICATION: occurrence this erratum result incorrect data unpredictable processor behavior when running with MTRRs disabled. Interaction between mouse, cursor, video display leading video corruption occur symptom this erratum well. WORKAROUND: Ensure that when MTRRs disabled, CR0.CD disable caching. This
recommendation described Intel Architecture Software Developer's Manual, Volume System Programming Guide. necessary disable MTRRs, first clear register before setting CR0.CD bit, flushing caches, disabling MTRRs ensure that memory type always returned strong ordering maintained.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A55.
Misprediction Program Flow Cause Unexpected Instruction Execution
PROBLEM: optimize performance through dynamic execution technology, architecture ability predict program flow. event misprediction, processor will normally clear incorrect prediction, adjust correct location, flush instructions have fetched from misprediction. circumstances where branch misprediction occurs, correct target branch already been opportunistically fetched into streaming buffers, cycle caused evicted cache line retried cache, processor fail flush retirement unit before speculative program flow committed permanent state. IMPLICATION: results this erratum range from effect unpredictable application failure. Manifestations this failure result
Unexpected values EIP, Faults traps (e.g., page faults) instructions that normally cause faults, Faults middle instructions, Unexplained values registers/memory correct EIP.
WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
A56.
System Report False Errors
PROBLEM: processor's circuitry fail meet frequency timing specification under certain environmental conditions. high temperature specification and/or voltage range, processor report false errors. IMPLICATION: system data error checking enabled (bit EBL_CR_POWERON register "1") Machine Check Architecture enabled, spurious double error detection occur causing Machine Check Exceptions (MCE) spurious single errors occur logged. Under some circumstances processor assert BINIT#, which turn, cause some systems generate MCE, others cause reboot. WORKAROUND: Disable system data error checking (set EBL_CR_POWERON register "0"). STATUS: processor part numbers affected "Pentium® Processor Identification Information"
table General Information section.
A57.
Full In-Order Queue Cause Infinite DBSY# Assertion
PROBLEM: this erratum occur, there must high rate code fetches from core cache, which must cache, parallel externally generated read transaction that hits modified line FOLLOWED consecutive length external transactions rapid succession FOLLOWED another external transaction that also hits modified line. IMPLICATION: writeback data transferred memory. further transactions issued because In-Order Queue full. WORKAROUND: None Identified. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A58.
Data Breakpoint Exception Displacement Relative Near Call Corrupt
PROBLEM: data breakpoint programmed memory location where stack push near call performed, processor will update stack appropriately, skip code destination call. Hence, program execution will continue with next instruction immediately following call, instead target call. IMPLICATION: failure mechanism this erratum that call would taken; therefore, instructions
called subroutine would executed. result, code relying execution subroutine will behave unpredictably.
WORKAROUND: program data breakpoint exception stack where push near call
performed.
STATUS: steppings affected Summary Table Changes beginning this section.
A59.
System Functional With Ratio
PROBLEM: processor underclocked core frequency system frequency ratio system enabled, system detection correction will negatively affect internal timing dependencies. IMPLICATION: system enabled, processor underclocked ratio, system behave unpredictably these timing dependencies. WORKAROUND: agents that support system must disable when ratio used. STATUS: steppings affected Summary Table Changes beginning this section.
A60.
Fault CMPS/SCAS Operation Cause Incorrect
PROBLEM: either General Protection Fault, Alignment Check Fault Machine Check Exception occur during first iteration CMPS SCAS instruction, incorrect pushed onto stack event handler following conditions true:
event occurs initial load performed instruction(s), condition zero flag before repeat instruction happens opposite repeat condition (i.e., REP/REPE/REPZ CMPS/SCAS with RENE/REPNZ CMPS/SCAS with faulting micro-op particular micro-op instruction retired retirement unit specific sequence.
will point instruction following CMPS/SCAS instead pointing faulting instruction.
IMPLICATION: result incorrect range from effect unexpected application/OS behavior. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
A61.
RDMSR WRMSR Invalid Address Cause Fault
PROBLEM: RDMSR WRMSR instructions allow reading writing MSRs (Model Specific Registers)
based index number placed ECX. processor should reject access reserved unimplemented MSRs generating #GP(0). However, there some invalid addresses which processor will generate #GP(0).
IMPLICATION: RDMSR, undefined values will read into EDX:EAX. WRMSR, undefined processor
behavior result.
WORKAROUND: invalid addresses with RDMSR WRMSR. STATUS: steppings affected Summary Table Changes beginning this section.
A62.
SYSENTER/SYSEXIT Instructions Implicitly Load "Null Segment Selector" Registers
PROBLEM: According processor specification, attempting load null segment selector into segment registers should generate General Protection Fault (#GP). Although loading null segment selector other segment registers allowed, processor will generate exception when segment register holding null selector used access memory.
However, SYSENTER instruction implicitly load null value segment selector. This occur value SYSENTER_CS_MSR between FFF8h FFFBh when SYSENTER instruction executed. This behavior part SYSENTER/SYSEXIT instruction definition; content SYSTEM_CS_MSR always incremented before loaded into This operation will null segment selector null result generated, does generate SYSENTER instruction itself. exception will generated expected when register used access memory, however. SYSEXIT instruction will also exhibit this behavior both when executed with value SYSENTER_CS_MSR between FFF0h FFF3h, between FFE8h FFEBh, inclusive.
IMPLICATION: These instructions intended operating system use. this erratum occurs (and does ensure that processor never null segment selector segment registers), processor's behavior become unpredictable, possibly resulting system failure. WORKAROUND: initialize SYSTEM_CS_MSR with values between FFF8h FFFBh, FFF0h FFF3h, FFE8h FFEBh before executing SYSENTER SYSEXIT. STATUS: steppings affected Summary Table Changes beginning this section.
A63.
PRELOAD Followed EXTEST Does Load Boundary Scan Data
PROBLEM: According IEEE 1149.1 Standard, EXTEST instruction would data "typically loaded onto latched parallel outputs boundary-scan shift-register stages using SAMPLE/PRELOAD instruction prior selection EXTEST instruction." result this erratum, this method cannot used load data onto outputs. IMPLICATION: Using PRELOAD instruction prior EXTEST instruction will produce expected data
after completion EXTEST.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A64.
Jump With D-bit Cleared Cause System Hang
PROBLEM: task switch performed executing jump through task gate Task State Segment (TSS) directly. Normally, when such jump occurs, D-bit (which indicates that page referenced Page Table Entry (PTE) been modified) which maps location previous will already set, processor will operate expected. However, D-bit clear time jump TSS, processor will hang. IMPLICATION: used which clear D-bit system pages, which jumps
task switch, then condition occur which results system hang. Intel identified commercial software which encounter this condition; this erratum discovered focused testing environment.
WORKAROUND: Ensure that code does clear D-bit system pages (including pages that contain task gate TSS). task gates rather than jumping when performing task switch. STATUS: steppings affected Summary Table Changes beginning this section.
A65.
Incorrect Chunk Ordering Prevent Execution Machine Check Exception Handler After BINIT#
PROBLEM: catastrophic error detected which results BINIT# assertion, BINIT# assertion
propagated processor's cache same time that data being sent processor, then data become corrupted processor's cache.
IMPLICATION: Since BINIT# assertion catastrophic event bus, corrupted data will used. However, prevent processor from executing Machine Check Exception (MCE) handler, causing system hang. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
A66.
Resume Flag Cleared After Debug Exception<br
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