LXT307 Low-Power Integrated Short-Haul Transceiver General D
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LXT307
Low-Power Integrated Short-Haul Transceiver
General Description
LXT307 fully integrated low-power transceiver optimized G.703 2.048 Mbps (E1) applications. features constant output impedance transmitter allowing high transmitter return loss. Transmit pulse amplitudes selectable various cable types. designed exceed latest international specifications, including G.775 166. LXT307 microprocessor controllable through serial interface. also controlled through individual pins Hardware Mode. LXT307 offers variety diagnostic features, including transmit receive monitoring. device requires single 2.048 clock reference chip high performance clock recovery system. uses advanced double-poly, double-metal CMOS process requires only single 5-volt power supply.
APRIL, 1996
PEAK DETECTOR RTIP RRING
Features
power dissipation typical Constant output impedance transmitter regardless data pattern typical) speed reference clock reduce board noise coupling Driver short circuit current limited OFTEL/BABT recommendations 75/120 Operation without component changes Transmit receive return loss exceeds ETSI G.703 Meets exceeds specifications including G.703, G.823 (03/93) G.775 Compatible with most popular framers Line driver, data recovery clock recovery functions Minimum receive signal Programmable transmit amplitude operation without component changes Local remote loopback functions Transmit performance monitor with detecting single line shorts improved reliability Analog/digital monitor G.775 Receiver jitter tolerance from Serial Control Interface Available 28-pin PLCC
Applications
G.703 Interfaces multiplexer Digital Access Cross-connect Systems (DACS) G.703 Trunk line cards Public Switching Systems PABX High-speed data transmission lines
LXT307 Block Diagram
MODE
HOST
CONTROL TPOS TNEG TCLK LOCAL LOOPBACK MCLK RCLK REMOTE LOOPBACK INTRNL GENERATOR EQUALIZER SYNCHRONIZER TRANSMIT DRIVER PERFORMANCE MONITOR
SCLK CLKE
-RLOOP LLOOP TAOS
LINE DRIVER TTIP TRING MTIP MRING
TIMING RCVRY
RPOS RNEG
DATA LATCH LOSS SIGNAL MONITOR
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LXT307 Low-Power Integrated Short-Haul Transceiver Figure Assignments
MCLK TCLK TPOS TNEG MODE RNEG RPOS RCLK LXT307PE CLKE/TAOS SCLK/LLOOP CS/RLOOP
MCLK TCLK TPOS TNEG MODE RNEG RPOS RCLK TTIP TGND
CLKE/TAOS SCLK/LLOOP CS/RLOOP SD0/GND SDI/GND INT/EC RGND RRING RTIP MRING MTIP TRING
SDO/GND SDI/GND INT/EC RGND RRING RTIP
LXT307NE
28-pin
TTIP TGND
28-pin PLCC
MRING MTIP TRING
Table Assignments Signal Descriptions
MCLK TCLK TPOS TNEG MODE I/O1 Description Master Clock. 2.048 clock input used generate internal clocks. Upon Loss Signal (LOS), RCLK derived from MCLK. Transmit Clock. Transmi clock input. TPOS TNEG sampled falling edge TCLK. TCLK supplied, transmitter remai powered down. Transmit Positive Data. Input positive pulse transmitted line. Transmit Negative Data. Input negative pulse transmi tted line. Mode Select. Setti MODE High puts LXT307 Host Mode. Host Mode, serial interface used control LXT307 determine status. Setti MODE puts LXT307 Hardware (H/W) mode. Hardware mode serial interface disabled hard-wired pins used control configurati report status. Receive Negative Data; Receive Positive Data. Recei data outputs. signal RNEG corresponds receipt negative RTIP RRING. signal RPOS corresponds receipt positi RTIP RRING. RNEG RPOS outputs Non-Return-to-Zero (NRZ). Host mode, CLKE determi clock edge which these outputs stable Hardware mode, both outputs stable valid rising edge RCLK. Recovered Clock. This clock recovered from signal received RTIP RRING. Resistor Termination. Connect through resistor.
RNEG RPOS
RCLK
Entries are: Digital Input; Digital Output; Analog Input; Analog Output; Supply.
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LXT307 Low-Power Integrated Short-Haul Transceiver Table Assignments Signal Descriptions continued
I/O1 connection. Driver Performance Monitor. goes High when transmit monitor (MTIP MRING) does detect signal 63±2 clock periods. remains High until signal detected. reset transition MTIP MRING. Loss Signal. goes High when signal falls below nominal more than consecutive periods. returns when recei signal detects transiti 32-bit window (12.5% density) with more than consecuti Transmit Tip; Transmit Ring. Differential Outputs. These low-impedance outputs achieve return loss with resistors used series with transformer specified Tables Transmit Ground. Ground return transmit vers power supply TV+. Transmit Power Supply. power supply input transmi vers. must vary from more than ±0.3 during operating conditi including start-up. Monitor Tip; Monitor Ring. These pins used moni TTIP TRING transmit outputs. transcei connected monitor output output another LXT307 board. prevent false interrupts host mode moni used, apply clock signal monitor pins other moni approximately clock's midrange voltage. monitor clock range from TCLK frequency. Receive Tip; Receive Ring. signal recei from line applied these pins. center-tapped, center-grounded, step-up transformer required these pins. Data clock from signal applied these pins recovered output RPOS/RNEG RCLK pins. Receive Power Supply. power supply circuits except transmi vers. (Transmit drivers supplied TV+.) Receive Ground. Ground return power supply RV+. Interrupt (Host Mode). This LXT307 Host mode output goes host processor when active. open-drain output shoul tied power supply through resistor. reset clearing respective register (LOS and/or DPM). Equalizer Control (H/W Mode). signal applied this LXT307 Hardware mode used determine amplitude output transmit pulses. Serial Data (Host Mode). serial data input stream applied this when LXT307 operates Host mode. sampled rising edge SCLK. (H/W Mode). Signal ground. Serial Data (Host Mode). serial data from on-chip register output LXT307 Host mode. CLKE High, valid rising edge SCLK. CLKE Low, ling edge SCLK. goes high-impedance state when serial port tten when High. (H/W Mode). Signal ground. Description
TTIP TRING TGND MTIP MRING
RTIP RRING RGND
Entries column are: Digital Input; Digi Output; Analog Input; Analog Output; Suppl
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LXT307 Low-Power Integrated Short-Haul Transceiver Table Assignments Signal Descriptions continued
I/O1 Description Chip Select (Host Mode). This input used access serial interface LXT307 Host mode. each read write operation, must transition from High Low, remain Low. Remote Loopback (H/W Mode). This input controls loopback functi LXT307 Hardware mode. Setting RLOOP logi enables Remote Loopback mode. Setting both RLOOP LLOOP High causes Reset. Serial Clock (Host Mode). clock used LXT307 Host mode data read data from serial interface registers. Local Loopback (H/W Mode). This input controls loopback functions LXT307 Hardware mode. Setting LLOOP High enables Local Loopback Mode. Clock Edge (Host Mode). Setti CLKE High causes RPOS RNEG ling edge RCLK, rising edge SCLK. When CLKE Low, RPOS RNEG valid rising edge RCLK, valid ling edge SCLK. Transmit Ones (H/W Mode). When High, TAOS causes LXT307 (Hardware mode) transmi continuous stream marks TCLK frequency. Activating TAOS causes TPOS TNEG inputs ignored. TAOS inhibited duri Remote Loopback.
RLOOP
SCLK LLOOP
CLKE
TAOS
Entries are: Digital Input; Digital Output; Analog Input; Analog Output; Supply.
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LXT307 Low-Power Integrated Short-Haul Transceiver
FUNCTIONAL DESCRIPTION
NOTE This functi onal informati design only. LXT307 fully integrated transceiver G.703 2.048 Mbps (E1) applications. simplified block diagram transceiver appears page LXT307 lows full-duplex transmission digital data over existing twisted-pair coax instal lations. interfaces lines, receive, transmit.
samples nputs determines maximum recei signal. percentage peak value provided data slicers threshold level ensure optimum signal-to-noise ratio. threshold ntained over whole input range. recei capable accurately recovering signals with -13.6 attenuation (from corresponding received signal level approximately Regardless received signal level, peak detectors held above minimum level provi immunity from mpul sive noise. After processing through data slicers, recei signal routed data clock recovery sections, recei monitor. data clock recovery circuits highl tolerant with input jitter tolerance signi ficantly better than required G.823, shown Figure Recovered clock signal supplied data latch. Recovered data output RPOS RNEG, recovered clock output RCLK. Refer Table Figure LXT307 receiver timing.
POWER REQUIREMENTS
LXT307 low-power CMOS device. operates from single power supply connected externally both transmitter receiver. However, inputs must ±0.3 each other, decoupled separately their respecti grounds. Isolation between transmit recei circui provided internally. During normal operation, LLOOP, transmi tter powers down TCLK supplied. transmitter powers down duri TAOS operati TCLK supplied.
RESET OPERATION
Upon power transceiver held stati unti power supply reaches approximately Upon crossing this threshold, device begins reset cycle calibrate transmit recei delay lines locks Phase Lock Loop receive line. reference clock required calibrate lines transmitter reference provi TCLK. MCLK used receiver reference clock. transceiver reset from Host Hardware mode. Host mode, reset commanded simultaneously ting RLOOP LLOOP register. Hardware mode, reset commanded holding RLOOP LLOOP high simultaneously Reset initiated falling edge reset request. ther mode, reset clears sets regi sters then calibration begi
LOSS SIGNAL PROCESSOR Declaring Condition
Recommendation G.775 defines basic teria detecti clearance Loss Signal (LOS) defects. LXT307 uses digital-and-analog detection scheme comply G.775. signal level falls below typical, LXT307 begins count consecuti times declares after approximately (160 190) consecutive zeros. Refer Table
Clearing Condition
LXT307 clears with three-step process: signal must first exceed signal level. Then 32-bit repeati window checks 12.5% density. meet parameter, there must least four bits window.) Final there must more than consecutive clear condition.
RECEIVER
LXT307 receives signal input from line each side center-grounded transformer. Positi pulses received RTIP negative pulses received RRING. signal received RTIP RRING processed through peak detector data slicers. peak detec-
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LXT307 Low-Power Integrated Short-Haul Transceiver TRANSMITTER
Data recei transmi ssion onto line clocked serial into device TPOS TNEG. Input synchronization supplied transmit clock (TCLK). TCLK supplied, transmitter remains powered down, except during remote loopback TAOS. Refer Table Figure master transmi clock timing characteristics. line provides constant output impedance (typical). This well-controlled output impedance provides excellent return loss when used with external precision resistors (±1% accuracy) seri with transmit transformer. Series resistors also provide increased surge protection reduce short circuit current Pulses drive coaxial shiel sted-pai lines. transmit transformer seri resistors recommended. This design meets exceeds ETSI European specificati transmit receive return loss when series resistors used.
Line Code
LXT307 transmits data line code shown Figure output driver maintai constant output impedance under dynamic conditi regardless whether driving marks spaces. transmitted pulse amplitude determined equalizer control signal shown Table equalizer control signal hardwi Hardware mode input part serial data stream (SDI) Host mode. Shaped pulses applied line driver transmi ssion onto line TTIP TRING.
Figure Coding
CELL TTIP
TRING
Table G.775 Requirements LXT307 Implementation Detection
Condition Detect G.775 Recommendation Signal with transitions1 less than equal signal level nomi consecutive interval where 255. Signal transiti ons1 level greater than equal below nominal consecutive pulse intervals where 255. Level Implementation Signal level below consecutive transition (typical 175) pulse intervals. Signal level above density greater than 12.5% 32-bit positions, with fewer than consecutive zeros.
Clear
signal with "transitions" corresponds G.703 compliant signal.
Table Equalizer Control Inputs Pulse Amplitude Selection
Line Length Cable Loss Recommendation G.703 Recommendation G.703 Application Coax sted-Pair (120
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LXT307 Low-Power Integrated Short-Haul Transceiver DRIVER PERFORMANCE MONITOR
transceiver incorporates advanced Performance Monitor (DPM) that connected parallel with TTIP TRING output transformer. circuitry uses four comparators discriminator filter glitches. output level goes High upon detecti consecutive zeros, cleared when transition detected transmit line when reset command received. output also goes High indicate signal line short ground TTIP TRING. ground fault induced flag automatical cleared when ground condition corrected (chi reset requi red). required each subsequent access Host mode registers. responds writi incoming serial word from into command register. Figure shows write operation. 16-bit serial word consists 8-bit Command/Address byte 8-bit Data byte. command word contains read request, subsequentl outputs contents status register onto pin. Figure shows read operation. Clock Edge (CLKE) signal determines when recei data outputs relative Serial Clock (SCLK) RCLK listed Table Table Figures show ming. SERIAL INPUT WORD Figure shows Serial Input data structure. LXT307 addressed setting Address/Command byte, corresponding address serial Address/Command byte provides Read/Write (R/W) control when chip accessed. logic read data output byte from chip, logic write input data byte chip. second eight bits write operation, clear Loss Signal (LOS) Driver Performance Monitor (DPM) interrupts, reset control diagnosti modes. first bits clear and/or mask interrupts. last three bits control operati modes (normal diagnostic) reset. Refer Table details bits SERIAL OUTPUT WORD Figure shows Seri Output data structure. high impedance when receives Address/Command byte. receives read command (R/W then becomes active after last Command/Address (A6) remains active eight SCLK cycles. Typical first changes state from gh-Z Low/High. first bits (D0-D4) output data byte reports Loss Signal (LOS) Driver Performance Monitor (DPM) conditions, equalizer settings, operati modes (normal diagnostic). last three bits through report operating modes interrupt status. line High interrupt pending), bits through report status operating mode listed Table line Low, interrupt status overrides other reports bits reflect interrupt status listed Table
OPERATING MODES
LXT307 transceiver controlled through hardwired pins (Hardware Mode-defaul microprocessor through serial interface (Host Mode) depending input (MODE). mode operation MODE logic level. LXT307 also commanded operate several diagnosti modes.
Hardware Mode Operation
Hardware mode transceiver controlled through individual pins. exception CLKE functions, Hardware mode provides functions provided Host mode. Hardware mode RPOS RNEG outputs valid rising edge RCLK. operate Hardware mode, MODE must Diagnostic Control Remote Loopback (RLOOP), Local Loopback (LLOOP), Transmit (TAOS) modes provided through individual pins. MODE Low, LXT307 operates Hardware Mode. Hardware Mode transcei controlled through individual pins; microprocessor required. RPOS RNEG valid sing edge RCLK. equalizer controlled through (EC). Diagnostic control Remote Loopback (RLOOP), Local Loopback (LLOOP), Transmit (TAOS) provided through pins
Host Mode Control
LXT307 operates Host mode when (MODE) asserted Host mode microprocessor controls LXT307 through serial port (SIO) provides access LIU. contains pair data regi sters, command inputs status outputs. transaction initi ated falling edge Chip Select pin. gh-to-Low transition
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LXT307 Low-Power Integrated Short-Haul Transceiver Interrupt Handling
Host mode provides latched Interrupt output pin, INT. change bits output data byte, respecti vely) triggers interrupt. shown Figure writing respective input data byte LOS, DPM) masks either both nterrupt generators. When interrupt occurred output Low. output stage consists ldown devi Hence, external pull-up resistor requi red. clear interrupt follows: both interrupt bits (LOS DPM, output data byte) writi input respectively), input data byte will clear nterrupt. Leaving either these positions will effectively mask associ ated nterrupt. re-enabl nterrupt capabi lity, reset and/or neither interrupt will cleared resetting reset chip, data input bits
Table CLKE Settings
CLKE HIGH Output RPOS/RNEG RPOS/RNEG Clock RCLK SCLK RCLK SCLK Valid Edge Rising ling ling Rising
Table Input Settings
(see Figure
Mode RLOOP LLOOP LLOOP TAOS TAOS RESET RLOOP LLOOP TAOS
Table Serial Data Output Coding
Status Reset occurred, program input. (i.e., normal operation) TAOS acti Local Loopback acti TAOS Local Loopback active. Remote Loopback active. Interrupt Status changed state since last clear occurred. changed state since last clear occurred. have both changed state since last clear clear occurred.
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LXT307 Low-Power Integrated Short-Haul Transceiver Figure LXT307 Write Operation
SCLK ADDRESS/COMMAND BYTE DATA INPUT BYTE
Remains High Impedance ADDRESS/ COMMAND BYTE
DON'T CARE
CLEAR MASK INTERRUPTS INPUT DATA BYTE
MODE OPERATION RESET
(LSB) CLEAR
CLEAR
TAOS RLOOP LLOOP (MSB) ENABLE ENABLE ENABLE
Figure LXT307 Read Operation
SCLK ADDRESS/COMMAND BYTE DATA OUTPUT BYTE
SDI/SDO
ADDRESS/ COMMAND BYTE
CLEAR INTERRUPTS OUTPUT DATA BYTE
REFER TABLE
(LSB)
RLOOP LLOOP
TAOS
(MSB)
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LXT307 Low-Power Integrated Short-Haul Transceiver Figure LXT307 Interrupt Handling
Start-up Restart Interrupts Enabled
Mask Interrupts
Does High Interrupt interrupt) Condition Exist (interrupt) Read Output Status Read Output Status Word* Word* (Bits D5-D&=Operating (Bits D5-D7=Operating) Mode) *Regardless Interrupt Status, What indicates status, Interrupt indicates Condition status Exists indicates status. Write Input Status Word Mask Interrupt. Write D0-D1 Input Status Word Mask Interrupt. Write Input Status Word Mask Interrupt.
Mask Which Interrupts
Write Input Status Word Mask Interrupt Write D0-D1 Input Status Word Mask Interrupt Write Input Status Word Mask Interrupt
Both Interrupt Conditions Masked
goes HIGH.
Read Output Status Word* (Bits D5-D7=Operating Mode)
*Regardless Interrupt Status, indicates status, indicates status indicates status.
Reenable Interrupts What Interrupt Condition Exists?
Write Input Status Word re-enable Interrupt. Write D0-D1 Input Status Word re-enable Interrupt. Write Input Status Word re-enable Interrupt.
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LXT307 Low-Power Integrated Short-Haul Transceiver Diagnostic Mode Operation
TAOS Figures Transmit Ones (TAOS) mode, TPOS TNEG nputs transceiver ignored. transceiver transmits conti nuous stream TCLK frequency when TAOS activated. TAOS commanded simultaneously with Local Loopback, inhi bited during Remote Loopback. LLOOP Figure Local Loopback (LLOOP) mode, receiver circui inhibited. transmit data clock inputs (TPOS, TNEG TCLK) looped back onto receive data clock outputs (RPOS, RNEG RCLK). transmitter circuits unaffected. TPOS TNEG inputs stream TAOS command acti transmi tted normal
Figure Local Loopback
Local Loopback LLOOP High RLOOP TAOS
Figure TAOS
Transmit Ones LLOOP RLOOP TAOS High
ENCODER
ENCODER
TTIP TRING
(All
RCLK RPOS RNEG
DECODER
TAOS TCLK TPOS TNEG RCLK RPOS RNEG
TCLK TPOS TNEG
Timing Control Timing Recovery
TTIP TRING RTIP RRING
Timing Control Timing Recovery
DECODER
RTIP RRING
RLOOP
Figure TAOS with LLOOP
Transmit Ones LLOOP TAOS TCLK TPOS TNEG RCLK RPOS RNEG LLOOP High RLOOP TAOS High
ENCODER
Timing Control Timing Recovery
TTIP TRING
(All
Figure Remote Loopback (RLOOP) mode, transmit data clock inputs (TPOS, TNEG TCLK) ignored. RPOS RNEG outputs looped back through transmit circuits output TTIP TRING RCLK frequency. Receiver circui unaffected RLOOP command continue output RPOS, RNEG RCLK signals received from sted-pai line.
DECODER
Figure Remote Loopback
Remote Loopback=
ENCODER
RTIP RRING
RCLK RPOS RNEG
DECODER
LLOOP
RLOOP High
TAOS TTIP TRING RTIP RRING
TCLK TPOS TNEG
Timing Control Timing Recovery
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LXT307 Low-Power Integrated Short-Haul Transceiver
APPLICATION INFORMATION
NOTE This application information design only. Figure 2.048 Mbps Twisted-Pair Wire application using code resistors line with transmit transformer provide high return loss surge protection. When high return loss critical
factor, transformer without in-line resistors provides maximum power savings. Tables list typical return loss figures various transformer ratios, values associated code coax twistedpair applications, respectively. LXT307 shown Hardware mode with general G.704 Framer. hardwired control lines TAOS, LLOOP RLOOP individually controllable, LLOOP RLOOP lines also tied single control Reset function.
Figure LXT307 Application (Hardware Mode)
E1/CRC4 FRAMER 2.048 Clock
MCLK TCLK TPOS TNEG TCLK TPOS TNEG MODE RNEG RPOS RCLK
LXT307
TRANSCEIVER TAOS LLOOP RLOOP RGND
RNEG RPOS RCLK
RRING RTIP MRING
1:1:1 2.048 Mbps RECEIVE
MTIP
0.47
NOTE: required series resistor used. Typical value adjust actual board parasitics obtain optimum return loss.
TTIP TGND
TRING
2.048 Mbps TRANSMIT
2-102
LXT307 Low-Power Integrated Short-Haul Transceiver COAXIAL APPLICATIONS
Figure shows line interface typical coaxi application. code should coax. With resistors line with output transformers, LXT307 produces 2.37 peak required coax applications. transformer used recei side.
Table Output Combinations
Xfmr Ratio1
Value2 14.3
Loss3
Table Transformer Specifications
Parameter Turns Rati Primary Inductance Leakage Inductance Interwi nding Capacitance Series Resistance Value (±2%)
Transformer turns rati accuracy ±2%. values ±1%. Typi return loss, 3.0728 kHz. required seri resistor used.
Table Output Combinations
Xfmr Ratio1 Value2 Loss3
Table Transformer Selection Guide
Transformer Manufacturer Pulse Engi neering Part Number PE65861 65351 0553-5006 67127370 671-5832 Turns Ratio Description Dual Single through hole Dual Single through hole Single through hole
Fuse Schott Midcom
Transformer turns rati accuracy ±2%. values ±1%. Typi return loss, 3.0728 kHz. required seri resistor used.
Figure Line Interface Coax Applications
Rt=9.1 TTIP
TRING LXT307 RTIP RRING
Rt=9.1 Rr=150 1:1:1
Rr=150
2-103
LXT307 Low-Power Integrated Short-Haul Transceiver
TEST SPECIFICATIONS
NOTE mini maximum Tables through Figures through represent performance specificati LXT307 guaranteed test, except where noted design.
Table Absolute Maximum Ratings
Parameter Supply (referenced GND) Input Voltage, pin1 Input Current, pin2 Storage Temperature RV+, TSTG CAUTION
Operations beyond these limits result permanent ice. Normal operation guaranteed these tremes.
Excluding RTIP RRING which must stay between (RV+ 0.3) Transient currents will cause latch TTIP, TRING, TGND withstand continuous current
RGND
Units
Table
Recommended Operating Conditions Characteristics
Parameter RV+, 4.75 5.25 Units
Supply
Ambient Operati Temperature
must exceed more than
Table Electrical Characteristics (Over recommended operating conditions)
Parameter Total power dissipati on1, Total power consumption3
T.B.D.
Units
Test Conditions density 100% density
level input voltage (pins 1-5, level input voltage4 (pins 1-5,
level output voltage
(pins 6-8,
-400
level output voltage4, (pins 6-8, Input leakage current6 Three-state leakage current (pin
Device power dissi pation while driving load over operating temperature range. Digital input levels within supply rails digital outputs capacitive load. transformer ratio 1:1. Guaranteed design other correlation methods. Power consumption while drivi effective load. Includes device load. transformer ratio 1:2; Functionality depends mode. Host/Hardware Mode Descriptions. Output drivers will output CMOS logic levels into CMOS loads. Except MTIP MRING
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LXT307 Low-Power Integrated Short-Haul Transceiver Table Analog Characteristics (Over recommended operating conditions)
Parameter Output Pulse Amplitudes Peak Voltage space 2.14 -0.237 -0.3 Typical1 2.37 +0.237 +0.3 kHz4 kHz4 kHz4 Broad Band3 Receiver sensiti vity 13.6 Receiver input impedance Signal interference ratio (FEXT)
Units peak
Test Conditions G.703 G.703
Ratio widths positive negati pulses nominal amplitude Ratio amplitudes positive negative pulses center pulse interval Recommended output load TTIP TRING Driver output impedance4 Driver short circuit current2 Jitter added transmi tter
0.025
0.01 0.025 0.025 0.050 Receive
G.823 G.823 G.823
Transmit
G.703, O.151 G.823 below nominal
Input jitter tolerance Loss Signal threshold Data decision threshold
lowable consecutive zeros before LOS4 reset transiti window
G.775 four transitions
Mini Return Loss
-2.048 2.048 3.072
Dynamic conditions G.703. Figures
Typical values measured design guaranteed subj production testi OFTEL OTR-001/BABT BS4650 with termination resistors transmi transformer test load. Input signal TCLK jitter-free. Guaranteed design other correlation methods.
2-105
LXT307 Low-Power Integrated Short-Haul Transceiver Figure 2.048 Mbps Pulse Mask Template
(244+25)
100%
(244-
NOMINAL PULSE
(244-25)
(244+244)
Table Receive Timing Characteristics (Over recommended operating conditions)
Parameter Receive clock duty cycle Receive clock width RPOS/RNEG RCLK rising setup time RCLK sing RPOS/ RNEG hold time RCLKd tSUR Typ1 Units Test Conditions
Typical values design only; they guaranteed subject production testing.
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LXT307 Low-Power Integrated Short-Haul Transceiver
Figure LXT307 Receive Clock Timing
HOST MODE CLKE
RCLK tSUR RPOS RNEG tSUR RPOS RNEG HOST MODE CLKE MODE
Figure LXT307 Transmit Clock Timing
TCLK
TPOS
Units
TNEG
Table Transmit Timing Characteristics (over recommended operating conditions)
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG Hold time MCLK MCLKt MCLKd TCLK TCLKt TCLKd tSUT Typ1 2.048 ±100 2.048
Typical values design only; they guaranteed subject production testing.
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LXT307 Low-Power Integrated Short-Haul Transceiver Table Serial Timing Characteristics (Over recommended operating conditions)
Parameter Rise digital output Fall time digital output SCLK setup time SCLK hold SCLK SCLK time SCLK rise fall time SCLK setup SCLK hold time inacti time SCLK valid SCLK falling edge rising edge high tCDH tCCH tCWH tCDV tCDZ Typ1 Units Test Conditions Load Load -400
Typical values design only; they guaranteed subject production testing.
Figure LXT307 Serial Data Input Timing Diagram
SCLK
CONTROL BYTE DATA BYTE
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LXT307 Low-Power Integrated Short-Haul Transceiver Figure LXT307 Serial Data Output Timing Diagram tCDZ SCLK tCDV
CLKE=1
tCDZ
HIGH
tCDV
CLKE=0
HIGH
Figure Typical Receiver Input Jitter Tolerance (Loop Mode)
1200 1000
LXT307 Device Jitter Tolerance Loop Mode
Jitter
G.823
1993
Slope equivalent dB/decade
Frequency
2-109
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