Three buck converters input voltage range fixed frequency Multiphase s

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Three buck converters input voltage range fixed frequency Multiphase s

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A4490 Triple Output Step-Down Switching Regulator
Three buck converters input voltage range fixed frequency Multiphase switching Independent control each converter Power-on-reset flag Internal compensation Package, small footprint
Designed provide power supply requirements printers, office automation, industrial, portable equipment, A4490 provides three high current, high performance, switching regulator outputs with independent soft start. High frequency switching allows selection inexpensive inductors small ceramic output capacitors. turn-on cycles regulators interleaved minimize stresses input capacitors reduce EMI. charge pump used provide supply driving power switches, ensuring operation very wide operating duty cycles avoiding need power-draining clamp circuits. power-on-reset circuit with user configurable delay indicates when enabled regulators specification. power-onreset flag also indicates when input voltage drops below specification, giving system controller advance warning while switchers continue operate down shutdown level. Internal diagnostics provide comprehensive protection against overloads, input undervoltages, overtemperatures.
Continued next page.
Package: 20-contact (suffix
Approximate size
Typical Application
PORZ CPOR Microcontroller Controller Logic
VBB1 VREG1 VBB2
A4490
ENB1 ENB2 ENB3
VREG2
PGND
VBB3 VREG3
4490-DS, Rev.
A4490
Triple Output Step-Down Switching Regulator
Description (continued) A4490 provided 20-contact, 0.75 nominal overall height QFN, with exposed enhanced thermal dissipation. lead (Pb) free, with 100% matte leadframe plating. Selection Guide
Part Number
A4490EES-T A4490EESTR-T
Applications include following: Photo, inkjet, portable printers Industrial Hand-held devices Portable applications
Operating Temperature Range (°C)
Packing
pieces tube 1500 pieces 7-in. reel
Absolute Maximum Ratings (reference GND)
Characteristic Load Supply Voltage LX1, LX2, Pins PORZ Pins ENBx Input Current Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VLXn IENBx TJ(max) Tstg Driven current-limited voltage source Range Notes Rating -0.3 Units
Recommended Operating Conditions
Characteristic Load Supply Voltage LX1, LX2, Pins Operating Ambient Temperature Junction Temperature Symbol VLXn Conditions operate connect supply supply. Powering Configurations section. Min. -0.7 Typ. Max. Units
Thermal Characteristics require derating maximum conditions, application information
Characteristic
Package Thermal Resistance
Symbol
Test Conditions*
4-layer based JEDEC standard
Value Units
*Additional thermal information available Allegro website.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Functional Block Diagram
Regulator
Charge Pump
Switch
VBB1 Switcher Control REG1
Bias Supply
ENB1
VBB2 ENB2 Switcher Control PORZ Block ENB3 CPOR Switcher Control PGND VBB3 REG3 REG2
Note: capacitors ceramic X5R.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Pin-out Diagram
ENB1
VBB1
VBB3
ENB2
ENB3 PGND
CPOR
VBB2
Terminal List
Number
1GND
Name GND1 ENB2 VBB22 CPOR PORZ PGND1 ENB3 VBB32 VBB12 ENB1 PAD3 Feedback REG1 Bias supply Ground Feedback REG2
PORZ
Function
Enable REG2, logic input, active high Switch node REG2 Input supply REG2 delay adjustment Power reset output, active Charge pump reservoir Charge pump capacitor terminal Charge pump capacitor terminal Ground charge pump circuitry Feedback REG3 Enable REG3, logic input, active high Switch node REG3 Input supply REG3 Input supply REG1 Switch node REG1 Enable REG1, logic input, active high Exposed enhanced thermal dissipation
PGND should connected externally. 2The three VBBx pins should connected together externally. 3Thermal should connected ground plane using thermal vias.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
ELECTRICAL CHARACTERISTICS1,2 25°C, supplied externally, unless noted otherwise
Characteristics General Quiescent Current Supply Range Quiescent Current REG1, REG2, REG3 Feedback Input Bias Current Feedback Voltage Output Voltage Regulation3 Frequency Maximum Duty Cycle Minimum Duty Cycle IBIAS VOUT DCmax DCmin 25°C, ILOAD Buck Switch On-Resistance RDS(on) 125°C, ILOAD 25°C, ILOAD 125°C, ILOAD Current Limit Threshold Soft Start Duration Logic Inputs Outputs ENBx Input Voltage ENBx Input Hysteresis ENBx Input Current PORZ Output (Open Drain) PORZ Output Leakage Current VI(hys) VPORZL IPORZH IPORZL fault asserted VPORZ fault asserted ILIM Peak current through switch with With respect target voltage VREGx IOUT -20°C 85°C VREGx IOUT -40°C 85°C -400 -2.5 -3.5 0.625 1.25 1.875 -100 ±1.5 IBBON IBBOFF ENBx high ENBx ENBx high, ILOAD current drawn feedback resistors ignored ENBx Symbol Test Conditions Min. Typ. Max. Units
Continued next page.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
ELECTRICAL CHARACTERISTICS1,2 (continued) 25°C, supplied externally, unless noted otherwise
Characteristics Power-On Reset Duration Protection VREGx Undervoltage Lockout Startup VREGx Undervoltage Lockout Shutdown VREGx Undervoltage Lockout Startup Hysteresis Undervoltage Lockout Startup Undervoltage Lockout Shutdown Undervoltage Lockout Shutdown Hysteresis Undervoltage Warning Threshold Junction Overtemperature Shutdown Junction Overtemperature Shutdown Hysteresis
1For 2Specifications
Symbol tPOR VREGUV(su) VREGUV(sd) VREGUV(suhys) VBBUV(su) VBBCPUV(su) VBBUV(sd) VBBCPUV(sd) VBBUV(sdhys) CPOR
Test Conditions
Min.
Typ.
Max.
Units %VFB %VFB
FB1, FB2, rising FB1, FB2, falling
external supply, rising External supply, rising external supply, falling External supply, falling external supply falling (forces PORZ low); switchers continue operate Temperature rising Recovery TJTSD -TJTSD(hys)
VBBCPUV(sdhys) External supply VBBUV(por) TJTSD TJTSD(hys)
input output current specifications, negative current defined coming (sourcing) specified pin. over junction temperature range -40°C 125°C assured design characterization. 3Average value relative target voltage. effects feedback resistors taken into account.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Functional Basic Operation A4490 contains three fixed frequency, buck switching converters with peak current-mode control, including slope compensation. Each converter independently turned enable inputs (EN1, EN2, EN3), which active high. When enabled, corresponding output brought-up under control soft start routine, which avoids output voltage overshoot minimizes input inrush current. output voltage typically divided down external potential divider, compared against internal reference voltage produce error signal, also known current demand signal. current signal through buck switch converted into voltage. This signal then compared against current demand signal create required duty cycle. beginning each switching cycle, buck switch turned When current signal through switch reaches level current demand signal, on-time switch terminated. next switching cycle, switch turned again cycle repeated. shared clock used define switching frequency each regulator. Each three switching cycles (REG1, REG2, REG3) phase shifted with respect another 120° attempt minimize pulsed current drawn from input filter capacitors. Under certain conditions, example conditions relatively high user-set output voltages, switching overlap between channels inevitable. Under conditions, such light loads high voltages, that cause duty cycles (DC) less than minimum value, converter enters pulse-skipping mode ensure regulation maintained. charge pump regulator provided ensure sufficient gate drive available three power switches across full input voltage range. This regulator allows operation even very wide operating duty cycles. initial power-up, internal regulator used provide bias supply on-chip control functions. Each regulator channel utilizes pulse-by-pulse current limiting event either short circuit overload. overload applied long enough, temperature rise sufficiently cause thermal shutdown circuit operate. part will auto-restart under control soft start circuit after thermal disable condition removed, assuming other conditions met. Shutdown section more information. Power Configuration A4490 supports alternative schemes providing logic supply voltage pin. addition, powered down using either pins. Powering minimize power dissipation, especially high input voltages, recommended that external supply applied input pin. Typically, this voltage derived from three regulated outputs that set-up between (VREGx). Another advantage powering externally that undervoltage lockout level lowered. maximize time switchers during power-down condition, alternative undervoltage shutdown conditions supported, depending which VDD-powering configuration been implemented. When external applied, minimum VBB, VBBUV(sd) typical. When external applied, minimum VBB, VBBCPUV(sd) typical. note caution when deriving from VREG output: during initial application VBB, internal bias supply automatically starts from internal regulator because VREG reached regulation. This means startup threshold determined VBBUV(su) (4.3 typical) because there external VDD. When VREG begun supply externally, shutdown threshold reduces VBBCPUV(sd) (3.4 typical). This assumes that VREG present. Powering Down with Referring figure each enable inputs (ENBx) held high being tied rail resistor supplied from regulator outputs. When voltage reaches minimum threshold, VBBUV(su) charge pump supply (VCP) ramps When reached minimum threshold VBBCPUV(su), soft start routines initiated (tSS) three regulator channels (VREGx). When three regulators have reached threshold, power-on-reset timer initiated. After power-on-reset period, tPOR elapsed, PORZ goes high, indicating that regulators specification.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
BBUV(su)
BBUV(por)
VBB+VCP
BBCPUV(su)
BB+5.5 BBCPUV(sd)
VREG1 VREG2 VREG3
85%FB1
85%FB2 85%FB3
PORZ
Figure Timing diagram powering down using
ENB1 ENB2 ENB3
VREG1 VREG2 VREG3
85%FB1 85%FB2 80%FB2 85%FB2
85%FB3
PORZ
tPOR
tPOR
tPOR
Figure Timing diagram powering down using
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
When voltage starts fall below undervoltage warning level, VBBUV(por) typical, PORZ flag resets. This gives advance warning system controller that voltage falling. Note that this feature only guaranteed when supplied externally. During this interval, three switchers continue operate. While falls further, supply also tends fall, which degrades drive voltage series switches. addition, higher voltage rails start fall regulation first, corresponding maximum duty cycle (Dmax) these particular converters reached. regulators that have lower output voltages achieve some level steady state, before A4490 powers down when corresponding undervoltage thresholds have been reached. example, possible output continue operate down typical, supply derived externally. extent this effect depends myriad factors, including input output filter capacitance, output loads, gate drive amplitude, MOSFET RDS(on), forth. Powering Down with Enable Referring figure present UVLO start-up thresholds, VBBUV(su) VBBCPUV(su) have been reached. Each regulators enabled turn. Initially, VREG1 enabled brought-up under control soft start circuit (tSS). Before VREG1 reaches FB1, VREG2 enabled brought-up under separate soft start control. When both regulators have reached their respective thresholds, power-on-reset (POR) timer initiated. Note that timer only enabled after enabled regulators reach their corresponding levels. After power-onreset time, tPOR elapsed, levels VREG1 VREG2 below their respective levels, then PORZ signal will high. some point later, VREG3 enabled, then PORZ reset VREG3 brought-up under control soft start circuit. When threshold reached, timer initiated. After tPOR elapsed, levels above their respective levels, then PORZ signal will high. Note that regulator channel enabled, channel will influence PORZ. avoid multiple signal changes
PORZ signal, recommended that system designed such that three regulator channels within specification before tPOR elapsed. regulator channel drops below PORZ signal will reset. voltage then recovers within timer initiated again. Note that soft start initiated when feedback voltage drops below level. This allow rapid auto-restart event overload similar fault. soft start required, recommended that receipt PORZ reset signal, system controller disables then re-enables relevant regulator channels again. soon last regulator disabled PORZ signal reset. Power Reset power-on-reset duration, tPOR determined selecting appropriate capacitor connected CPOR pin. value tPOR determined following formula: tPOR 2.131 CPOR PORZ output goes high when both above undervoltage warning levels, pins regulators that enabled VREG voltage. Because external capacitor charged current source, care must taken layout avoid additional leakage paths. capacitor should positioned adjacent CPOR pin, ground connection A4490 should short possible. recommended that tPOR period exceed start-up phases three regulators, avoid possibility multiple triggerings PORZ output. Output Voltage Selection output voltage each three regulators following relationship, shown here VREG1 channel: REG1 where (connected between pin) should value between connected between output rail pin. VREG1 output regulator voltage. reference voltage. tolerances feedback resistors influence voltage setpoint. therefore important consider tolerance selection when targeting overall regulation figure.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
bias current, IBIAS flowing node into will introduce small voltage offset output. Enable Each regulator channel individually enabled corresponding ENBx pin. channel required startup automatically after voltage applied, that particular channel should have tied rail pullup resistor. This resistor should selected limit current less than maximum specified value, This prevents internal protection clamps from turning recommended that pull-up resistor used. This would ensure current remains below maximum value when Soft Start Each regulator channel contains soft start circuit. soft start cycle initiated when appropriate regulator enable input high; VBB, charge pump, bias supply voltages above minimum values; thermal shutdown condition exists. Note that overload short circuit will cause soft start cycle, unless thermal shutdown event occurs. During soft start cycle, reference voltage ramped from typical, which turn forces current demand signal increase linear fashion. Shutdown converter channels disabled event either thermal shutdown event undervoltage (VBBUV(sd) VBBCPUV(sd)). soon above fault conditions have been removed, assuming inputs enabled, appropriate channels will auto-restart under control soft start. Current Limit typical peak current limit each channel specified minimum, with duty cycle 0.9. minimum current limit occurs maximum duty cycle (0.9), because slope compensation maximum effect under this condition. duty cycle reduces, current limit increases. This means applications that operate with narrow duty cycle, possible operate with load current greater than Figure illustrates typical peak current limit versus duty cycle. example, possible operate with peak current limit 3.75 with duty cycle 0.3. well ensuring peak current limit exceeded, under worst case load input voltage conditions, also important
check implications thermal performance. Thermal Considerations section. Component Selection Inductor inductance value, determines ripple current. important ensure that minimum current limit exceeded under worst-case conditions: VBB(min), ILOAD(max), fSW(min), L(min). recommended that gapped ferrite solutions used opposed powdered iron solutions, latter which exhibit relatively high core losses that have large impact long term reliability. Inductors typically specified current levels, current saturation current. With regard current, important understand current level specified, terms ambient temperature. Some manufacturers quote ambient only, whilst others quote temperature that includes self-induced temperature rise. example, inductor rated 85°C includes self-induced temperature rise 25°C maximum load, then inductor cannot safely operated beyond ambient temperature 60°C full load. current assumed simply maximum load current, with perhaps some margin allow overloads, forth. first stage determining inductor value specify peak-to-peak ripple current typically about maximum load.
Duty Cycle
Figure Current limit versus duty cycle
Current Limit
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
maximum peak-to-peak ripple current, IRIPPLE occurs maximum input voltage. Therefore duty cycle, should found under these conditions (for VREG1 channel): D(min) VREG1+Vf VBB(max)+Vf
output capacitor determines output voltage ripple used close control loop. guarantee stability, capacitance increase output voltage reduced. This actually reasonable from ripple voltage point view, ripple voltage typically specified percentage output voltage. following table outlines what minimum output capacitance should given output voltage:
Output Voltage <1.8 Minimum Output Capacitance
where forward voltage drop recirculation diode. required inductance found:
VBB(max) VREG1 D(min) (min) IRIPPLE fSW(min)
Note that manufacturers inductance tolerance should also taken into account. This value high ±20%. peak-to-peak current should exceed avoid instability innermost circuit loops insufficient slope compensation. maximum peak current found from ensure that saturation current level chosen inductor exceeded: Isat ILOAD IRIPPLE
Capacitance values with greater than above values used with effect reducing bandwidth. This necessary systems that have extremely ripple/noise requirements. output ripple largely determined output capacitance effects largely ignored assuming good layout practice observed. output voltage ripple approximated VRIPPLE IRIPPLE COUT
Recommended inductor manufacturers ranges are: Taiyo Yuden: NR6045 series outputs Taiyo Yuden: NRG4026 series outputs Sumida: CDH74 series outputs Output Capacitor interests size, cost performance, highly recommended that ceramic capacitor types used. When using ceramic capacitors another important consideration E-field effects actual value capacitor. minimize effects capacitance reducing with output voltage, recommended that working voltage capacitor considerably more than output voltage. suggestion, recommended that V-rated capacitors should used output voltages below. output voltages V-rated capacitor should used.
When using ceramic capacitors, there generally need consider current carrying capability negligible heating effects ESR. Also, current flowing into output capacitor extremely low. Input Capacitor Again highly recommended that ceramic, capacitors used. value input capacitance determines amount current ripple (EMI) that appears source (VBB supply) terminals. amounts current flowing input capacitor depend relative impedances between input capacitor impedance source impedance. achieve impedance filter solution recommended place least capacitors parallel.
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Again, there generally need consider heating effects current flowing through ESR. Also, phaseshifting input current drawn each regulators helps reduce overall current. Flyback Diode This diode conducts during switch off-time. Schottky diode recommended minimize both forward drop switching losses. worst case dissipation occurs maximum when duty cycle, minimum. average current through diode found: IDIODE(av) ILOAD D(min))
following steps used guideline determining suitable thermal solution. should noted that this process usually iterative achieve optimum solution. These factors considered follows: Step Estimate maximum ambient temperature, TA(max) application. Step Define maximum junction temperature, TJ(max). Note that absolute maximum 150°C. Step Determine worst case power dissipation, PD(max). evaluation should consider these maximum load minimum VBB. Contributors switch static dynamic losses, control losses. These described following sections Switch Static Losses following steps used determine switch static losses: Estimate maximum duty cycle:
forward voltage drop, found from diode characteristics using actual load current (not average current). static power dissipation found: PSTAT ILOAD(av)
also important take into account thermal rating package, ambient temperature, ensure that enough heatsinking provided maintain diode junction temperature within safe operating area device. minimize heating effects from A4490 diode vice-versa, recommended that diode mounted reverse side printed circuit board. Support Components capacitor (C11), charge pump capacitor (C1), reservoir capacitor (C2) filter capacitor (C12) should ceramic X7R. Thermal Considerations ensure A4490 operates safe operating area, which effectively means restricting junction temperature less than 150°C, several checks should made. general approach work what thermal impedance (RJA) required maintain junction temperature given level, particular power dissipation. Another factor worth considering that other power dissipating components system influence thermal performance A4490. example, power loss contribution from recirculation diode sense resistor cause junction temperature A4490 higher than expected.
D(max)
VREG (min)
where forward voltage drop Schottky diode under given load current. Estimate RDS(on) each regulator switch given junction temperature: RDS(on)TJ RDS(on)25C (10) Note that range restricted between RDS(on) increases. example, RDS(on) 25°C with greater than typical, stated Electrical Characteristics table. Under same temperature conditions, with RDS(on) typical. voltages between RDS(on) found linear approximation. more information operating A4490 between voltage Power Configurations section. static loss each switch determined: PSTAT ILOAD2 D(max) RDS(on)TJ where ILOAD load that particular regulator channel. (11)
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Switch Dynamic Losses following used determine switch dynamic losses: Both turn turn losses estimated: PDYN (min) ILOAD 10-9 (12)
Switch static losses 5+0.4 0.84 6+0.4 3.3+0.4 0.58 VREG2 duty cycle, 6+0.4 1.8+0.4 0.34 VREG3 duty cycle, 6+0.4 VREG1 duty cycle, RDS(on) each switch found: RDS(on)TJ 0.653
where switching frequency. Control Losses following steps used determine control losses: PVBB IBBON PVDD IVDD where IVDD quiescent current VDD. Total Losses total losses estimated: PTOTAL PSTAT1 PSTAT2 PSTAT2 +PDYN1 +PDYN2 PDYN3 +PVBB PVDD (15) (14) (13)
static loss each switch found: PSTAT1 0.84 0.653 0.55 PSTAT2 0.58 0.653 0.379 PSTAT3 0.82 0.34 0.653 0.14 Switch dynamic losses 10-9 0.045 PDYN2 10-9 0.045 PDYN3 10-9 0.036 Control losses PVBB 0.005 0.03 PDYN1 PVDD 0.001 0.003 total power dissipation found: PTOTAL 0.55 0.379 0.14 0.045 0.045 0.036 0.03 0.003 1.228 thermal impedance required solution found: 36.6 °C/W 1.228 this particular solution high thermal efficiency board required ensure junction temperature kept below 115°C. maximum effectiveness, area underneath thermal A4490 should exposed copper. Several thermal vias (say between should used connect thermal internal ground plane. possible, additional thermal copper plane should applied bottom side connected thermal A4490 through vias.
where IBBON quiescent current assuming three regulators
Thermal Impedance thermal impedance required solution determined: Example Selected parameters: VBB(min) VREG1 VREG2 VREG3 70°C 115°C
PTOTAL
(16)
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
avoid ground bounce offset issues, highly recommended that ground referenced feedback resistors (R2, should connected close connection A4490 possible. local quiet ground plane around these components implemented, however, this ground plane should have high impedance connection star connection power stages. ground plane used, recommended that does overlap switching nodes (LX1, LX2, LX3) avoid possibility noise pick-up. minimize possibility noise injection issues, recommended isolate ground plane around high impedance nodes such FBx, ENBx CPOR. terms grounding power components, star connection should made minimize ground loop impedances. Note that although ground plane required meet thermal characteristics solution still imperative implement ground star connection power components. ground charge pump (PGND) should connected thermal vias. Figures below illustrates importance keeping ground connections short possible forming good star connections. Figure also illustrates current conduction paths during on-cycle switching FET. following points should noted: capacitor should placed close possible terminals. capacitance should split between terminals VREG1 VREG3 terminal VREG2.
This calculation assumes thermal influence from other components. possible, advisable mount flyback diodes reverse side printed circuit board. Ensure impedance electrical connections implemented between board layers. Layout Guidelines ground plane largely dictated thermal requirements described previous section. ground referenced power components should referenced star ground, located away from A4490 minimize ground bounce issues. small, local, relatively quiet ground plane near A4490 should used ground referenced support components, minimize interference effects ground noise from power circuitry. Figure illustrates recommended grounding architecture.
A4490 Support Components
Power Circuitry
A4490
Local "Quiet' Ground Plane PGND
Cout
Star Connection Thermal Vias Internal Ground Plane
Figure Ground plane configurations
VREG
VREG
COUT RLOAD
COUT RLOAD
Star Connection
Star Connection
Figure on-cycle current conduction paths
Figure off-cycle current conduction paths
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
terminals VREG1 VREG2 should connected short wide traces terminal VREG3. Each inductor should connected close possible respective switching (LX1, LX2, LX3) output capacitors. Figure shows current conduction path during off-cycle switching FET. following points should noted: diode should placed close possible both switching inductor.
Support components: capacitor (C11), charge pump capacitor (C1), reservoir capacitor (C2), filter capacitor (C12) should located close possible their respective terminal connections. ground referenced capacitors should connected close terminal possible. Powering Configurations following three diagrams show typical configurations providing power application. middle diagram corresponds typical application shown front page.
Only supplied
applied externally (first option)
applied externally (second option)
VREG
VREG
VREG
Comments: Simple configuration, only supply required Increased power losses higher voltages start-up (typical), shutdown (typical)
Comments: Reduced power losses higher voltages start-up (typical), shutdown (typical). this case, start-up threshold (VBBUV(su) lower because VREG present
Comments: Power restricted increase RDS(on) buck switches start-up (typical), shutdown (typical)
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
A4490
Triple Output Step-Down Switching Regulator
Package 20-Pin
0.30 4.00 ±0.15 4.00 ±0.15 0.95 2.60 4.10 0.50
2.60 4.10 0.08 +0.05 0.25 -0.07 0.50 SEATING PLANE 0.75 ±0.05 Layout Reference View
Reference Only (reference JEDEC MO-220WGGD) Dimensions millimeters Exact case lead configuration supplier discretion within limits shown Terminal mark area Exposed thermal (reference only, terminal identifier appearance supplier discretion)
+0.15 0.40 -0.10
2.60
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) pads minimum 0.20 from adjacent pads; adjust necessary meet application process requirements layout tolerances; when mounting multilayer PCB, thermal vias exposed thermal land improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Coplanarity includes exposed thermal terminals
2.60
Copyright ©2008, Allegro MicroSystems, Inc. products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. Allegro's products used life support devices systems, failure Allegro product reasonably expected cause failure that life support device system, affect safety effectiveness that device system. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use.
latest version this document, visit website: www.allegromicro.com
Allegro MicroSystems, Inc. Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com

Three buck converters input voltage range fixed frequency Multiphase s

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