SBAS224B DECEMBER 2001 REVISED 2002 16-Bit, 500kSPS, microPower S

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SBAS224B DECEMBER 2001 REVISED 2002 16-Bit, 500kSPS, microPower S

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ADS832ADS
SBAS224B DECEMBER 2001 REVISED 2002
16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
HIGH-SPEED PARALLEL INTERFACE 500kSPS SAMPLING RATE POWER: 85mW 500kSPS BIPOLAR INPUT RANGE TQFP-32 PACKAGE
DESCRIPTION
ADS8323 16-bit, 500kSPS Analog-to-Digital Converter (ADC) with internal 2.5V reference. device includes 16-bit capacitor-based with inherent sample-and-hold. ADS8323 offers full 16-bit interface, 8-bit option where data read using read cycles. ADS8323 available TQFP-32 package specified over industrial -40°C +85°C temperature range.
APPLICATIONS
HIGH-SPEED DATA AQUISITION OPTICAL POWER MONITORING MOTOR CONTROL
Output Latches Three State Drivers
BYTE
ADS832
Parallel Data Output
CDAC Comparator Conversion Control Logic Internal +2.5V CLOCK CONVST BUSY
REFIN REFOUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2001, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION
MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MISSING CODES ERROR (LSB) PACKAGE-LEAD TQFP-32 SPECIFICATION TEMPERATURE RANGE -40°C 85°C
PRODUCT ADS8323Y
PACKAGE DESIGNATOR(1)
ORDERING NUMBER ADS8323Y/250 ADS8323Y/2K ADS8323YB/250 ADS8323YB/2K
TRANSPORT MEDIA, QUANTITY Tape Reel, Tape Reel, 2000 Tape Reel, Tape Reel, 2000
ADS8323YB
TQFP-32
-40°C 85°C
NOTE: most current specifications package information, refer site www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, DGND DVDD -0.3V Supply Voltage, AGND AVDD -0.3V Analog Input Voltage Range AGND 0.3V AVDD 0.3V Reference Input Voltage AGND 0.3V AVDD 0.3V Digital Input Voltage Range DGND 0.3V DVDD 0.3V Ground Voltage Differences, AGND DGND ±0.3V Voltage Differences, DVDD AGND -0.3V Power Dissipation 850mW Operating Virtual Junction Temperature Range, -40°C 150°C Operating Free-Air Temperature Range, -40°C 85°C Storage Temperature Range, TSTG -65°C 150°C Lead Temperature 1.6mm (1/16 inch) from Case 10sec 260°C NOTE: Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY Supply Voltage AVDD(1) DVDD(1) 4.75 4.75 5.25 5.25 UNIT PACKAGE -REFIN +REFIN 2.55 TQFP-32 DISSIPATION RATING TABLE 25°C POWER RATING 1636mW DERATING FACTOR ABOVE 25°C(1) 13.09mW/°C 70°C POWER RATING 1047mW 85°C POWER RATING 850mW
ANALOG/REFERENCE INPUTS Differential analog input voltage (IN+ IN-) External Reference Voltage
NOTE: voltage difference between AVDD DVDD terminals cannot exceed 0.3V maintain performance specifications.
NOTE: This inverse traditional junction-to-ambient thermal resistance (RJA). Thermal resistances production tested informational purposes only.
EQUIVALENT INPUT CIRCUIT
AVDD C(SAMPLE) 20pF DVDD
AGND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit
DGND
Equivalent Digital Input Circuit
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SBAS224B
ELECTRICAL CHARACTERISTICS
-40°C +85°C, +DVDD +AVDD +5V, VREF +2.5V, fSAMPLE 500kSPS, fCLK fSAMPLE, unless otherwise specified. ADS8323Y PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span(1) Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Gain Error(3) Common-Mode Rejection Ratio Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Aperture Delay Aperture Jitter Small-Signal Bandwidth Step Response Overvoltage Recovery DYNAMIC CHARACTERISTICS Total Harmonic Distortion(4) SINAD Spurious-Free Dynamic Range REFERENCE OUTPUT Voltage Source Current Drift Line Regulation REFERENCE INPUT Range DIGITAL INPUT/OUTPUT Logic Family Logic Levels: Data Format POWER-SUPPLY REQUIREMENT Power-Supply Voltage +AVDD +DVDD Supply Current Power Dissipation TEMPERATURE RANGE Specified Performance Specifications same ADS8323Y. NOTES: Ideal input span; does include gain offset error. means Least Signifcant Bit, with VREF equal +2.5V; 1LSB 76µV. Measured relative ideal, full-scale input (+In (-In)) 4.9999V. Thus, gain error includes error internal voltage reference. Calculated first nine harmonics input frequency. 5Vp-p 100kHz 5Vp-p 100kHz 5Vp-p 100kHz IOUT Static Load IOUT 4.75V 5.25V 2.475 ±0.25 2.50 CMOS +5µA -5µA -1.6mA +1.6mA -0.3 +DVDD 2.55 2.525 2.48 2.52 ±0.5 (-IN) -VREF -0.3 -0.3 ±0.5 ±0.12 ±0.25 CONDITIONS +VREF AVDD AVDD ADS8323YB UNITS Bits Bits LSB(2) µVrms kSPS ppm/°C
1Vp-p 1MHz FFFFH Output Code
Binary Two's Complement
4.75 4.75 fSAMPLE 500kSPS fSAMPLE 500kSPS
5.25 5.25
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TIMING CHARACTERISTICS(1)(2)
specifications typical -40°C +85°C, +DVDD +5V. ADS8323Y PARAMETER Conversion Time Acquisition Time CLOCK Period CLOCK HIGH Time CLOCK Time CONVST CLOCK HIGH CONVST Time CONVST BUSY HIGH CONVST CONVST HIGH CLOCK HIGH BUSY HIGH HIGH HIGH Time Data Valid Data Hold from HIGH BYTE Change LOW(3) HIGH Time SYMBOL tCONV tACQ ADS8323YB UNITS
NOTES: input signals specified with rise fall times 5ns, (10% DVDD), timed from voltage level (VIL VIH) timing diagram, below. BYTE asynchronous; when BYTE bits through appear DB15-DB0. When BYTE bits through appear DB7-DB0. remain between changes BYTE.
TIMING DIAGRAM
CLOCK Acquisition Conversion tCONV
Acquisition tACQ
CONVST
BUSY
BYTE
DB15-D8
Bits 15-8
Bits 15-8
DB7-D0
Bits
Bits
Bits 15-8
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SBAS224B
CONFIGURATION
View TQFP
REFOUT
+AVDD
AGND
REFIN
DB15 DB14 DB13 DB12 DB11 DB10
ADS8323
BYTE CONVST CLOCK DGND +DVDD BUSY
ASSIGNMENTS
NAME DB15 DB14 DB13 DB12 DB11 DB10 BUSY +DVDD DESCRIPTION Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data HIGH when conversion progress. Digital Power Supply, +5VDC. NAME DGND CLOCK DESCRIPTION Digital Ground external CMOS compatible clock applied CLOCK input synchronize conversion process external source. Convert Start, Active LOW. Synchronization pulse parallel output, Active LOW. Selects most significant bits (LOW) least significant bits (HIGH). Data valid pins 9-16. Chip Select, Active LOW. Inverting Input Channel Noninverting Input Channel Analog Ground Analog Power Supply, +5VDC. Connect Connect Reference Input. When using internal 2.5V reference this directly REFOUT. Reference Output
CONVST BYTE AGND +AVDD REFIN REFOUT
NOTE: Analog Input, Analog Output, Digital Input, Digital Output, Power-Supply Connection.
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TYPICAL CHARACTERISTICS
-40°C +85°C, +DVDD +AVDD +5V, VREF +2.5V, fSAMPLE 500kSPS, fCLK fSAMPLE, unless otherwise specified.
SIGNAL-TO-NOISE RATIO SIGNAL-TO-(NOISE+DISTORTION) INPUT FREQUENCY
FREQUENCY SPECTRUM (4096 Point FFT; 100.1kHz, -0.2dB)
SNR, SINAD (dB)
Amplitude (dB)
-110 -130 Frequency (kHz)
SINAD
Frequency (kHz)
SPURIOUS-FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION INPUT FREQUENCY -100
INL+ TEMPERATURE 22.9
SFDR (dB)
(dB)
SFDR
Frequency (kHz)
-0.1
-7.6 Temperature (°C)
INL- TEMPERATURE 0.05
0.25
DNL+ TEMPERATURE 19.1
Delta (LSB)
Delta (LSB)
0.15
11.4
-0.05
-3.8
Delta (µV)
0.05
-0.10
-7.6
-0.05
-3.8
-0.15
-11.4
-0.20
Temperature (°C)
-15.3
-0.15
-11.4 Temperature (°C)
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SBAS224B
Delta (µV)
Delta (µV)
Delta (LSB)
TYPICAL CHARACTERISTICS (Cont.)
-40°C +85°C, +DVDD +AVDD +5V, VREF +2.5V, fSAMPLE 500kSPS, fCLK fSAMPLE, unless otherwise specified.
DNL- TEMPERATURE -0.2 -0.4 -0.6 45.8 30.5 15.3
GAIN ERROR TEMPERATURE 762.9 610.4 457.8 305.2 152.6 -152.6 Temperature (°C)
Delta (LSB)
Delta (LSB)
Delta (µV)
-15.3 -30.5 -45.8
Temperature (°C)
VREF TEMPERATURE -1.0 26.2 13.1 -13.1
TEMPERATURE
Delta (LSB)
Delta (mV)
-2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 Temperature (°C)
-26.2 -39.3 -52.4 -65.5 -78.6 -91.8 -104.9
Delta (mA)
-0.4
-0.8
-1.2
Temperature (°C)
BIPOLAR ZERO TEMPERATURE -0.2 -0.6 106.8 76.3 45.8
Delta (µV)
-0.6
POSITIVE FULL-SCALE TEMPERATURE 412.0 335.7 253.4 183.1 106.8 30.5 -45.8 Temperature (°C)
Delta (LSB)
Delta (LSB)
15.3 -15.3 -45.8 -76.3
Temperature (°C)
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Delta (µV)
Delta (µV)
TYPICAL CHARACTERISTICS (Cont.)
-40°C +85°C, +DVDD +AVDD +5V, VREF +2.5V, fSAMPLE 500kSPS, fCLK fSAMPLE, unless otherwise specified.
NEGATIVE FULL-SCALE TEMPERATURE 76.3 -76.3 -152.6 -228.9 -305.2 -381.5
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR CODE
Delta (LSB)
Delta (µV)
(LSB) (LSB)
Temperature (°C)
-0.5 -1.0 -1.5 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Decimal Code
THEORY OPERATION
ADS8323 high-speed Successive Approximation Register (SAR) 16-bit with internal 2.5V bandgap reference that operates from single supply. input fully differential with typical common-mode rejection 70dB. part accepts differential analog input voltage range -VREF +VREF, centered common-mode voltage (see Analog Input section). part will also accept bipolar input ranges when level shift circuit used front (see Figure Figure basic operating circuit ADS8323. ADS8323 requires external clock conversion process. This clock vary between 25kHz (1.25kHz throughput) 10MHz (500kSPS throughput). duty cycle clock unimportant long minimum HIGH times least 40ns clock period least 100ns. minimum clock frequency governed parasitic leakage Capacitive Digital-to-Analog Converter (CDAC) capacitors internal ADS8323. analog input provided input pins, -IN. When conversion initiated, differential input these pins sampled internal capacitor array. conversion initiated ADS8323 bringing CONVST (pin minimum 20ns. CONVST places sample-and-hold amplifier hold state conversion process started. BUSY output (pin will HIGH when conversion begins will stay HIGH during conversion. While conversion progress, both inputs disconnected from internal function. When conversion result latched into output register, BUSY signal will LOW. data read from parallel output following conversion bringing both LOW.
NOTE: This mode operation described more detail Timing Control section this data sheet.
SAMPLE-AND-HOLD SECTION
sample-and-hold ADS8323 allow accurately convert input sine wave full-scale amplitude 16-bit resolution. input bandwidth sample-andhold greater than Nyquist rate (Nyquist equals one-half sampling rate) even when operated maximum throughput rate 500kSPS. typical small-signal bandwidth sample-and-hold amplifier 20MHz. Typical aperture delay time, time takes ADS8323 switch from sample hold mode following negative edge CONVST signal, 10ns. average delta repeated aperture delay values typically 30ps (also known aperture jitter). These specifications reflect ability ADS8323 capture input signals accurately exact same moment time.
REFERENCE
internal reference used, REFOUT (pin should directly connected REFIN (pin 31). ADS8323 operate, however, with external reference range 1.5V 2.55V corresponding full-scale range 3.0V 5.1V. internal reference ADS8323 doublebuffered. internal reference used drive external load, buffer provided between reference load applied REFOUT (pin (the internal reference typically source sink 10µA current; compensation capacitance should least 0.1µF minimize noise). external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion.
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SBAS224B
Analog Supply 10µF 0.1µF
0.1µF 20pF Analog Input
REFIN
REFOUT
+AVDD
AGND
DB15 DB14 DB13 DB12
BYTE CONVST ADS8323 CLOCK DGND +DVDD BUSY
Chip Select
Read Input Conversion Start Clock Input
DB11 DB10
Busy Output
FIGURE Typical Circuit Configuration.
ANALOG INPUT
analog input bipolar fully differential. There general methods driving analog input ADS8323: single-ended differential, shown Figures When input single-ended, input held common-mode voltage. input swings around same common voltage peak-to-peak amplitude (common-mode VREF) (common-mode VREF). value VREF determines range over which common-mode voltage vary (see Figure
-VREF +VREF peak-to-peak Common Voltage Single-Ended Input
ADS832
VREF peak-to-peak Common Voltage ADS8323 VREF peak-to-peak Differential Input
FIGURE Methods Driving ADS8323 either SingleEnded Differential.
ADS832SBAS224B
When input differential, amplitude input difference between input, (+IN) (-IN). peak-to-peak amplitude each input ±1/2VREF around this common voltage. However, since inputs 180° out-of-phase, peak-to-peak amplitude differential voltage +VREF -VREF. value VREF also determines range voltage that common both inputs (see Figure each case, care should taken ensure that output impedance sources driving inputs matched. matching observed, result offset error, which changes with temperature. Often, small capacitor (20pF) between positive negative inputs helps match their impedance. input current analog inputs depends number factors: sample rate, input voltage, source impedance. Essentially, current into ADS8323 charges internal capacitor array during sampling period. After this capacitance been fully charged, there further input current. source analog input voltage must able charge input capacitance (25pF) 16-bit settling level within clock cycles (400ns), minimum acquisition time used. When converter goes into hold mode, input impedance greater than Care must taken regarding absolute analog input voltage. inputs should always remain within range AGND 0.3V AVDD 0.3V.
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VREF +VREF Voltage
Voltage -VREF VREF Single-Ended Inputs
1/2VREF Voltage 1/2VREF
+VREF
-VREF Differential Inputs (+IN) (-IN)
Common-Mode Voltage (Single-Ended Mode) IN-. maximum differential voltage between ADS8323 VREF. Figures further explanation common voltage range single-ended differential inputs.
NOTES: Common-Mode Voltage (Differential Mode)
FIGURE Using ADS8323 Single-Ended Differential Input Modes.
AVDD
4.55 AVDD 4.025
Common Voltage Range
Common Voltage Range
Single-Ended Input
2.75 2.25
Differential Input
0.45
0.975
VREF 2.55
VREF 2.55
FIGURE Single-Ended Input: Common-Mode Voltage Range VREF.
FIGURE Differential Input: Common-Mode Voltage Range VREF.
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SBAS224B
NOISE
Figure shows transition noise ADS8323. lowlevel input applied analog-input pins converter through 8192 conversions. digital output will vary output code internal noise ADS8323. This true 16-bit SAR-type ADCs. ADS8323, with five output codes distribution, will yield ±0.8LSB transition noise operation. Remember that achieve this low-noise performance, peak-to-peak noise input signal reference must 50µV.
5052
OPA132
(pin (pin
Bipolar Input
OPA353 BIPOLAR INPUT ±10V ±2.5V
ADS8323 REFOUT (pin 2.5V
FIGURE Level Shift Circuit Bipolar Input Ranges.
DIGITAL INTERFACE
1968 0014
TIMING CONTROL
timing diagram Timing Characteristics section detailed information timing signals their requirements. ADS8323 uses external clock (CLOCK, that controls conversion rate CDAC. With 10MHz external clock, sampling rate 500kSPS that corresponds maximum throughput time.
0015
0016 Code
0017
0018
FIGURE Histogram 8192 Conversions Low-Level Input.
EXPLANATION CLOCK, BUSY BYTE PINS
CLOCK-An external clock must provided ADS8323. maximum clock frequency 10MHz that provides 500kSPS throughput. minimum clock frequency 25kHz that provides 1.25kHz throughput. minimum clock cycle 100ns (see Timing Diagram, tC1), CLOCK must remain HIGH (see Timing Diagram, tW1) (see Timing Diagram, tW2) least 40ns. BUSY-Initially BUSY output LOW. Reading data from output register sampling input analog signal will affect state BUSY signal. After CONVST input goes conversion starts, maximum 25ns later BUSY output will HIGH. That signal will stay HIGH during conversion will provide status internal conversion, rising edge 17th clock cycle, data from internal latched into output registers. BUSY signal will maximum 25ns later (see Timing Diagram, tD4). BYTE-The output data will appear full 16-bit word DB15-DB0 (MSB-LSB D15-D0) BYTE LOW. there only 8-bit available board, result also read 8-bit using only DB7-DB0. this case, reads necessary (see Timing Diagram). first, before, leaving BYTE reading least significant bits DB7-DB0, then bringing BYTE HIGH. When BYTE HIGH, upper bits (D15-D8) will appear DB7-DB0.
AVERAGING
Averaging digital codes compensate noise ADC. averaging conversion results, transition noise will reduced factor 1/n, where number averages. example, averaging conversion results will reduce transition noise ±0.4LSB. Averaging should only used input signals with frequencies near signals, digital filter used low-pass filter decimate output codes. This works similar manner averaging-for every decimation signal-to-noise ratio will improve 3dB.
BIPOLAR INPUTS
differential inputs ADS8323 were designed accept bipolar inputs (-VREF +VREF) around common-mode voltage, which corresponds input range with 2.5V reference. using simple circuit featuring four high-precision external resistors, ADS8323 configured accept bipolar inputs. conventional ±2.5V, ±5V, ±10V input ranges could interfaced ADS8323 using resistor values shown Figure
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START CONVERSION READING DATA
bringing CONVST signal LOW, input data immediately placed hold mode (10ns). Although must when CONVST goes initiate conversion. conversion follows with next rising edge CLOCK. important detect hold command during certain clock cycle, then falling edge CONVST signal must occur least 10ns before rising edge CLOCK (see Timing Diagram, tD1). CONVST signal remain without initiating conversion. CONVST signal must HIGH least 20ns (see Timing Diagram, tW4) before brought again CONVST must stay least 20ns (see Timing Diagram, tW3). Once CONVST signal goes LOW, further impulses this signal ignored until conversion finished part reset. When conversion finished (after clock cycles) sampling switches will close sample value. start next conversion must delayed allow input capacitor ADS8323 fully charged. This delay time depends driving amplifier, should least 400ns. gain acquisition time, falling edge CONVST must take place just before rising edge CLOCK (see Timing Diagram, tD1). conversion cycle requires clock cycles. However, reading data during conversion falling hold edge might cause loss performance. Reading Data (RD, CS)-In general, data outputs tri-state. Both must enable these outputs. must stay together least 40ns (see Timing Diagram, tD7) before output data valid. must remain HIGH least 20ns (see Timing Diagram, tW7) before bringing back subsequent read command. clock-cycles after start conversion (next rising edge clock after falling edge CONVST), data latched into output register reading process start again. being tells ADS8323 that board assigned ADS8323. shares with digital gates, there possibility that digital (high-frequency) noise gets coupled into ADC. just used ADS8323, hard-wired ground. output data should read 125ns prior falling edge CONVST 10ns after falling edge. ADS8323's output Binary Two's Complement format (see Figure
DESCRIPTION Full-Scale Range Least Significant (LSB) +Full Scale Midscale Midscale 1LSB Zero ANALOG VALUE VREF VREF/65535 BINARY CODE +VREF -VREF 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 CODE 7FFF 0000 FFFF 8000
LAYOUT
optimum performance, care should taken with physical layout ADS8323 circuitry. This particularly true CLOCK input approaching maximum throughput rate. ADS8323 offers single-supply operation, will often used close proximity with digital logic, microcontrollers, microprocessors, digital signal processors. more digital logic present design higher switching speed, more difficult will achieve good performance from converter. basic architecture sensitive glitches sudden changes power supply, reference, ground connections, digital inputs that occur just prior latching output analog comparator. Thus, during single conversion n-bit converter, there "windows" which large external transient voltages affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high-power devices. degree error digital output depends reference voltage, layout, exact timing external event. Their error change external event changes time with respect CLOCK input. average, ADS8323 draws very little current from external reference reference voltage internally buffered. reference voltage external originates from amp, make sure that drive bypass capacitor capacitors without oscillation. 0.1µF bypass capacitor recommended from directly ground. AGND DGND pins should connected clean ground point. cases, this should "analog" ground. Avoid connections which close grounding point microcontroller digital signal processor. required, ground trace directly from converter powersupply entry point. ideal layout will include analog ground plane dedicated converter associated analog circuitry. with connections, should connected power supply plane, trace, that separate from connection digital logic until they connected power entry point. Power ADS8323 should clean well bypassed. 0.1µF ceramic bypass capacitor should placed close device possible. addition, 10µF capacitor recommended. needed, even larger capacitor series resistor used low-pass filter noisy supply. some situations, additional bypassing required, such 100µF electrolytic capacitor, even filter made inductors capacitors designed essentially low-pass filter supply, removing high-frequency noise.
DIGITAL OUTPUT BINARY TWO'S COMPLEMENT
TABLE Ideal Input Voltages Output Codes.
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SBAS224B
Binary Two's Complement 0111 1111 1111 1111 0111 1111 1111 1110 0111 1111 1111 1101 65535
65534 6553
Digital Output Code
0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111
32769
32768
32767
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
VNFS VREF 0.000038V 0.000076V 0.000152V 16-BIT
2.499962V
2.500038V VBPZ 2.5V
VPFS VREF VPFS 1LSB 4.999924V 4.999848V 1LSB 76µV 2.5V VREF 2.5V
Unipolar Analog Input Voltage
Bipolar Input, Binary Two's Complement Output: (BTC) Negative Full-Scale Code VNFS 8000H, Vcode VREF Bipolar Zero Code VBPZ 0000H, Vcode Positive Full-Scale Code VPFS 7FFFH, Vcode (VCM VREF) 1LSB
FIGURE Ideal Conversion Characteristics (Condition: Single-Ended. 2.5V, VREF 2.5V).
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PACKAGE DRAWING (S-PQFP-G32)
0,23 0,17
MPQF027 NOVEMBER 1995
PLASTIC QUAD FLATPACK
0,50
0,08
0,13
3,50 5,05 4,95 7,10 6,90 1,05 0,95
Gage Plane
0,25 0,10 0,70 0,40
Seating Plane 1,20 0,08 4087735/A 11/95 NOTES: linear dimensions millimeters. This drawing subject change without notice.
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SBAS224B
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8323Y/250 ADS8323Y/2K ADS8323YB/250
Status ACTIVE ACTIVE ACTIVE
Package Type TQFP TQFP TQFP
Package Drawing
Pins Package Plan 2000
Lead/Ball Finish SNPB SNPB SNPB
Peak Temp Level-3-220C-168 Level-3-220C-168 Level-3-220C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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SBAS224B DECEMBER 2001 REVISED 2002 16-Bit, 500kSPS, microPower S

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