8M-BIT MASK (8/16 OUTPUT) organization (byte mode) 512K (word mod

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8M-BIT MASK (8/16 OUTPUT) organization (byte mode) 512K (word mod

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MX23C8111
8M-BIT MASK (8/16 OUTPUT)
organization (byte mode) 512K (word mode) Fast access time Random access: 95ns (max.) Page access: 50ns (max.) Current Operating: 60mA Standby: 100uA Supply voltage 5V±10% Package (500mil) PDIP (600mil)
ORDER INFORMATION
Part Access Page Access Package Time MX23C8111MC-95 95ns Time 50ns 50ns 60ns 50ns 50ns 60ns PDIP PDIP PDIP
MX23C8111MC-10 100ns MX23C8111MC-12 120ns MX23C8111PC-95 95ns
MX23C8111PC-10 100ns MX23C8111PC-12 120ns
CONFIGURATION
BYTE D15/A1
DESCRIPTION
PDIP
BYTE D15/A-1
MX23C8111
MODE SELECTION
Byte D15/A-1 Output Input D0~D7 High High D0~D7 D0~D7 D8~D15 High High D8~D15 High Mode Word Byte Power Stand-by Active Active Active
P/N:PM0171
MX23C8111
Symbol A0~A18 D0~D7
Function Address Inputs Data Outputs Chip Enable Input Output Enable Input Power Supply Ground Connection
REV. 2.2, NOV. 2001
MX23C8111
BLOCK DIAGRAM
A0/(A-1) BYTE Address Buffer Memory Array Page Buffer Page Decoder Word/ Byte Output Buffer D15/(D7)
ABSOLUTE MAXIMUM RATINGS
Item Voltage Relative Input Voltage Output Voltage Ambient Operating Temperature Storage Temperature Symbol Topr Tstg Ratings -0.3V 7.0V -0.3V 0.5V -0.3V 0.5V -65° 125°
CHARACTERISTICS 70°C, 5V±10%)
Item Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance Symbol ICC1 ISTB1 ISTB2 COUT MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 10uA 10uA 60mA 100uA 10pF 10pF Conditions -1.0mA 2.1mA
f=10MHz, output open CE=VIH 0.2V 1MHZ 1MHZ
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
CHARACTERISTICS 70°C, 5V±10%)
Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Delay Symbol tACE 23C8111-95 MIN. MAX. 95ns 90ns 95ns 50ns 50ns 20ns 23C8111-10 MIN. MAX. 100ns 100ns 100ns 50ns 50ns 20ns 23C8111-12 MIN. MAX. 120ns 120ns 120ns 60ns 60ns 20ns
Note:Output high-impedance delay (tHZ) measured from going high, this parameter guaranteed design over full voltage temperature operating range tested.
Test Conditions
Input Pulse Levels 0.4V~2.7V 95ns 100ns speed grade 0.4V~2.4V 120ns speed grade Input Rise Fall Times 10ns Input Timing Level 1.5V Output Timing Level 0.8V 2.0V Output Load Figure
(load)=-1mA DOUT (load)=2.1mA
C<100pF
Note:No output loading present tester load board. Active loading used under software programming control. Output loading capacitance includes load board's stray capacitance.
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
TIMING DIAGRAM
Access Timing (Normal Access)
tACE
DATA
VALID
VALID
VALID
Page Read
A3-A18
VALID
(A-1),A0,A1,A2
1'st
2'nd VALID VALID
3'rd
DATA
VALID
Note: enable. Page size words 16-bit mode, bytes 8-bit mode.
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
PACKAGE INFORMATION 42-PIN PLASTIC DIP(600 mil)
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
44-PIN PLASTIC
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
REVISION HISTORY
REVISION DESCRIPTION Characteristics: tOH-10ns Modify Package Information PAGE P5,6 DATE JAN/29/1999 NOV/22/2001
P/N:PM0171
REV. 2.2, NOV. 2001
MX23C8111
MACRONIX INTERNATIONAL CO., LTD.
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http //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.

8M-BIT MASK (8/16 OUTPUT) organization (byte mode) 512K (word mod

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