RISC PROCESSOR RISCore IDT79R3500 Integrated Device Technolo

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IDT79R3500 RISC PROCESSOR RISCore
RISC PROCESSOR RISCore
IDT79R3500
Integrated Device Technology, Inc.
FEATURES:
Efficient Pipelining-The CPU's 5-stage pipeline design assists obtaining execution rate approaching instruction cycle. Pipeline stalls exceptions handled precisely efficiently. On-Chip Cache Control-The IDT79R3500 provides high-bandwidth memory interface that handles separate external Instruction Data Caches ranging size from 256kBs each. Both caches accessed during single cycle. cache control on-chip. On-Chip Memory Management Unit-A fully-associative, 64-entry Translation Lookaside Buffer (TLB) provides fast address translation virtual-to-physical memory mapping virtual address space. Dynamically able switch between Big- Little- Endian byte ordering conventions. Optimizing Compilers available FORTRAN, Pascal, COBOL, Ada, PL/1 C++. through 40MHz clock rates yield 32VUPS sustained throughput. Supports independent multi-word block refill both instruction data caches with variable block sizes.
Supports concurrent refill execution instructions. Partial word stores executed read-modify-write. external interrupt inputs, software interrupts, with single cycle latency exception handler routine. Flexible multiprocessing support chip with impact uniprocessor designs. single chip integrating R3000 R3010 execution units, using R3000A pinout. Software compatible with R3000, R2000 CPUs R3010, R2010 FPAs. disable feature allowing simple memory model Embedded Applications. Programmable width allowing reduced cost cache. Hardware Support Single- Double-Precision Floating Point Operations that include Add, Subtract, Multiply, Divide, Comparisons, Conversions. Sustained Floating Point Performance MFlops single precision LINPACK 7.3MFLOPS double precision Supports Full Conformance With IEEE 754-1985 Floating Point Specification 64-bit operation using sixteen 64-bit data registers Military product compliant MIL-STD 833, class
IDT79R3500 PROCESSOR
CONTROL
Master Pipeline/Bus Control (System Control Coprocessor)
Registers Exponent Unit Divide Unit Multiply Unit
Exception/Control Registers Memory Management Unit Registers Translation Lookaside Buffer entries) Virtual Page Number/ Virtual Address
General Registers (32x32) Local Control Logic Shifter Integer Multiplier/Divider Address Adder Increment/Mux
(20+4) ADDRESS (18)
logo registered trademark RISCore, CEMOS trademarks Integrated Device Technology, Inc.
Data (32+4)
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1992 Integrated Device Technology, Inc.
OCTOBER 1992
DSC-9054/3
IDT79R3500 RISC PROCESSOR RISCore
DESCRIPTION:
IDT79R3500 RISC Microprocessor consists three tightly-coupled processors integrated single chip. first processor full 32-bit based RISC (Reduced Instruction Computer) principles achieve standard microprocessor performance. second processor system control coprocessor, called CP0, containing fully-associative 64-entry (Translation Lookaside Buffer), (Memory Management Unit) control registers, supporting virtual memory subsystem, Harvard Architecture Cache Controller achieving bandwidth 320MBs/second using industry standard static RAMs. third processor Floating Point Accelerator which performs arithmetic operations values floating-point representations. This processor fully conforms requirements ANSI/IEEE Standard 754-1985, "IEEE Standard Binary Floating-Point Arithmetic." addition, architecture fully supports standard's recommendations. programmer model this device will same programmer model system which uses discrete IDT79R3000 with IDT79R3010: integer registers, floating point registers; co-processor registers; floating point status control register; RISC integer ALU; Integer Multiply Divide ALU; Floating Point Add/Subtract, Multiply, Divide ALUs. device pipeline will same IDT79R3000, will co-processor functionality. instructions have been introduced. compatibility extends characteristics, software execution initialization mode vector selection. This data sheet provides overview features architecture IDT79R3500 CPU, Revision 3.0. more detailed description operation device incorporated R3500 Family Hardware User Manual, more detailed architectural overview provided MIPS RISC Architecture book, both available from IDT. Documentation providing details software development environments supporting this processor also available from IDT. IDT79R3500 Registers IDT79R3500 provides general purpose 32bit registers, 32-bit Program Counter, 32-bit registers that hold results integer multiply divide operations. Only general registers have special purpose: register hardwired value "0", which useful constant, register used link register jump-and-link instructions (return address subroutine calls). registers shown Figure Note that there Program Status Word (PSW) register shown this figure: functions traditionally provided register instead provided Status Cause registers incorporated within System Control Coprocessor (CP0).
REGISTERS
IDT79R3010A provides general purpose 32bit registers, Control/Status register, Revision Identification register. Floating-point coprocessor operations reference three types registers: Floating-Point Control Registers (FCR) Floating-Point General Registers (FGR) Floating-Point Registers (FPR)
General Purpose Registers Multiply/Divide Registers
Program Counter
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Figure IDT79R3500 Registers
Floating-Point General Registers (FGR) There Floating-Point General Registers (FGR) FPA. They represent directly-addressable 32-bit registers, accessed Load, Store, Move Operations. Floating-Point Registers (FPR) FGRs described preceding paragraph also used form sixteen 64-bit Floating-Point Registers (FPR). Pairs general registers (FGRs), example FGR0 FGR1 (Figure physically combined form single 64-bit FPR. FPRs hold value either single- doubleprecision floating-point format. Double-precision format FPRs formed from adjacent FGRs. Floating-Point Control Registers (FCR) There Floating-Point Control Registers (FCR) FPA. They accessed only Move operations include following: Control/Status register, used control monitor exceptions, operating modes, rounding modes; Revision register, containing revision information about FPA.
IDT79R3500 RISC PROCESSOR RISCore
General Purpose Registers (FGR/FPR) FGR1 FGR3 FGR5 FGR0 Control/Status Register FGR2 FGR4 Exceptions/Enables/Modes Implementation/Revision Register
FGR27 FGR29 FGR31 FGR26 FGR28 FGR30
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Figure Registers
Instruction Overview IDT79R3500 instructions bits long, there only three instruction formats. This approach simplifies instruction decoding, thus minimizing instruction execution time. IDT79R3500 processor initiates instruction every cycle, able complete instruction almost every clock cycle. only exceptions Load instructions Branch instructions, which each have single cycle latency associated with their execution. Note, however, that majority cases compilers able fill these latency cycles with useful instructions which require result previous instruction. This effectively eliminates these latency effects. actual instruction determined after extensive simulations determine which instructions should implemented hardware, which operations best synthesized software from other basic instructions. This methodology resulted IDT79R3500 having highest performance available microprocessor.
I-Type (Immediate) immediate
J-Type (Jump) R-Type (Register) target
funct
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Figure IDT79R3500 Instruction Formats
IDT79R3500 instruction divided into following groups: Load/Store instructions move data between memory general registers. They I-type instructions, since only addressing mode supported base register plus 16bit, signed immediate offset. Load instruction single cycle latency, which means that data being loaded available instruction immediately after load instruction. compiler will fill this delay slot with either instruction which dependent loaded data, with instruction. There latency associated with store instruction. Loads Stores performed byte, half-word, word, unaligned word data (32-bit data aligned modulo-4 address). cache constructed write-through cache. Computational instructions perform arithmetic, logical shift operations values registers. They occur both R-type (both operands result registers) I-type (one operand 16-bit immediate) formats. computational instructions perform arithmetic operations floating point values registers. Note that computational instructions three operand instructions; that result operation stored into different register than either operands. This means that operands need overwritten arithmetic operations. This results more efficient large register set. Conversion instructions perform conversion operations floating point values registers. Compare intructions perform comparisons contents registers condition based results. result compare operations tied directly Cond software testing. Jump Branch instructions change control flow program. Jumps always paged absolute address formed combining 26-bit target with four bits Program counter (J-type format, subroutine calls), 32-bit register byte addresses (R-type, returns
IDT79R3500 RISC PROCESSOR RISCore
Description Load/Store Instructions Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte Store Halfword Store Word Store Word Left Store Word Right Load/Store/Move Instructions Load Word Store Word from Move Word Move Word from Move Control word Move Control word from Arithmetlc Instructions (ALU Immediate) Immediate Immediate Unsigned Less Than Immediate Less Than Immediate Unsigned Immediate Immediate Exclusive Immediate Load Upper Immediate Arithmetic Instructions (3-operand, register-type) Unsigned Subtract Subtract Unsigned Less Than Less Than Unsigned Exclusive Computational Instructions Floating point Floating point Subtract Floating point Multiply Floating point Divide Floating-point Absolute value Floating point Move Floating point Negate Compare Instructions Floating-point Compare Shift Instructions Shift Left Logical Shift Right Logical
Description
LWC1 SWC1 MTC1 MFC1 CTC1 CFC1
SLLV SRLV SRAV CVT.S.fmt CVT.D.fmt CVT.W.fmt MULT MULTU DIVU MFHI MTHI MFLO MTLO JALR BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL
Shift Instructions (Cont.) Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable Conversion Instructions Floating point Convert Single Floating point Convert Double Floating point Convert fixed point MultIply/Divide Instructions Multiply Multiply Unsigned Divide Divide Unsigned Move From Move Move From Move Jump Branch Instructions Jump Jump Link Jump Register Jump Link Register Branch Equal Branch Equal Branch Less than Equal Zero Branch Greater Than Zero Branch Less Than Zero Branch Greater than Equal Zero Branch Less Than Zero Link Branch Greater than Equal Zero Link Special Instructions System Call Break Coprocessor Instructions Load Word from Coprocessor Store Word Coprocessor Move Coprocessor Move From Coprocessor Move Control Coprocessor Move Control From Coprocessor Coprocessor Operation Branch Coprocessor True Branch Coprocessor False System Control Coprocessor (CPO) Instructions Move Move From Read indexed entry Write Indexed entry Write Random entry Probe matching entry Restore From Exception
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ADDI ADDIU SLTI SLTIU ANDI XORI
ADDU SUBU SLTU ADD.fmt SUB.fmt MUL.fmt DlV.fmt ABS.fmt MOV.fmt NEG.fmt C.cond.fmt
SYSCALL BREAK LWCZ SWCZ MTCZ MFCZ CTCZ CFCZ COPZ BCZT BCZF
MTC0 MFC0 TLBR TLBWI TLBWR TLBP
IDT79R3500 Instruction Summary
IDT79R3500 RISC PROCESSOR RISCore
dispatches). Branches have 16-bit offsets relative program counter (I-type). Jump Link instructions save return address Register R3500 instruction features number branch conditions. Included ability compare register zero branch, also ability branch based comparison between registers. Thus, performance increased since software does have perform arithmetic instructions prior branch branch conditions. Coprocessor instructions perform operations coprocessors. Coprocessor Loads Stores I-type. Coprocessor instructions perform operations System Control Coprocessor (CP0) registers manipulate memory management exception handling facilities processor. Special instructions perform variety tasks, including movement data between special general registers, system calls, breakpoint. They always R-type. Table lists instruction IDT79R3500 processor. IDT79R3500 System Control Coprocessor (CP0) IDT79R3500 operate with four tightlycoupled coprocessors (designated through CP3). System Control Coprocessor CP0), incorporated IDT79R3500 chip supports virtual memory system exception handling functions IDT79R3500. virtual memory system implemented using Translation Lookaside Buffer group programmable registers shown Figure System Control Coprocessor (CP0) Registers registers shown Figure used control memory management exception handling capabilities IDT79R3500. Table provides brief description each register.
SYSTEM CONTROL COPROCESSOR (CP0) INSTRUCTIONS
Register EntryHi EntryLo Index Random Status Cause Context BadVA PRId Description High half entry half entry Programmable pointer into array Pseudo-random pointer into array Mode, interrupt enables, diagnostic status info Indicates nature last exception Exception Program Counter Pointer into kernel's virtual Page Table Entry array Most recent virtual address Processor revision identification (Read only)
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STATUS
CAUSE
ENTRYHI
ENTRYLO
INDEX
RANDOM CONTEXT Used with Virtual Memory System Used with Exception Processing
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ACCESSED RANDOM
BADVA
Figure System Coprocessor Registers
IDT79R3500 RISC PROCESSOR RISCore
Memory Management System IDT79R3500 addressing range 4GB. However, since most IDT79R3500 systems implement physical memory smaller than 4GBs, IDT79R3500 provides logical expansion memory space translating addresses composed large virtual address space into available physical memory address. modes supported. When used, address space divided into 2GBs which accessed both users kernel, 2GBs kernel only. Virtual addresses within kernel/user segment translated physical addresses page basis. This mode typical UNIX other sophisticated operating systems. When disabled, mapping locked 2GBs kernel/user, 1.5GBs kernel only. This mode requires manipulation, provides large linear address space, typical embedded applications. (Translation Lookaside Buffer) Virtual memory mapping assisted Translation Lookaside Buffer (TLB). on-chip provides very fast virtual memory access well-matched requirements multi-tasking operating systems. fully-associative contains entries, each which maps page, with controls read/write access, cacheability, process identification. allows each user access 2GBs virtual address space. Figure illustrates format each entry. Translation operation involves matching current Process
(PID) upper bits address against (Virtual Page Number) fields TLB. When both match entry Global), replaced with (Physical Frame Number) form physical address. misses handled software, with entry replaced determined imple RANDOM function. routine process miss UNIX environment requires only 10-12 cycles, which compares favorably with many CPUs which perform operation hardware. Disabled Operation Many embedded systems like complexity uncertainty associated with on-chip TLB. However, many systems still desire ability implement kernel/user mode. Therefore, implement hierachical task model, must used. R3500 gives system designer more option, allowing disabled performing fixed mapping virtual physical addresses, while maintaining separation kernel user resources. user elect disable through reset sectors. this case, mapping shown Figure used, device power consumption reduced. Note "cached" segments means that there mechanism exclude addresses these regions from cache. This mapping means that applications designed kseg0 kseg1 avoid TLB) R3500, disable reduce power, have change software take advantage this feature.
TLBPID
ENTRYHI Virtual Page Number TLBPID Process Physical Frame Number Non-cacheable flag Dirty flag (Write protect) Valid entry flag Global flag (ignore PID) Reserved
ENTRYLO
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Figure Entry Format
IDT79R3500 RISC PROCESSOR RISCore
0xFFFFFFFF KERNEL MAPPED CACHEABLE (kseg2) 0xC0000000 KERNEL UNMAPPED UNCACHED (kseg1) 0xA0000000 KERNEL UNMAPPED CACHED (kseg0) 0x80000000 0x7FFFFFFFF KERNEL/USER MAPPED CACHEABLE (kuseg)
0xFFFFFFFF
PHYSICAL MEMORY
3584
0x20000000 0x1FFFFFFF MEMORY 0x00000000
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Figure IDT79R3500 Virtual Address Mapping
Address Translation Virtual Physical (TBL Disabled)
0xffffffff Kernel Cached (kseg2) 0xc0000000 Kernel Uncached 0xa0000000 (kseg1) Kernel Uncached (kseg0) Kernel/User Cacheable Tasks 2048 Kernel Cacheable Tasks 1024
0x80000000
User Cached (kseg)
Inaccessible
0x00000000
Kernel Boot
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NOTE: This model consistent with mapping available IDT79R3051 family. identical mapping provides software compatibility lower cost CPUs. Figure Disabled Mapping
IDT79R3500 RISC PROCESSOR RISCore
Operating Modes IDT79R3500 operating modes: User mode Kernel mode. IDT79R3500 normally operates User mode until exception detected forcing into Kernel mode. remains Kernel mode until Restore From Exception (RFE) instruction executed. manner which memory addresses translated mapped depends operating mode IDT79R3500. Figure shows translation performed each operating modes. User Mode-in this mode, single, uniform virtual address space (kuseg) available. When used, each virtual address extended with 6-bit process identifier field form unique virtual addresses. references this segment mapped through TLB. cache processes determined settings each page within entries. used, these addresses translated begin physical address space. Kernel Mode-four separate segments defined this mode: kuseg-when kernel mode, references this segment treated just like user mode references, thus streamlining kernel access user data. kseg0-references this 512MB segment cache memory mapped through TLB. Instead, they always first 0.5GB physical address space. kseg1-references this 512MB segment mapped through cache. Instead, they hard-mapped into same 0.5GB segment physical address space kseg0. kseg2-when used, references this segment directly addresses upper physical address space. These addresses defined kernel mode which cacheable. When used, references this segment always mapped through cache determined settings within entry.
Load, Store, Move Operation Load, Store, Move operations data between memory integer registers registers. These operations perform format conversions cause floatingpoint exceptions. Load, Store, Move operations reference single 32-bit word either Floating-Point General Registers (FGR) Floating-Point Control Registers (FCR). Floating-Point Operations supports following single- double-precision format floating-point operations: Subtract Multiply Divide Absolute Value Move Negate Compare addition, supports conversions between singleand double-precision floating-point formats fixed-point formats. incorporates separate Add/Subtract, Multiply, Divide units, each capable independent concurrent operation. Thus, achieve very high performance, floating point divides overlapped with floating point multiplies floating point additions. These floating point operations occur independently actions CPU, allowing further overlap integer floating point operations. Figure illustrates example types overlap permissible. Exceptions supports five IEEE standard exceptions: Invalid Operation Inexact Operation Division Zero Overflow Underflow also suppoerts optional, Unimplemented Operation exception that allows unimplemented instructions trap software emulation routines. provides precise exception capability CPU; that execution floating point operation which generates exception causes that exception occur instruction which caused operation. This precise exception capability requirement applications languages which provide mechanism local software exception handlers within software modules.
COPROCESSOR OPERATION (CP1)
continually monitors processor instruction stream. instruction does apply coprocessor, ignored; instruction does apply coprocessor, executes that instruction transfers necessary result exception data synchronously main processor. performs three types operations: Loads Stores; Moves; Two- three-register floating-point operations.
IDT79R3500 RISC PROCESSOR RISCore
DIV.S MUL.S
STORE (SWC1) MUL.S Only Load, Store, Move operations permitted during these cycles. Other instructions proceed during these cycles. However, multiply divide operation cannot overlapped. These cycles free integer operations CPU. ADD.S STORE (SWC1) LOAD (LWC1) STORE (SWC1)
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Figure Examples Overlapping Floating Point Operation
I-Cache
D-Cache
Register file write back exceptions
*FpWB
Cycle
Figure Instruction Execution
only
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*FWB
*FWB
*FWB
Instruction Flow
*FWB
*FWB
*FWB
Current Cycle
Figure IDT79R3500 Execution Sequence
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IDT79R3500 RISC PROCESSOR RISCore
IDT79R3500 PIPELINE ARCHITECTURE
execution single IDT79R3500 integer instruction consists five pipe stages while floating point instruction takes pipe stages. They are: IF-Instruction fetch. processor calculates instruction address required read from cache. RD-The instruction present data during phase this pipe stage. Instruction decode occurs during phase two. Operands read from registers required. ALU-Perform required operation instruction operands. this instruction, instruction execution commences. MEM-Access memory. instruction load store, data presented captured during phase this pipe stage. WB-Write integer results back into register file. cycles this pipe stage used exceptions. FWB-The uses this stage write back results register file. Each these steps requires approximately cycle shown Figure (parts some operations spill over into another cycle while other operations require only cycle.) uses five stage pipeline while while uses stage achieve instruction execution rate approaching instruction cycle. Thus, execution instructions time overlapped shown Figure This pipeline operates efficiently because different resources (address data accesses, operations, register accesses, utilized non-interfering basis.
Microprocessor (CPU) Data Address
Memory (and I/O)
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Figure Simple Microprocessor Memory System
Figure illustrates memory system that supports significantly greater memory bandwidth required take full advantage IDT79R3500's performance capabilities. features this system are:
IDT79R3500A Microprocessor Data Address
Instruction Cache
Data Cache
MEMORY SYSTEM HIERARCHY
high performance capabilities IDT79R3500 processor demand system configurations incorporating techniques frequently employed large, mainframe computers seldom encountered systems based more traditional microprocessors. primary goal systems employing RISC techniques minimize average number cycles each instruction requires execution. Techniques reduce cycles-perinstruction include compact uniform instruction set, deep instruction pipeline described above), utilization optimizing compilers. Many advantages obtained from these techniques can, however, negated inefficient memory system. Figure illustrates memory simple microprocessor system. this system, outputs addresses memory reads instructions data from memory writes data memory. address space completely undifferentiated: instructions, data, devices treated same. such system, primary limiting performance factor memory bandwidth.
Write Buffer
Data Main Memory
Address
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Figure IDT79R3500 System with High-Performance Memory System
IDT79R3500 RISC PROCESSOR RISCore
External Cache Memory-Local, high-speed memory (called cache memory) used hold instructions data that repetitively accessed (for example, within program loop) thus reduces number references that must made slower-speed main memory. Some microprocessors provide limited amount cache memory chip itself. external caches supported IDT79R3500 much larger; while small cache improve performance some programs, significant improvements wide range programs require large caches. Separate Caches data Instructions-Even with high-speed caches, memory speed still limiting factor because fast cycle time high-performance microprocessor. IDT79R3500 supports separate caches instructions data alternates accesses caches during each cycle. Thus, processor obtain data instructions cycle rate using caches constructed with commercially available static devices. order maximize bandwidth cache while minimizing requirement SRAM access speed, IDT79RR3500 divides single-processor clock cycle into phases. During phase, address data cache access presented while data previously addressed instruction cache read; during next phase, data operation completed while instruction cache being addressed. Thus, both caches read single processor cycle using only address data pins. Write Buffer-in order ensure data consistency, data that written data cache must also written main memory. cache write model used IDT79R3500 that write-through cache; that data written immediately written into main memory. relieve this responsibility (and inherent performance burden) IDT79R3500 supports interface write buffer. IDT79R3020 Write Buffer captures data (and associated addresses) output ensures that data passed main memory. IDT79R3500 Processor Subsystem Interfaces Figure illustrates three subsystem interfaces provided IDT79R3500 processor: Cache control interface (on-chip) separate data instruction caches permits implementation off-chip caches using standard SRAM devices. IDT79R3500 directly controls cache memory with minimum external components. Both instruction data cache vary from 256kB (64K entries). IDT79R3500 also includes control logic which determines whether entry read from cache desired data. IDT79RR3500 implements advanced feature that allows certain comparisons
eliminated, which turn reduces number cache SRAMs required. Int(5) reset mode vector contains bits which sets comparison options. Table illustrates disable encoding. first table implements standard IDT79R3000A operating mode where parity used. second eliminates upper bits, eliminating normally required SRAMs limiting main memory addressing 128mB. third elimnates lower bits, which requires cache least 64kB each. fourth eliminates upper lower bits, requiring least cache entries, limits main memory addressing 128mB. cases, IDT79R3500 continues check parity which selected driven from cache. IDT79R3500 cache controller implements direct mapped cache high performance (bandwidth). ability refill multiple words when cache miss occurs, thus reducing effective miss rate less than large caches. When cache miss occurs, IDT79R3500 support refilling cache word blocks minimize effective penalty having access main memory. IDT79R3500 also incorporates ability perform instruction streaming; while cache refilling, processor resume execution once missed word obtained from main memory. this way, processor continue execute concurrently with cache block refill. Memory controller interface system (main) memory. This interface also includes logic signals allow operation with write buffer further improve memory bandwidth. addition standard full word access, memory controller supports ability write bytes half-words using partial word operations. memory controller also supports ability retry memory accesses example, data returned from memory invalid error needs signalled. Coprocessor Interface-The IDT79R3500 features board tightly coupled coprocessors. Coprocessor defined system control coprocessor Coprocessor Floating Point Accelerator. They have direct access internal data which allows them direct load store data same fashion accessing registers. This relieves typical bottleneck having load data into register then passing that data co-processors. applications where chip, using IDT79R3010A, several control pins were used communications with Phase Lock Loop located IDT79R3010A synchronize together. they integrated into single chip, these longer needed. FpCond output, which used coprocessor branch instructions, internally tied CpCond(1) input leaving external CpCond(1) available another function. This signal selectable either output FpBusy Fplnt.
IDT79R3500 RISC PROCESSOR RISCore
Cond(1) output selection determined reset time according value read Int(4). Table illustrates options that allow FpInt routed either CpCond(1) output, internal pins. internally routed, that interrupt dedicated that input will longer affect IDT79R3500. selection using CpCond(1) allows some external Logic added path, which might required some applications. Another method Fpint handling also accommodated. mode pin, previously programmed route interrupt dedicated Fpint output that
previously GND. mode sampled reset dedicated Fpint indicates interrupt then routing Table applies. internal CPBusy input, which used stall coprocessor needs hold subsequent operations, sources-FPBusy external CpBusy which logically ORed together. Further, Exception both internally tied brought with external CPBusy input accommodate chip coprocessor This external interface available support application specific functions.
MULTIPROCESSING SUPPORT
Mode Mode Check Which TAGs (31:12) (27:12) (31:16) (27:16) Ignore Which Tags None (31:28) (15:12) (31:28;15:12)
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Table Disable Encoding
Cycle "LOW" "LOW"
Cycle
Cycle
Cycle "HIGH" "LOW" "LOW" "LOW" "LOW"
Action FPint driven onto CpCond(1) Int(3) Fpint Int(1) Fpint Int(2) Fpint Int(0) Fpint Int(4) Fpint Int(5) Fpint Reserved, Undefined Reserved, Undefined
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"LOW" "LOW"
"LOW" "HIGH" "LOW"
"LOW" "HIGH" "LOW" "HIGH" "LOW" "LOW" "HIGH" "HIGH" "LOW"
IDT79R3500 supports multiprocessing applications simple effective way. Multiprocessing applications require cache coherency across multiple processors. IDT79R3500 offers signals support cache coherency: first, MPStall, stalls processor within cycles being received keeps from accessing cache. This allows external agent snoop into processor data cache. second signal, MPInvalidate, causes processor write data data cache which indicates externally addressed cache entry invalid. Thus, subsequent access that location would result cache miss, data would obtained from main memory. signals would generated external logic which utilizes secondary cache perform snooping functions. IDT79R3500 does impose architecture this secondary cache, rather flexible enough support variety application specific architectures still maintain cache coherency. Further, there impact designs which require this feature. IDT79R3500 further allows cache RAMs with internal address latches multiprocessor systems.
"LOW" "HIGH" "HIGH" "LOW" "HIGH" "LOW" "HIGH" "LOW" "HIGH" "HIGH" "HIGH" "LOW"
ADVANCED FEATURES
IDT79R3500 offers number additional features such ability swap instruction data caches, facilitating diagnostics cache flushing. Another feature isolates the, caches, which forces cache hits occur regardless contents fields. IDT79R3500 allows processor execute user tasks opposite byte ordering (endianness) operating system, programmable width bus, further allows certain parity checking disabled. More details these features found IDT79R3000A Family Hardware User's Manual. Further features IDT79R3500 configured during last four cycles prior negation RESET input. These functions include ability select cache sizes cache refill block sizes; ability utilize multiprocessor interface; whether instruction streaming enabled; whether byte ordering follows "Big-Endian" "Little-Endian" protocols, etc. Additionally, IDT79R3500 mode must
Table Int(4) Encoding Fpint
IDT79R3500 RISC PROCESSOR RISCore
true enable features that X,Y, cycles define. Table shows configuration options selected Reset. These further discussed IDT79R3000A Family Hardware User's Manual.
BACKWARD COMPATIBILITY
primary goal IDT79R3500 ability replace IDT79R3000A IDT79R3010A with single chip solution. pinout IDT79R3500 been selected ensure this compatibility, with functions mapped onto previously used pins. instruction compatible with that R2000 binary level. result, code written older processor executed. most IDT79R3000A applications, IDT79R3500 placed socket with modification initialization settings. Additionally, IDT79R3500 used systems that include IDT79R3010 original design. Further application assistance these topics available from IDT.
packaging. addition, these packages incorporate coppertungsten thermal slug designed efficiently transfer heat from case package, thus effectively lower thermal resistance package. additional external heat sink affixed package thermal slug further decreases effective thermal resistance package. case temperature measured environment determine whether device within specified operating range. case temperature should measured center surface opposite package cavity (the package cavity side where package mounted). equivalent allowable ambient temperature, calculated using thermal resistance from case ambient (ca) given package. following equation relates ambient case temperature: P*ca where maximum power consumption, calculated using maximum from Electrical Characteristics section. Typical values various airflows shown Table various packages.
PACKAGE THERMAL SPECIFICATIONS
IDT79R3500 utilizes special packaging techniques improve both thermal electrical characteristics microprocessor. order improve electrical characteristics device, package constructed using multiple signal planes, including individual power planes ground planes reduce noise associated with high-frequency parts. addition, 161-pin package utilizes extra power ground pins reduce inductance from internal power planes power planes Board. order improve thermal characteristics microprocessor, device housed using cavity down
Airflow (ft/min) (161-PGA) (160 MQUAD) 1000
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Table R3500 Package Characteristics
Input Int0 Int1 Int2 Int3 Int4 Int5
Cycle DBIkSize0 IBIkSize0 DispPar/RevEnd Reserved(1) FPINT decode 7R3500 mode
Cycle DBIkSize1 IBIkSize1 IStream StorePartial FPINT decode disable
Cycle Extend Cache MPAdrDisable IgnoreParity MultiProcessor FPINT decode Mode
Cycle Endian TriState NoCache BusDriveOn FPINT onto CpCond Mode
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NOTES: Reserved entries must driven high. These values must driven stable throughout enfire RESET period. Table R3500 Mode Selectable Features
IDT79R3500 RISC PROCESSOR RISCore
Data AdrLo
Data AdrLo TagV TagP Transparent Latch IClk AdrLo Data DataP Transparent Latch
Data
DClk
Data
IAdr [15:2]
IDT79R3500A Processor with System Control Coprocessor
DAdr [15:2]
Data
Instruction Cache
Data Cache
Clk2xSys SysOut AccTy(2:0) Memory Interface MemRd MemWr RdBusy WrBusy CpCond(0) BusError Clk2xSmp Clk2Rd Clk2xPhi Reset CpSync CpBusy CpCond[2:3] Int[5:0] Hardware Interrupts
Figure IDT79R3500 Subsystem Interfaces Example; Caches
Clocks
Coprocessors
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IDT79R3500 RISC PROCESSOR RISCore
CONFIGURATION
Pin) AdrLo AdrLo Data DataP AdrLo AdrLo AdrLo Mode AdrLo AdrLo AdrLo AdrLo AdrLo Busy
AdrLo CpCond AdrLo AdrLo CpCond
Int(2)
Busy Busy
Int(5) Error
Reset
Tag12
DRd2
AdrLo AdrLo Data Data Data Data DataP Data Data Data Data Data Data
AdrLo AdrLo
IRd2
Int(1) Int(0)
Int(3) Int(4)
DWr2
Tag15
Tag13 TagP0
Tag18
FpInt
AdrLo Data
Tag14
Tag17
Tag19
Tag16
Tag20
Tag21
Tag23
Data Data Data Data
Tag22
TagP1
Data Data
Tag25
Tag24
Tag28
Tag29
Tag26
TagP2
Tag27
Data DataP Data
Typ2
Tag31
Tag30
Data Data Data
Typ1
Data Data Data
DataP 161-Pin (Top View) Data
DRd1
DClk
IRd1
IWr1
IClk
Sync DWr1
TagV
IWr2
Data
Data Data
Data
Data
Clk2x Clk2x
Clk2x Clk2x
Typ0
2871
Exception
SysOut
NOTE: AdrLo multifunction pins which controlled mode select programming interrupt pins reset time AdrLo Invalidate, CpCond (2). AdrLo Stall, CpCond (3). This package pin-compatible with 175-pin R3000A.
IDT79R3500 RISC PROCESSOR RISCore
CONFIGURATION
Tag(12) Tag(13) Tag(14) Tag(15) TagP(0) Tag(16) Tag(17) Tag(18) Tag(19) Tag(20) Tag(21) Tag(22) Tag(23) TagP(1) Tag(24) Tag(25) Tag(26) Tag(27) Tag(28) Tag(29) Tag(30) TagP(2) Tag(31) TagV AccTyp(2) AccTyp(1) AccTyp(0)
Reset Error
RdBusy CpBusy
WrBusy Int(5) Int(4) Int(3) Int(2) Int(1)
CpSync MemRd MemWr DWr(1) DWr(2) IWr(1) IWr(2) DRd(1) DRd(2) IRd(1) IRd(2)
IClk DClk
AdrLo(17) AdrLo(16) CpCond(1) CpCond(0) AdrLo(15) Mode AdrLo(14) AdrLo(13) AdrLo(12) AdrLo(11) AdrLo(10) AdrLo(9) AdrLo(8) AdrLo(7) AdrLo(6) AdrLo(5)
SysOut
EIAJ MQUAD Side View (Cavity Down) Clk2xRd Clk2xSys Clk2xSmp Clk2xPhi
FPInt
Exception
Data(30) Data(29)
Data(28) Data(27) DataP(3) Data(31) Data(26) Data(25) Data(24) Data(22) Data(21)
AdrLo(4) AdrLo(3) AdrLo(2) AdrLo(1) AdrLo(0) Data(0) Data(1) Data(2) Data(7) DataP(0) Data(3) Data(4) Data(5) Data(6) Data(8) Data(9) Data(10) Data(15) DataP(1) Data(11) Data(12) Data(13) Data(14) Data(16) Data(17) Data(18) Data(23) DataP(2) Data(19) Data(20)
NOTE: AdrLo multifunction pins which controlled mode select programming interrupt pins reset time AdrLo Invalidate, CpCond (2). AdrLo Stall, CpCond (3). This package pin-compatible with 175-pin R3000A.
2860
IDT79R3500 RISC PROCESSOR RISCore
CONFIGURATION
Reset* BusError* RdBusy* WrBusy* CpBusy Int5* Int4* Int3* Int2* Int1* Int0* AdrLo17 AdrLo16 FPINT Resvd1 CpCond1 CpCond0 AdrLo15 MODE AdrLo14 AdrLo13 AdrLo12 AdrLo11 AdrLo10 AdrLo9 AdrLo8 AdrLo7 AdrLo6 AdrLo5 AdrLo4 AdrLo3 AdrLo2
Tag12 Tag13 Tag14 Tag15 TagP0 Tag16 Tag17 Tag18 Tag19 Tag20 Tag21 Tag22 Tag23 TagP1 Resvd2 Tag24 Tag25 Tag26 Tag27 Tag28 Tag29 Tag30 TagP2 Tag31 TagV AccTyp2 AccTyp1 AccTyp0 Run* CpSync* MemRd*
IDT79R3500 172-Pin Flatpack View (Cavity
AdrLo1 AdrLo0 Data0 Data1 Data2 Data7 DataP0 Data3 Data4 Data5 Data6 Data8 Data9 Data10 Resvd0 Data15 DataP1 Data11 Data12 Data13 Data14 Data16 Data17 Data18 Data23 DataP2 Data19 Data20
MemWr* DWr2* IWr2* DRd2* IRd2* IClk DClk SysOut* Clk2xRd DWr1* IWr1* DRd1* IRd1* Clk2xSys CLK2xSmp Clk2xPhi Exc* Data30 Data29 XEn* Data28 Data27 DataP3 Data31 Data26 Data25 Data24 Data22 Data21
2871
IDT79R3500 RISC PROCESSOR RISCore
DESCRIPTIONS
Name Data (0-31) DataP (0-3) (12-31) TagV (0-2) AdrLo (0-17) Description 32-bit used instruction data transmission among processor, caches, memory interface, coprocessors. 4-bit containing even parity over data bus. 20-bit used transferring cache tags high addresses between processor, caches, memory interface. validity indicator. 3-bit containing even parity over concatenation TagV Tag. 18-bit containing byte addresses used transferring addresses from processor caches memory interface. (AdrLo CpCond (2), AdrLo CpCond reset initialization). Read enable instruction cache. Write enable instructon cache. identical copy IWr1 used split load. read enable data cache. write enable data cache. identical copy DWr1 used split load. read enable Read Buffer. 3-bit used indicate size data being transferred data bus, whether data transfer occurring, purpose transfer. Signals occurrence main memory write. Signals occurrence main memory read. Signals occurrence error during main memory read write. Indicates whether processor STALL state. discrete design, R3000 output tied directly R3010 input. theIDT79 R3500, this done internally, signal also brought application specific coprocessors. Indicates that instruction that about commit state change should aborted; also indicates other exception related information. discrete design, R3000 Exception output tied IDT79R3010 Exception input. IDT79R3500 this done internally, Exception signal also brought application specific coprocessors. clock which identical SysOut used external coprocessors timing synchronization with IDT79R3500. discrete design, CpSync output from IDT79R3000 tied IDT79R3010 FPSync input. IDT79R3500, this done internally, CpSync signal also brought application specific coprocessors. main memory read stall termination signal. most system designs RdBusy normally asserted deasserted only indicate successful completion memory read. RdBusy sampled processor only during memory read stalls. main memory write stall initiation/termination signal. Input used indicate that requested coprocessor resource unavailable, used preserve precise exception model. descrete design, CpBusy driven directly R3010 FpBusy output. IDT79R3500 CpBusy input logical both internal FpBusy external CpBusy pin. This input provided external application specific coprocessors. internal pull down resistor provided this input left open. Signal used branch Coprocessor true/false instruction. discrete systems using IDT79R3010 FPA, this normally tied FpCond output. IDT79R3500, internal FpCond directly tied internal CpCond(1) input leaving this available other functions.This defaults output FpBusy internal signal (via Reset vectors), output FPInt-in latter case, external hardware must route this signal appropriate pin. Conditional branch status from coprocessors processor. Function provided AdrLo 16/17 pins selected reset time. identical copy DRd1 used split load. identical copy IRd1 used split load.
IRd1 IWr1 IRd2 IWr2
ICIk
instruction cache address latch clock. This clock runs continuously.
DRd1 DWr1 DRd2 DWr2
DCIk
data cache address latch clock. This clock runs continuously.
AccTyp(0-2)
MemWr MemRd BusError Exception
CpSync
RdBusy
WrBusy CpBusy
CpCond(1)
CpCond (0,2-3)
IDT79R3500 RISC PROCESSOR RISCore
DESCRIPTIONS (CONT.)
Name MPStall MPInvalidate Description Multiprocessing Stall. Signals processor that should stall accesses caches multiprocessing environment. This physically same CpCond3; determined RESET initialization. Multiprocessing Invalidate. Signals processor that should issue invalidate data cache data bus. address invalidated externally provided. This same CpCond2; determined RESET initialization. 6-bit used memory interface coprocessors signal maskable interrupts IDT79R3500. This also used reset time select among mode-selectable features IDT79R3500. FPInt output signal typically connected these interrupt lines; choice programmable through reset vectors with default being Int(3). master double frequency input clock used generating SysOut. double frequency clock input used determine sample point data coming into processor coprocessors. double frequency clock input used determine enable time cache RAMs. double frequency clock input used determine position internal phases, phase1 phase2. Synchronous initialization input used force execution starting from reset memory address. Reset must deasseted synchronously asserted asynchronously. deassertion Reset must synchronized leading edge SysOut. mode input sampled rising edge reset, connection between FpInt interrrupt will established interrept reset vector. should used establish this option. mode sampled rising edge reset, FpInt will output, must externally connected back interrupt input pin. Ground should used select this option. mode sampled rising edge reset, this signal will FPInt output from core IDT79R3500, must externally connected back interrupt pin. mode sampled rising edge reset, this should grounded.
(0-5)
CIk2xSys CIk2xSmp CIk2xRd CIk2xPhi
Reset
Mode
FPINT
ABSOLUTE MAXIMUM RATINGS Symbol Rating VTERM Terminal Voltage with Respect Operating Temperature Commercial Military Unit -0.5 +7.0 -0.5 +7.0
RECOMMENDED OPERATING TEMPERATURE SUPPLY VOLTAGE
Grade Military 20-25 Commercial 20-33 Commercial Temperature -55°C +125°C (Case) +70°C (Ambient) +90°C (Case) ±10%
2871
TBIAS TSTG
+70(4) +125 (Ambient) (Case) +90(5) (Case) Case Temperature +125 +135 Under Bias +90(5) Storage +125 +155 Temperature Input Voltage -0.5 +7.0 -0.5 +7.0
2871 NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. minimum -3.0V pulse width less than 15ns. should exceed +0.5 Volts. more than output should shorted time. Duration short should exceed seconds. 16-33 only. 37-40 only.
IDT79R3500 RISC PROCESSOR RISCore
TEST CONDITIONS
Symbol VIHS VILS Parameter Input HIGH Voltage Input Voltage Input HIGH Voltage Input Voltage Min. Max. Unit
2871
OUTPUT LOADING TESTING
+4mA
+1.5V
Device Under Test 25pF
-4mA
2871
ELECTRICAL CHARACTERISTICS COMMERCIAL TEMPERATURE RANGE(TA +70°C, +5.0V ±5%)
79R3500 20.0MHz Symbol VOHC VOHT VOLT VIHS VILS COUT Parameter Output HIGH Voltage Output Voltage Output HIGH Output HIGH Output Input HIGH
Voltage (4.6) Voltage (4.6) Voltage
25.0MHz Min. -100 -100 Max.
33.33MHz Min. -100 -100 Max. Unit
Test Conditions Min., -4mA Min., Min., -4mA Min., -8mA Min.,
Min.
Max.
Voltage
Input Voltage (2,5) Input HIGH Voltage
Input Input Output
(1,2) Voltage
Capacitance Capacitance
Operating Current Input HIGH Input
Leakage Leakage
70°C VCC,
-100 -100
Output Tri-state Leakage
2871 NOTES: Min. -3.0V pulse width less than 15ns.ILVshould fall below -0.5 Volts larger periods. Reset. VIHS VILS apply CIk2xSys, CIk2xSmp, CIk2xRd, CIk2xPhi, CpBusy, These parameters apply clock inputs. VOHT VOLT apply bidirectional data busses only. Note that also apply these signals. VOLT provided give designer further information about these specific signals. should held above volts. Guaranteed design. VOHC applies toRUN Exception
IDT79R3500 RISC PROCESSOR RISCore
ELECTRICAL CHARACTERISTICS MILITARY TEMPERATURE RANGE -55°C +125°C, +5.0V ±10%)
79R3500 20.0MHz Symbol VOHC VOHT VOLT VIHS VILS COUT Parameter Output HIGH Voltage Output Voltage Output HIGH Output HIGH
Voltage (4,6) Voltage
25.0MHz Min. -100 -100 Max. Unit
Test Conditions Min., -4mA Min., Min., -4mA Min., -8mA Min.,
Min.
Max.
(4,6) Output Voltage Input HIGH Voltage
Input Input HIGH
Voltage (2,5) Voltage
(1,2) Input Voltage Input Capacitance Output Capacitance
Operating Current Input HIGH Input
Leakage Leakage
70°C VCC,
-100 -100
Output Tri-state Leakage
2871 NOTES: Min. -3.0V pulse width less than 15ns.ILVshould fall below -0.5 Volts larger periods. Reset. VIHS VILS apply CIk2xSys, CIk2xSmp, CIk2xRd, CIk2xPhi, CpBusy, These parameters apply clock inputs. also apply these signals. provided VOHT VOLT apply bidirectional data busses only. Note that give designer further information about these specific signals. should held above volts. Tested only initially, after design changes which affect capacitance. VOHC applies toRUN Exception
IDT79R3500 RISC PROCESSOR RISCore
ELECTRICAL CHARACTERISTICS COMMERCIAL TEMPERATURE RANGE +90°C, +5.0V ±5%)
79R3500 40.0MHz Symbol VOHC VOHT VOLT VIHS VILS COUT Parameter Output HIGH Voltage Output Voltage Output HIGH Output HIGH Output Input HIGH Input
Voltage (4,6) Voltage (4,6) Voltage
Test Conditions Min., -4mA Min., Min., -4mA Min., -8mA Min.,
Min.
Max.
Unit
2871
Voltage Voltage
(2,5) Input HIGH Voltage (1,2) Input Voltage Input Capacitance Output Capacitance
Operating Current
Input HIGH Leakage
70°C VCC,
-100 -100
Input
Leakage
Output Tri-state Leakage
NOTES: Min. -3.0V pulse width less than 15ns.ILVshould fall below -0.5 Volts larger periods. Reset. VIHS VILS apply CIk2xSys, CIk2xSmp, CIk2xRd, CIk2xPhi, CpBusy, These parameters apply clock inputs. also apply these signals. VOLT provided VOHT VOLT apply bidirectional data busses only. Note that give designer further information about these specific signals. should held above volts. Guaranteed design. VOHC applies toRUN Exception
IDT79R3500 RISC PROCESSOR RISCore
ELECTRICAL CHARACTERISTICS(1,2,3) COMMERCIAL TEMPERATURE RANGE(TA +70°C, +5.0V ±5%)
20.0MHz Min. Max. Load= 25pF Load= 25pF -2.5 -2.5 -2.5 Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF 3000 tcyc/4 tcyc/4 tcyc/4 -2.0 -1.0 79R3500 25.0MHz Min. Max. -2.5 -2.5 -2.5 3000 tcyc/4 tcyc/4 tcyc/4 -1.5 -0.5 33.33MHz Min. -2.5 -2.5 -2.5 3000 Max. tcyc/4 tcyc/4 tcyc/4 -1.5 -0.5 13.5 13.5 Unit
Symbol Clock
Parameter
Test Conditions Note Note
TCkHigh Input Clock HIGH TCkLow Input Clock TCkP Input Clock Period CIk2xSys CIk2xSmp CIk2xSmp CIk2xRd CIk2xSmp Clk2xPhi Operation TDEn Data Enable TDDIs Data Disable
TDVal TWrDly TCBS TCBH TAcTy TAT2 TMWr TExc TAval TIntS TIntH TFpbusy Tfpint
Data Valid Write Delay Data Set-up Data Hold(3) CpBusy Set-up CpBusy Hold Access Type (1:0) Access Type Memory Write Exception Address Valid Int(n) Set-up Int(n) Hold
Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF
Stall Operation TSAVal Address Valid TSAcTy Access Type TMRdi TMRdt TStl Memory Read Initiate Memory Read Terminate Terminate
Tcyc Tcyc ns/25pF
2871
TRun Initiate TSMWr Memory Write TSExc Exception Valid Reset Initialization TRST Reset Pulse Width TprwOn Power Capacitive Load Deration
Load Derate
NOTES: timings referenced 1.5V. clock parameters apply four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi. This parameter guaranteed design. Tcyc clock cycle (two cycles clock). signal, signals given device will derate given load difference greater than 15%. With exception Clock transition time 2.5ns 33.33MHz; clock transition time other speeds.
IDT79R3500 RISC PROCESSOR RISCore
ELECTRICAL MILITARY TEMPERATURE RANGE -55°C +125°C, +5.0V ±10%)
79R3500 20.0MHz Symbol Parameter Clock TCkHigh Input Clock HIGH TCkLow Input Clock TCkP Input Clock Period CIk2xSys CIk2xSmp CIk2xSmp CIk2xRd CIk2xSmp Clk2xPhi Operation Data Enable TDEn TDDIs Data Disable TDVal TWrDly TCBS TCBH TAcTy TAT2 TMWr TExc TAval TIntS TIntH Data Valid Write Delay Data Set-up Data Hold(3) CpBusy Set-up CpBusy Hold Access Type (1:0) Access Type Memory Write Exception Address Valid Int(n) Set-up Int(n) Hold Test Conditions Note Note Min. Load= 25pF Load= 25pF -1.5 -1.5 -1.5 3000 Max. tcyc/4 tcyc/4 tcyc/4 -2.0 -1.0 Min. -1.5 -1.5 -1.5 3000 25.0MHz Max. tcyc/4 tcyc/4 tcyc/4 -1.5 -0.5 Unit Tcyc Tcyc ns/25pF
2871
CHARACTERISTICS(1,2,3)
Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF
Stall Operation TSAVal Address Valid TSAcTy Access Type TMRdi TMRdt TStl Memory Read Initiate Memory Read Terminate Terminate
Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF
Initiate TRun TSMWr Memory Write TSExc Exception Valid Reset Initialization Reset Pulse Width TRST TpwrOn Power Capacitive Load Deration
Load Derate
NOTES: timings referenced 1.5V. clock parameters apply four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi. This parameter guaranteed design. Tcyc clock cycle (two cycles clock). signal, signals given device will derate given load difference greater than 15%. With exception Clock transition time 2.5ns 33.33MHz; clock transition time other speeds.
IDT79R3500 RISC PROCESSOR RISCore
ELECTRICAL CHARACTERISTICS(1,2,3) COMMERCIAL TEMPERATURE RANGE +90°C, +5.0V ±5%)
79R3500 40.0MHz Symbol Parameter Test Conditions Note Note Min. 12.5 -2.5 -2.5 -2.5 Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF 3000 Max. tcyc/4 tcyc/4 tcyc/4 -1.5 -0.5 12.5 Unit Tcyc Tcyc ns/25pF
2871
Clock TCkHigh Input Clock HIGH TCkLow Input Clock Input Clock Period TCkP CIk2xSys CIk2xSmp CIk2xSmp CIk2xRd CIk2xSmp Clk2xPhi Operation TDEn TDDIs TDVal TWrDly TCBS TCBH TAcTy TAT2 TMWr TExc TAval TIntS Data Data Valid
Disable
Data Enable
Load= 25pF Load= 25pF
Write Delay Data Set-up Data Hold(3) CpBusy Set-up CpBusy Hold Access Type (1:0) Access Type Memory Write Exception Address Valid Int(n) Set-up
Load= 25pF Load= 25pF Load= 25pF Load= 25pF Load= 25pF
Int(n) Hold TIntH Tfpbusy Tfpint Stall Operation TSAVal Address Valid TSAcTy Access Type TMRdi TMRdt TStl TRun Memory Read Initiate Memory Read Terminate Terminate Initiate
TSMWr Memory Write TSExc Exception Valid Reset Initialization TRST Reset Pulse Width TpwrOn Power Capacitive Load Deration
Load Derate
On(4)
NOTES: timings referenced 1.5V. clock parameters apply four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi. This parameter guaranteed design. Tcyc clock cycle (two cycles clock). signal, signals given device will derate given load difference greater than 15%. With exception Clock transition time 2.5ns.
IDT79R3500 RISC PROCESSOR RISCore
Phase
Tsys Tsys
FpSysOut Tsys FpPhiOut
Tsys
FpInt Tfpint
FpInt Tfpint
2873
Figure Floating Point Interrupt
Phase
Tsys Tsys
FpSysOut Tsys FpPhiOut
Tsys
Tfpbusy FpBusy
Tfpbusy
Texh Exception TSExS TStallS TStallH
TRExS
TExH
2873
Figure Floating Point Busy
IDT79R3500 RISC PROCESSOR RISCore
Tcklow Clk2xSys
Tckp
Tckhigh
Tsmp Clk2xSmd Clk2xRd Tsys Clk2xPhi
2871
Figure Input Clock Timing
Tcyc SysOut Tsmp SmpOut* RdOut* Tsys PhiOut* Tsys
2871
Tsmp
Figure Processor Reference Clock Timing These signals actually output from processor. They drawn provide reference other timing diagrams.
IDT79R3500 RISC PROCESSOR RISCore
Phase
Tsys Tsys
SysOut Tsys PhiOut Taval AddrLo Addr Tacty AccTyp Tacty2 AccTyp Input Data Buses Tsmp IClk DClk Tdval Tddis Taval
Tsys
Taval Addr
Taval Addr
Addr
Size Stored Data
Size Load Data
Output Tden
Input
Input
Tsmp Tsmp
Tsmp
Tsys Tsmp Twrdly
2871
Tsmp
Tsys
Figure Synchronous Memory (Cache) Timing
IDT79R3500 RISC PROCESSOR RISCore
Phase
STALL
STALL
FIXUP
SysOut Tsys PhiOut
Tsys Tsys
Tsys Tsys
Tsys Tsys
Tsys
Tsaval AddrLo Addr Tdval (Address High) Addr Tddis Addr Tdval Addr Addr Tddis
Tden Tacty
Tacty Reserved
Tden
Tacty Data Size Tat2
AccTyp
Data Size Tat2 Tsacty Tsacty
AccTyp Tdval Data (Output) Tden Tsmp Twrdly Tmwr MemWr Tsmp WrBusy Tsmwr Tddis
Reserved Tdval Tddis
Tden
Tmwr
Tmwr
Tsmp
Trun
2871
Figure Memory Write Timing
IDT79R3500 RISC PROCESSOR RISCore
Phase
STALL
STALL
FIXUP
SysOut Tsys PhiOut
Tsys Tsys
Tsys Tsys
Tsys Tsys
Tsys
Tsaval AddrLo Addr Addr Tdval (Address High) Tacty AccTyp Data Size Tat2 AccTyp Tsacty Tsacty Cached Data (Input) Tsmp Twrdly Tmrdi MemRd Tsmp RdBusy CpCond0 Tstl Tsmp Trun Tsys Tmrdt Tsmp Data Miss Read Address Tden Tden Tacty Data Size Tat2 Tddis Tacty Read Address Tdval Addr Addr Addr
2871
Figure Memory Read Timing
IDT79R3500 RISC PROCESSOR RISCore
Coprocessor Store
Coprocessor Load
Phase
Tsys Tsys
SysOut Tsys PhiOut Input Data Trun Tsmp Tdval Tddis
Tsys
Output Tden
Input
Input
Tsmp Tsmp Tstl
Tcbh CpBusy Tcbs Texc Exception Exc1W CpCond(n) Condition Valid
2871
IntGr2M Tsmp Tsys Exc1W IntGr2M
Figure Coprocessor Load/Store Timing
IDT79R3500 RISC PROCESSOR RISCore
Phase
Tsys Tsys
SysOut Tsys PhiOut
Tsys
Tsmp Int(n) TIntS TIntH TIntS
Tsmp TIntH
2871
Figure Interrupt Timing
Phase SysOut
Tsys Tsys
Tsys Tsys
Tsys Tsys
Tsys Tsys
Tsys Tsys
PhiOut Mode Cycle Modes Tsmp Int(n) TIntH TIntS Reset
2871
Cycle Modes Tsmp
Cycle Modes Tsmp TIntH TIntS
Cycle Modes Tsmp TIntH TIntS TIntH Tsmp
TIntS
Figure Mode Vector Initialization NOTES: SysOut Reset must negated synchronously; however, should asserted asynchronously. Designs must rely proper functioning prior assertion ofReset. Reset actually sampled both Phase Phase insure proper initialization, must negated relative Phase
IDT79R3500 RISC PROCESSOR RISCore
ORDERING INFORMATION
XXXXX Device Type Speed Package Process/ Temperature Range Blank Commercial (0°C +70°C) Military (-55°C +125°C) Compliant MIL-STD-883, Class Military Temperature Range Only 161-Pin (Cavity Down) 160-Pin MQUAD 172-pin Flatpack (Cavity 16.67 20.0 25.0 33.33 40.0
79R3500
RISCore Processor
2871
VALID COMBINATIONS
79R3500 20,25,33,40 79R3500 20,25,-B,M

RISC PROCESSOR RISCore IDT79R3500 Integrated Device Technolo

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