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Intel386EX Embedded Microprocessor User's Manual
Intel386EXTB Embedded Microprocessor Intel386EXTC Embedded Microprocessor
Intel386EX Embedded Microprocessor User's Manual
Information this document provided connection with Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes these specifications time, without notice. Microcontroller products have minor variations this specification known errata. *Other brands names property their respective owners. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation Literature Sales P.O. 7641 Prospect, 60056-7641 call 1-800-548-4725
COPYRIGHT INTEL CORPORATION,
CONTENTS
CHAPTER GUIDE THIS MANUAL MANUAL CONTENTS NOTATIONAL CONVENTIONS. SPECIAL TERMINOLOGY RELATED DOCUMENTS ELECTRONIC SUPPORT SYSTEMS 1.5.1 FaxBack Service .1-6 1.5.2 Bulletin Board System (BBS) .1-7 1.5.3 CompuServe Forums .1-7 1.5.4 World Wide .1-7 TECHNICAL SUPPORT PRODUCT LITERATURE. CHAPTER ARCHITECTURAL OVERVIEW Intel386 EMBEDDED PROCESSOR CORE. INTEGRATED PERIPHERALS. CHAPTER CORE OVERVIEW Intel386 PROCESSOR ENHANCEMENTS 3.1.1 System Management Mode .3-1 3.1.2 Additional Address Lines .3-1 Intel386 PROCESSOR INTERNAL ARCHITECTURE 3.2.1 Core Unit .3-4 3.2.2 Instruction Prefetch Unit .3-4 3.2.3 Instruction Decode Unit .3-4 3.2.4 Execution Unit .3-5 3.2.5 Segmentation Unit .3-5 3.2.6 Paging Unit .3-5 CORE Intel386 PROCESSOR INTERFACE. CHAPTER SYSTEM REGISTER ORGANIZATION OVERVIEW 4.1.1 Intel386 Processor Core Architecture Registers .4-2 4.1.2 Intel386 Processor Peripheral Registers .4-2 ADDRESS SPACE PC/AT SYSTEMS EXPANDED ADDRESS SPACE. ORGANIZATION PERIPHERAL REGISTERS ADDRESS DECODING TECHNIQUES. 4.5.1 Address Configuration Register .4-6
Intel386EX MICROPROCESSOR USER'S MANUAL
4.5.2 Enabling Disabling Expanded Space .4-8 4.5.2.1 Programming REMAPCFG Example .4-8 ADDRESSING MODES 4.6.1 DOS-compatible Mode .4-9 4.6.2 Nonintrusive Mode .4-11 4.6.3 Enhanced Mode .4-11 4.6.4 Non-DOS Mode .4-11 PERIPHERAL REGISTER ADDRESSES. 4-15 CHAPTER DEVICE CONFIGURATION INTRODUCTION PERIPHERAL CONFIGURATION 5.2.1 Controller, Arbiter, Refresh Unit Configuration .5-3 5.2.1.1 Using Unit with External Devices .5-3 5.2.1.2 Service SSIO Peripheral .5-3 5.2.1.3 Using Timer Initiate Transfers .5-4 5.2.1.4 Limitations Signal Multiplexing .5-4 5.2.2 Interrupt Control Unit Configuration .5-7 5.2.3 Timer/counter Unit Configuration .5-11 5.2.4 Asynchronous Serial Configuration .5-14 5.2.5 Synchronous Serial Configuration .5-18 5.2.6 Chip-select Unit Clock Power Management Unit Configuration .5-19 5.2.7 Core Configuration .5-21 CONFIGURATION. 5-23 DEVICE CONFIGURATION PROCEDURE 5-28 CONFIGURATION EXAMPLE. 5-28 5.5.1 Example Design Requirements .5-28 5.5.2 Example Design Solution .5-29 CHAPTER INTERFACE UNIT OVERVIEW 6.1.1 Signal Descriptions .6-3 OPERATION 6.2.1 States .6-7 6.2.2 Pipelining .6-8 6.2.3 Data Transfers Operand Alignment .6-9 6.2.4 Ready Logic .6-10 CYCLES 6-13 6.3.1 Read Cycle .6-13 6.3.2 Write Cycle .6-16 6.3.3 Pipelined Cycle .6-19
CONTENTS
6.3.4 Interrupt Acknowledge Cycle .6-23 6.3.5 Halt/Shutdown Cycle .6-26 6.3.6 Refresh Cycle .6-28 6.3.7 Cycle .6-31 6.3.7.1 Write Cycles .6-31 6.3.7.2 Read Cycles .6-31 LOCK. 6-34 6.4.1 Locked Cycle Activators .6-34 6.4.2 Locked Cycle Timing .6-34 6.4.3 LOCK# Signal Duration .6-35 EXTERNAL MASTER SUPPORT (USING HOLD, HLDA). 6-35 6.5.1 HOLD/HLDA Timing .6-36 6.5.2 HOLD Signal Latency .6-37 DESIGN CONSIDERATIONS. 6-38 6.6.1 Interface Intel387SX Math Coprocessor .6-38 6.6.1.1 System Configuration .6-39 6.6.1.2 Software Considerations .6-40 6.6.2 SRAM/FLASH Interface .6-41 6.6.3 PSRAM Interface .6-42 6.6.4 Paged DRAM Interface .6-43 6.6.5 Non-Paged DRAM Interface .6-44 CHAPTER SYSTEM MANAGEMENT MODE SYSTEM MANAGEMENT MODE OVERVIEW HARDWARE INTERFACE 7.2.1 System Management Interrupt Input (SMI#) .7-1 7.2.2 Active Output (SMIACT#) .7-2 7.2.3 System Management (SMRAM) .7-2 SYSTEM MANAGEMENT MODE PROGRAMMING CONFIGURATION. 7.3.1 Register Status During .7-3 7.3.2 System Management Interrupt .7-4 7.3.2.1 SMI# Priority .7-7 7.3.2.2 System Management Interrupt During HALT Cycle .7-8 7.3.2.3 HALT Restart .7-9 7.3.2.4 System Management Interrupt During Instruction .7-9 7.3.2.5 Restart .7-10 7.3.3 Handler Interruption .7-10 7.3.3.1 Interrupt During Handler .7-10 7.3.3.2 HALT During Handler .7-11 7.3.3.3 Idle Mode Powerdown Mode During .7-12 7.3.3.4 SMI# During Operation .7-12 7.3.4 SMRAM Programming .7-12 7.3.4.1 Chip-select Unit Support SMRAM .7-12
Intel386EX MICROPROCESSOR USER'S MANUAL
7.3.4.2 SMRAM State Dump Area .7-14 7.3.5 Resume Instruction (RSM) .7-15 Intel386 PROCESSOR IDENTIFIER REGISTERS 7-15 PROGRAMMING CONSIDERATIONS. 7-16 7.5.1 System Management Mode Code Example .7-16 CHAPTER CLOCK POWER MANAGEMENT UNIT OVERVIEW 8.1.1 Clock Generation Logic .8-1 8.1.2 Power Management Logic .8-3 8.1.2.1 Interaction with Power Management Modes .8-4 8.1.2.2 Interface Unit Operation During Idle Mode .8-5 8.1.2.3 Watchdog Timer Unit Operation During Idle Mode .8-5 8.1.3 Clock Power Management Registers Signals .8-6 CONTROLLING PSCLK FREQUENCY CONTROLLING POWER MANAGEMENT MODES 8.3.1 Idle Mode .8-9 8.3.2 Powerdown Mode .8-10 8.3.3 Ready Generation During HALT .8-10 DESIGN CONSIDERATIONS. 8-11 8.4.1 Reset Considerations .8-11 8.4.2 Power-up Considerations .8-12 8.4.2.1 Built-in Self Test .8-12 8.4.2.2 JTAG Reset .8-12 8.4.3 Powerdown Mode Idle Mode Considerations .8-13 PROGRAMMING CONSIDERATIONS. 8-13 8.5.1 Clock Power Management Unit Code Example .8-13 CHAPTER INTERRUPT CONTROL UNIT OVERVIEW OPERATION. 9.2.1 Interrupt Sources .9-4 9.2.2 Interrupt Priority .9-6 9.2.2.1 Assigning Interrupt Level .9-6 9.2.2.2 Determining Priority .9-7 9.2.3 Interrupt Vectors .9-8 9.2.4 Interrupt Process .9-9 9.2.5 Poll Mode .9-14 REGISTER DEFINITIONS. 9-15 9.3.1 Port Configuration Register (P3CFG) .9-18 9.3.2 Interrupt Configuration Register (INTCFG) .9-19
CONTENTS
9.3.3 Initialization Command Word (ICW1) .9-20 9.3.4 Initialization Command Word (ICW2) .9-21 9.3.5 Initialization Command Word (ICW3) .9-22 9.3.6 Initialization Command Word (ICW4) .9-24 9.3.7 Operation Command Word (OCW1) .9-25 9.3.8 Operation Command Word (OCW2) .9-26 9.3.9 Operation Command Word (OCW3) .9-27 9.3.10 Interrupt Request Register (IRR) .9-28 9.3.11 In-Service Register (ISR) .9-28 9.3.12 Poll Status Byte (POLL) .9-28 DESIGN CONSIDERATIONS. 9-29 9.4.1 Interrupt Acknowledge Cycle .9-29 9.4.2 Interrupt Detection .9-29 9.4.3 Spurious Interrupts .9-30 9.4.4 Cascading Interrupt Controllers .9-30 PROGRAMMING CONSIDERATIONS. 9-32 9.5.1 Interrupt Control Unit Code Examples .9-32 CHAPTER TIMER/COUNTER UNIT 10.1 OVERVIEW 10-1 10.1.1 Signals Registers .10-3 10.2 OPERATION 10-5 10.2.1 Mode Interrupt Terminal Count .10-6 10.2.2 Mode Hardware Retriggerable One-shot .10-8 10.2.3 Mode Rate Generator .10-10 10.2.4 Mode Square Wave .10-12 10.2.5 Mode Software-triggered Strobe .10-16 10.2.6 Mode Hardware-triggered Strobe .10-18 10.3 REGISTER DEFINITIONS. 10-20 10.3.1 Configuring Input Output Signals .10-20 10.3.1.1 Hardware Control GATEn .10-20 10.3.1.2 Software Control GATEn .10-20 10.3.2 Initializing Counters .10-24 10.3.3 Writing Counters .10-26 10.3.4 Reading Counter .10-27 10.3.4.1 Simple Read .10-27 10.3.4.2 Counter-latch Command .10-27 10.3.4.3 Read-back Command .10-30 10.4 PROGRAMMING CONSIDERATIONS. 10-33 10.4.1 Timer/Counter Unit Code Examples .10-34
Intel386EX MICROPROCESSOR USER'S MANUAL
CHAPTER ASYNCHRONOUS SERIAL UNIT 11.1 OVERVIEW 11-1 11.1.1 Signals .11-3 11.2 OPERATION 11-4 11.2.1 Baud-rate Generator .11-4 11.2.2 SIOn Transmitter .11-6 11.2.3 SIOn Receiver .11-9 11.2.4 Modem Control .11-12 11.2.5 Diagnostic Mode .11-12 11.2.6 Interrupt Sources .11-13 11.2.6.1 Interrupt Sources .11-13 11.2.6.2 sources .11-13 11.2.7 External UART Support .11-14 11.3 REGISTER DEFINITIONS. 11-15 11.3.1 Port Configuration Registers (PINCFG PnCFG 1-3]) .11-17 11.3.2 SSIO Configuration Register (SIOCFG) .11-21 11.3.3 Divisor Latch Registers (DLLn DLHn) .11-22 11.3.4 Transmit Buffer Register (TBRn) .11-23 11.3.5 Receive Buffer Register (RBRn) .11-24 11.3.6 Serial Line Control Register (LCRn) .11-25 11.3.7 Serial Line Status Register (LSRn) .11-26 11.3.8 Interrupt Enable Register (IERn) .11-27 11.3.9 Interrupt Register (IIRn) .11-28 11.3.10 Modem Control Register (MCRn) .11-29 11.3.11 Modem Status Register (MSRn) .11-31 11.3.12 Scratch Register (SCRn) .11-32 11.4 PROGRAMMING CONSIDERATIONS. 11-32 11.4.1 Asynchronous Serial Unit Code Examples .11-33 CHAPTER CONTROLLER 12.1 OVERVIEW 12-1 12.1.1 Terminology .12-3 12.1.2 Signals .12-4 12.2 OPERATION. 12-5 12.2.1 Transfers .12-5 12.2.2 Cycle Options Data Transfers .12-5 12.2.2.1 Fly-By Mode .12-5 12.2.2.2 Two-Cycle Mode .12-6 12.2.2.3 Programmable Transfer Direction .12-6 12.2.2.4 Ready Generation Cycles .12-7 12.2.2.5 Usage 4-Byte Temporary Register .12-7 12.2.3 Starting Transfers .12-9
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CONTENTS
12.2.4 Control Arbitration .12-9 12.2.5 Ending Transfers .12-10 12.2.6 Buffer-transfer Modes .12-12 12.2.6.1 Single Buffer-Transfer Mode .12-12 12.2.6.2 Autoinitialize Buffer-Transfer Mode .12-12 12.2.6.3 Chaining Buffer-Transfer Mode .12-12 12.2.7 Data-transfer Modes .12-13 12.2.7.1 Single Data-transfer Mode .12-14 12.2.7.2 Block Data-transfer Mode .12-18 12.2.7.3 Demand Data-transfer Mode .12-21 12.2.8 Cascade Mode .12-25 12.2.9 Interrupts .12-26 12.2.10 8237A Compatibility .12-27 12.3 REGISTER DEFINITIONS. 12-28 12.3.1 Configuration Register (PINCFG) .12-31 12.3.2 Configuration Register (DMACFG) .12-32 12.3.3 Channel Registers .12-33 12.3.4 Overflow Enable Register (DMAOVFE) .12-34 12.3.5 Command Register (DMACMD1) .12-35 12.3.6 Status Register (DMASTS) .12-36 12.3.7 Command Register (DMACMD2) .12-37 12.3.8 Mode Register (DMAMOD1) .12-38 12.3.9 Mode Register (DMAMOD2) .12-40 12.3.10 Software Request Register (DMASRR) .12-42 12.3.11 Channel Mask Group Mask Registers (DMAMSK DMAGRPMSK) .12-44 12.3.12 Size Register (DMABSR) .12-46 12.3.13 Chaining Register (DMACHR) .12-47 12.3.14 Interrupt Enable Register (DMAIEN) .12-48 12.3.15 Interrupt Status Register (DMAIS) .12-49 12.3.16 Software Commands .12-50 12.4 DESIGN CONSIDERATIONS. 12-50 12.5 PROGRAMMING CONSIDERATIONS. 12-50 12.5.1 Controller Code Examples .12-51 CHAPTER SYNCHRONOUS SERIAL UNIT 13.1 OVERVIEW 13-1 13.1.1 SSIO Signals .13-4 13.2 SSIO OPERATION 13-5 13.2.1 Baud-rate Generator .13-5 13.2.2 Transmitter .13-6 13.2.2.1 Transmit Mode using Enable .13-7 13.2.2.2 Autotransmit Mode .13-12 13.2.2.3 Slave Mode .13-12
Intel386EX MICROPROCESSOR USER'S MANUAL
13.2.3 Receiver .13-12 13.3 REGISTER DEFINITIONS. 13-16 13.3.1 Configuration Register (PINCFG) .13-17 13.3.2 SSIO Configuration Register (SIOCFG) .13-18 13.3.3 Prescale Clock Register (CLKPRS) .13-19 13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) .13-20 13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) .13-21 13.3.6 SSIO Control Register (SSIOCON1) .13-21 13.3.7 SSIO Control Register (SSIOCON2) .13-23 13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) .13-24 13.3.9 SSIO Receive Holding Buffer (SSIORBUF) .13-25 13.4 DESIGN CONSIDERATIONS. 13-25 13.5 PROGRAMMING CONSIDERATIONS. 13-26 13.5.1 SSIO Example Code .13-26 CHAPTER CHIP-SELECT UNIT 14.1 OVERVIEW 14-1 14.2 UPON RESET 14-2 14.3 OPERATION 14-2 14.3.1 Defining Channel's Address Block .14-2 14.3.2 System Management Mode Support .14-10 14.3.3 Cycle Length Control .14-11 14.3.4 Size Control .14-11 14.3.5 Overlapping Regions .14-11 14.4 REGISTER DEFINITIONS. 14-13 14.4.1 Configuration Register (PINCFG) .14-15 14.4.2 Port Configuration Register (P2CFG) .14-16 14.4.3 Chip-select Address Registers .14-17 14.4.4 Chip-select Mask Registers .14-19 14.5 DESIGN CONSIDERATIONS. 14-21 14.6 PROGRAMMING CONSIDERATIONS. 14-22 14.6.1 Chip-Select Unit Code Example .14-22 CHAPTER REFRESH CONTROL UNIT 15.1 DYNAMIC MEMORY CONTROL. 15-1 15.1.1 Refresh Methods .15-1 15.2 REFRESH CONTROL UNIT OVERVIEW 15-2 15.2.1 Signals .15-4 15.2.2 Refresh Intervals .15-4
CONTENTS
15.2.3 Refresh Addresses .15-4 15.2.4 Arbitration .15-5 15.3 OPERATION 15-5 15.4 REGISTER DEFINITIONS. 15-6 15.4.1 Refresh Clock Interval Register (RFSCIR) .15-7 15.4.2 Refresh Control Register (RFSCON) .15-8 15.4.3 Refresh Base Address Register (RFSBAD) .15-9 15.4.4 Refresh Address Register (RFSADD) .15-10 15.5 DESIGN CONSIDERATIONS. 15-11 15.6 PROGRAMMING CONSIDERATIONS. 15-14 15.6.1 Refresh Control Unit Example Code .15-14 CHAPTER INPUT/OUTPUT PORTS 16.1 OVERVIEW 16-1 16.1.1 Port Functionality .16-2 16.2 REGISTER DEFINITIONS. 16-6 16.2.1 Configuration .16-7 16.2.2 Initialization Sequence .16-10 16.3 DESIGN CONSIDERATIONS. 16-10 16.3.1 Status During After Reset .16-10 16.4 PROGRAMMING CONSIDERATIONS. 16-11 16.4.1 Ports Code Example .16-11 CHAPTER WATCHDOG TIMER UNIT 17.1 OVERVIEW 17-1 17.1.1 Signals .17-3 17.2 WATCHDOG TIMER UNIT OPERATION. 17-3 17.2.1 Idle Powerdown modes .17-4 17.2.2 General-purpose Timer Mode .17-4 17.2.3 Software Watchdog Mode .17-5 17.2.4 Monitor Mode .17-5 17.3 DISABLING 17-6 17.4 REGISTER DEFINITIONS. 17-7 17.5 DESIGN CONSIDERATIONS. 17-12 17.6 PROGRAMMING CONSIDERATIONS. 17-12 17.6.1 Writing Reload Registers (WDTRLDH WDTRLDL) .17-12 17.6.2 Minimum Counter Reload Value .17-12 17.6.3 Watchdog Timer Unit Code Examples .17-12
Intel386EX MICROPROCESSOR USER'S MANUAL
CHAPTER JTAG TEST-LOGIC UNIT 18.1 OVERVIEW 18-1 18.2 TEST-LOGIC UNIT OPERATION. 18-3 18.2.1 Test Access Port (TAP) .18-3 18.2.2 Test Access Port (TAP) Controller .18-4 18.2.3 Instruction Register (IR) .18-7 18.2.4 Data Registers .18-8 18.3 TESTING 18-10 18.3.1 Identifying Device .18-10 18.3.2 Bypassing Devices Board .18-10 18.3.3 Sampling Device Operation Preloading Data .18-10 18.3.4 Testing Interconnections (EXTEST) .18-10 18.3.5 Disabling Output Drivers .18-11 18.4 TIMING INFORMATION 18-12 18.5 DESIGN CONSIDERATIONS. 18-14 APPENDIX SIGNAL DESCRIPTIONS APPENDIX COMPATIBILITY WITH PC/AT* ARCHITECTURE HARDWARE DEPARTURES FROM PC/AT SYSTEM ARCHITECTURE B.1.1 Unit B.1.2 Industry Standard (ISA) Signals B.1.3 Interrupt Control Unit B.1.4 Units B.1.5 CPU-only Reset B.1.6 HOLD, HLDA Pins B.1.7 Port SOFTWARE CONSIDERATIONS PC/AT SYSTEM ARCHITECTURE. B.2.1 Embedded Basic Input Output System (BIOS) B.2.2 Embedded Disk Operating System (DOS) B.2.3 Microsoft* Windows* APPENDIX EXAMPLE CODE HEADER FILES REGISTER DEFINITIONS CODE EXAMPLES EXAMPLE CODE DEFINES
CONTENTS
APPENDIX SYSTEM REGISTER QUICK REFERENCE PERIPHERAL REGISTER ADDRESSES. CLKPRS CSnADH (UCSADH). CSnADL (UCSADL) CSnMSKH (UCSMSKH) D-10 CSnMSKL (UCSMSKL) D-11 DLLn DLHn D-12 DMABSR D-13 DMACFG D-14 D.10 DMACHR D-15 D.11 DMACMD1. D-16 D.12 DMACMD2. D-17 D.13 DMAGRPMSK D-18 D.14 DMAIEN D-19 D.15 DMAIS D-20 D.16 DMAMOD1 D-21 D.17 DMAMOD2 D-22 D.18 DMAMSK D-23 D.19 DMAnBYCn, DMAnREQn DMAnTARn D-24 D.20 DMAOVFE D-25 D.21 DMASRR D-26 D.22 DMASTS D-27 D.23 ICW1 (MASTER SLAVE) D-28 D.24 ICW2 (MASTER SLAVE) D-29 D.25 ICW3 (MASTER). D-29 D.26 ICW3 (SLAVE) D-30 D.27 ICW4 (MASTER SLAVE) D-30 D.28 IDCODE D-31 D.29 IERn D-32 D.30 IIRn D-33 D.31 INTCFG D-34 D.32 D-35 D.33 LCRn D-36 D.34 LSRn D-37 D.35 MCRn D-38 D.36 MSRn D-39
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D.37 D.38 D.39 D.40 D.41 D.42 D.43 D.44 D.45 D.46 D.47 D.48 D.49 D.50 D.51 D.52 D.53 D.54 D.55 D.56 D.57 D.58 D.59 D.60 D.61 D.62 D.63 D.64 D.65 D.66 D.67 D.68 D.69 D.70 D.71 D.72 D.73 D.74
OCW1 (MASTER SLAVE). OCW2 (MASTER SLAVE). OCW3 (MASTER SLAVE). P1CFG P2CFG P3CFG PINCFG PnDIR PnLTC. PnPIN POLL (MASTER SLAVE) PORT92. PWRCON RBRn REMAPCFG RFSADD RFSBAD RFSCIR RFSCON. SCRn SIOCFG SSIOBAUD SSIOCON1 SSIOCON2 SSIOCTR SSIORBUF SSIOTBUF TBRn TMRCFG TMRCON TMRn UCSADH. UCSADL UCSMSKH UCSMSKL WDTCNTH WDTCNTL. WDTRLDH WDTRLDL WDTSTATUS.
D-40 D-41 D-42 D-43 D-44 D-45 D-46 D-47 D-48 D-48 D-49 D-50 D-51 D-52 D-53 D-54 D-54 D-55 D-55 D-56 D-57 D-58 D-59 D-60 D-61 D-61 D-62 D-62 D-63 D-64 D-65 D-67 D-67 D-67 D-67 D-68 D-69 D-70
CONTENTS
APPENDIX INSTRUCTION SUMMARY INSTRUCTION ENCODING CLOCK COUNT SUMMARY. INSTRUCTION ENCODING E-22 E.2.1 32-bit Extensions Instruction E-23 E.2.2 Encoding Instruction Fields E-24 E.2.2.1 Encoding Operand Length Field E-24 E.2.2.2 Encoding General Register (reg) Field E-24 E.2.2.3 Encoding Segment Register (sreg) Field E-25 E.2.2.4 Encoding Address Mode E-26 E.2.2.5 Encoding Operation Direction Field E-30 E.2.2.6 Encoding Sign-Extend Field E-30 E.2.2.7 Encoding Conditional Test (tttn) Field E-30 E.2.2.8 Encoding Control Debug Test Register (eee) Field E-31 GLOSSARY INDEX
Intel386EX MICROPROCESSOR USER'S MANUAL
FIGURES
Figure 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 6-10 6-11 6-12 6-13 6-14 6-15 Page Intel386EX Embedded Processor Block Diagram .2-2 Instruction Pipelining .3-2 Intel386CX Processor Internal Block Diagram .3-3 PC/AT Address Space (10-bit Decode) .4-3 Expanded Address Space (16-bit Decode) .4-4 Address Configuration Register (REMAPCFG).4-7 Setting Code Example .4-8 DOS-Compatible Mode .4-10 Example Nonintrusive DOS-Compatible Mode .4-12 Enhanced Mode .4-13 NonDOS Mode .4-14 Peripheral Connections.5-2 Configuration DMA, Arbiter, Refresh Unit .5-5 Configuration Register (DMACFG).5-6 Interrupt Control Unit Configuration.5-9 Interrupt Configuration Register (INTCFG).5-10 Timer/Counter Unit Configuration.5-12 Timer Configuration Register (TMRCFG).5-13 Serial Unit Configuration.5-15 Serial Unit Configuration.5-16 SSIO Configuration Register (SIOCFG).5-17 SSIO Unit Configuration .5-18 Configuration Chip-select Unit Clock Power Management Unit .5-20 Core Configuration .5-21 Port Configuration Register (PORT92).5-22 Configuration Register (PINCFG).5-24 Port Configuration Register (P1CFG).5-25 Port Configuration Register (P2CFG).5-26 Port Configuration Register (P3CFG).5-27 Basic External Cycles.6-6 Simplified State Diagram (Does Include Address Pipelining Hold states).6-8 Ready Logic .6-11 Basic Internal External Cycles.6-12 Nonpipelined Address Read Cycles .6-15 Nonpipelined Address Write Cycles .6-18 Complete States (Including Pipelined Address) .6-20 Pipelined Address Cycles.6-21 Interrupt Acknowledge Cycles .6-25 Halt Cycle .6-27 Basic Refresh Cycle .6-29 Refresh Cycle During HOLD/HLDA.6-30 16-bit Cycles 8-bit Devices (Using BS8#).6-33 LOCK# Signal During Address Pipelining .6-35 Intel386 Processor Intel387 Math Coprocessor Interface.6-39
CONTENTS
FIGURES
Figure 6-16 6-17 6-18 6-19 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 10-1 10-2 10-3 10-4 10-5 10-6 Page Intel386 Processor SRAM/FLASH Interface.6-41 Intel386 Processor PSRAM Interface .6-42 Intel386 Processor Paged DRAM Interface.6-43 Intel386 Processor Non-Paged DRAM Interface .6-44 Standard SMI# .7-5 SMIACT# Latency .7-6 SMI# During HALT .7-8 SMI# During Instruction .7-9 SMI# Timing .7-10 Interrupted SMI# Service.7-11 HALT During Handler.7-12 Clock Power Management Unit Connections .8-2 Clock Synchronization .8-3 Interaction with Idle Powerdown Modes.8-5 Clock Prescale Register (CLKPRS) .8-7 Power Control Register (PWRCON).8-8 Timing Diagram, Entering Leaving Idle Mode .8-9 Timing Diagram, Entering Leaving Powerdown Mode .8-11 Reset Synchronization Circuit .8-12 Interrupt Control Unit Configuration.9-3 Methods Changing Default Interrupt Structure.9-7 Interrupt Process Master Request from Non-slave Source .9-11 Interrupt Process Slave Request.9-12 Interrupt Process Master Request from Slave Source .9-13 Port Configuration Register (P3CFG).9-18 Interrupt Configuration Register (INTCFG).9-19 Initialization Command Word Register (ICW1).9-20 Initialization Command Word Register (ICW2).9-21 Initialization Command Word Register (ICW3 Master).9-22 Initialization Command Word Register (ICW3 Slave).9-23 Initialization Command Word Register (ICW4).9-24 Operation Command Word (OCW1) .9-25 Operation Command Word (OCW2) .9-26 Operation Command Word (OCW3) .9-27 Poll Status Byte (POLL) .9-28 Interrupt Acknowledge Cycle.9-29 Spurious Interrupts .9-30 Cascading External 82C59A Interrupt Controllers.9-31 Timer/Counter Unit Signal Connections .10-2 Mode Basic Operation .10-7 Mode Disabling Count .10-7 Mode Writing Count.10-8 Mode Basic Operation .10-9 Mode Retriggering One-shot .10-9
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Intel386EX MICROPROCESSOR USER'S MANUAL
FIGURES
Figure 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 Page Mode Writing Count.10-10 Mode Basic Operation .10-11 Mode Disabling Count .10-11 Mode Writing Count.10-12 Mode Basic Operation (Even Count).10-13 Mode Basic Operation (Odd Count) .10-14 Mode Disabling Count .10-14 Mode Writing Count (With Trigger).10-15 Mode Writing Count (Without Trigger).10-15 Mode Basic Operation .10-16 Mode Disabling Count .10-17 Mode Writing Count.10-17 Mode Basic Operation .10-18 Mode Retriggering Strobe .10-19 Mode Writing Count Value .10-19 Timer Configuration Register (TMRCFG).10-21 Port Configuration Register (P3CFG).10-22 Configuration Register (PINCFG).10-23 Timer Control Register (TMRCON Control Word Format).10-25 Timer Register (TMRn Write Format) .10-26 Timer Control Register (TMRCON Counter-latch Format) .10-28 Timer Register (TMRn Read Format).10-29 Timer Control Register (TMRCON Read-back Format) .10-30 Timer Register (TMRn Status Format) .10-32 Serial Unit Configuration.11-2 SIOn Baud-rate Generator Clock Sources .11-4 SIOn Transmitter .11-7 SIOn Data Transmission Process Flow.11-8 SIOn Receiver .11-9 SIOn Data Reception Process Flow .11-11 Configuration Register (PINCFG).11-17 Port Configuration Register (P1CFG).11-18 Port Configuration Register (P2CFG).11-19 Port Configuration Register (P3CFG).11-20 SSIO Configuration Register (SIOCFG).11-21 Divisor Latch Registers (DLLn DLHn) .11-22 Transmit Buffer Register (TBRn) .11-23 Receive Buffer Register (RBRn).11-24 Serial Line Control Register (LCRn) .11-25 Serial Line Status Register (LSRn).11-26 Interrupt Enable Register (IERn) .11-27 Interrupt Register (IIRn) .11-28 Modem Control Signals Diagnostic Mode Connections .11-29 Modem Control Signals Internal Connections .11-29
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CONTENTS
FIGURES
Figure 11-21 11-22 11-23 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 12-30 12-31 12-32 12-33 12-34 13-1 13-2 13-3 13-4 13-5 13-6 Page Modem Control Register (MCRn) .11-30 Modem Status Register (MSRn).11-31 Scratch Register (SCRn).11-32 Unit Block Diagram.12-2 Temporary Buffer Operation Read Transfer.12-8 Temporary Buffer Operation Write Transfer .12-8 Start Two-cycle Transfer Initiated DRQn .12-9 Changing Priority Channel External Requests .12-10 Buffer Transfer Ended Expired Byte Count .12-11 Buffer Transfer Ended EOP# Input.12-11 Single Data-transfer Mode with Single Buffer-transfer Mode .12-15 Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode .12-16 Single Data-transfer Mode with Chaining Buffer-transfer Mode .12-17 Block Data-transfer Mode with Single Buffer-transfer Mode .12-19 Block Data-transfer Mode with Autoinitialize Buffer-transfer Mode .12-20 Buffer Transfer Suspended Deactivation DRQn .12-21 Demand Data-transfer Mode with Single Buffer-transfer Mode.12-22 Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode .12-23 Demand Data-transfer Mode with Chaining Buffer-transfer Mode .12-24 Cascade Mode .12-26 Configuration Register (PINCFG).12-31 Configuration Register (DMACFG).12-32 Channel Address Byte Count Registers (DMAnREQn, DMAnTARn, DMAnBYCn).12-33 Overflow Enable Register (DMAOVFE).12-34 Command Register (DMACMD1) .12-35 Status Register (DMASTS).12-36 Command Register (DMACMD2) .12-37 Mode Register (DMAMOD1) .12-39 Mode Register (DMAMOD2) .12-41 Software Request Register (DMASRR write format).12-42 Software Request Register (DMASRR read format) .12-43 Channel Mask Register (DMAMSK) .12-44 Group Channel Mask Register (DMAGRPMSK) .12-45 Size Register (DMABSR) .12-46 Chaining Register (DMACHR).12-47 Interrupt Enable Register (DMAIEN) .12-48 Interrupt Status Register (DMAIS).12-49 Transmitter Receiver Master Mode .13-2 Transmitter Master Mode, Receiver Slave Mode.13-2 Transmitter Slave Mode, Receiver Master Mode.13-3 Transmitter Receiver Slave Mode .13-3 Clock Sources Baud-rate Generator .13-5 SSIO Transmitter with Autotransmit Mode Enabled .13-7
Intel386EX MICROPROCESSOR USER'S MANUAL
FIGURES
Figure 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 16-3 16-4 16-5 16-6 17-1 17-2 17-3 Page SSIO Transmitter with Autotransmit Mode Disabled .13-8 Transmit Data Polling .13-9 Interrupt Service Routine Transmitting Data Using Interrupts.13-10 Transmitter Master Mode, Single Word Transfer (Enabled when Clock High) .13-11 Transmitter Master Mode, Single Word Transfer (Enabled when Clock Low) .13-11 Receive Data Polling .13-13 Interrupt Service Routine Receiving Data Using Interrupts.13-14 Receiver Master Mode, Single Word Transfer .13-15 Configuration Register (PINCFG).13-17 SSIO Configuration Register (SIOCFG).13-18 Clock Prescale Register (CLKPRS) .13-19 SSIO Baud-rate Control Register (SSIOBAUD) .13-20 SSIO Baud-rate Count Down Register (SSIOCTR).13-21 SSIO Control Register (SSIOCON1) .13-22 SSIO Control Register (SSIOCON2) .13-23 SSIO Transmit Holding Buffer (SSIOTBUF).13-24 SSIO Receive Holding Buffer (SSIORBUF) .13-25 Channel Address Comparison Logic .14-3 Determining Channel's Address Block Size .14-4 Cycle Length Adjustments Overlapping Regions.14-12 Configuration Register (PINCFG).14-15 Port Configuration Register (P2CFG).14-16 Chip-select High Address Register (CSnADH, UCSADH) .14-17 Chip-select Address Register (CSnADL, UCSADL) .14-18 Chip-select High Mask Registers (CSnMSKH, UCSMSKH).14-19 Chip-select Mask Registers (CSnMSKL, UCSMSKL).14-20 Refresh Control Unit Connections .15-3 Refresh Clock Interval Register (RFSCIR) .15-7 Refresh Control Register (RFSCON) .15-8 Refresh Base Address Register (RFSBAD) .15-9 Refresh Address Register (RFSADD) .15-10 Connections Ensure Refresh Rows 8-Bit Wide PSRAM Device .15-11 RAS# Only Refresh Logic: Paged Mode .15-13 RAS# Only Refresh Logic: Non-Paged Mode .15-14 Port Block Diagram.16-2 Logic Diagram Bi-directional Port .16-3 Port Configuration Register (PnCFG).16-7 Port Direction Register (PnDIR) .16-8 Port Data Latch Register (PnLTC).16-8 Port State Register (PnPIN) .16-9 Watchdog Timer Unit Connections.17-2 Counter Value Registers (WDTCNTH WDTCNTL) .17-8 Status Register (WDTSTATUS) .17-9
CONTENTS
FIGURES
Figure 17-4 17-5 18-1 18-2 18-3 18-4 18-5 18-6 Page Reload Value Registers (WDTRLDH WDTRLDL).17-10 Power Control Register (PWRCON).17-11 Test Logic Unit Connections .18-2 Controller (Finite-State Machine).18-6 Instruction Register (IR).18-7 Identification Code Register (IDCODE) .18-8 Internal External Timing Loading Instruction Register.18-12 Internal External Timing Loading Data Register.18-13 Derivation Signal Typical PC/AT System Derivation Signal Intel386EX processor-based Systems General Instruction Format. E-22
Intel386EX MICROPROCESSOR USER'S MANUAL
TABLES
Table 5-10 5-11 5-12 5-13 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 12-4 13-1 Page PC-compatible Peripherals.2-3 Embedded Application-specific Peripherals .2-4 Peripheral Register Address Slot 15.4-5 Peripheral Register Addresses.4-15 Master's Connections .5-8 Master's Connections .5-8 Signal Pairs Pins without Multiplexer.5-23 Example Configuration Registers.5-30 Example DMACFG Configuration Register .5-31 Example TMRCFG Configuration Register .5-32 Example INTCFG Configuration Register .5-33 Example SIOCFG Configuration Register .5-33 Configuration Register Design Woksheet .5-34 DMACFG Register Design Worksheet .5-35 TMRCFG Register Design Worksheet .5-36 INTCFG Register Design Worksheet .5-37 SIOCFG Register Design Worksheet .5-37 Interface Unit Signals .6-3 Status Definitions .6-5 Sequence Nonaligned Transfers.6-10 Bits Cleared Upon Entering .7-3 Processor State Initialization Values.7-4 Relative Priority Exceptions Interrupts.7-7 Clock Power Management Registers .8-6 Clock Power Management Signals.8-6 82C59A Master Slave Interrupt Sources .9-5 Registers .9-16 Signals .10-3 Associated Registers .10-4 Operations Caused GATEn .10-6 GATEn Connection Options .10-20 Minimum Maximum Initial Counts.10-26 Results Multiple Read-back Commands Without Reads.10-33 Signals .11-3 Maximum Minimum Output Rates .11-5 Divisor Values Common Rates .11-5 Status Signal Priorities Sources .11-13 Registers .11-15 Access Multiplexed Registers.11-16 Signals.12-4 Operations Performed During Transfer .12-6 Registers .12-28 Software Commands .12-50 SSIO Signals .13-4
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CONTENTS
TABLES
Table 13-2 13-3 14-1 14-2 15-1 15-2 16-1 16-2 16-3 17-1 17-2 18-1 18-2 18-3 18-4 18-5 E-10 E-11 E-12 E-13 E-14 E-15 Page Maximum Minimum Baud-rate Output Frequencies .13-6 SSIO Registers.13-16 Signals .14-13 Registers.14-14 Signals .15-4 Registers .15-6 Multiplexing .16-5 Port Registers.16-6 Control Register Values Port Configurations.16-7 Signals .17-3 Registers .17-7 Test Access Port Dedicated Pins .18-3 Controller State Descriptions.18-4 Example Controller State Selections .18-5 Test-logic Unit Instructions .18-7 Boundary-scan Register Assignments .18-9 Signal Description Abbreviations. Description Signals Available Device Pins State Abbreviations States After Reset During Idle, Powerdown, Hold. Peripheral Register Addresses. Instruction Summary Fields Within Instructions. E-23 Encoding Operand Length Field. E-24 Encoding Field When Field Present Instruction E-24 Encoding Field When Field Present Instruction E-25 Encoding Segment Register (sreg) Field. E-25 Encoding 16-bit Address Mode with "mod r/m" Byte E-27 Encoding 32-bit Address Mode with "mod r/m" Byte s-i-b Byte Present). E-28 Encoding 32-bit Address Mode ("mod r/m" Byte s-i-b Byte Present). E-29 Encoding Operation Direction Field E-30 Encoding Sign-Extend Field E-30 Encoding Conditional Test (tttn) Field E-30 When Interpreted Control Register Field E-31 When Interpreted Debug Register Field E-31 When Interpreted Test Register Field. E-31
xxiii
GUIDE THIS MANUAL
CHAPTER GUIDE THIS MANUAL
This manual describes Intel386EX Embedded Processor. intended hardware designers familiar with principles microprocessors with Intel386 processor architecture. This chapter organized follows:
Manual Contents (see below) Notational Conventions (page 1-3) Special Terminology (page 1-4) Related Documents (page 1-5) Electronic Support Systems (page 1-6) Technical Support (page 1-7) Product Literature (page 1-8) MANUAL CONTENTS
This manual contains chapters appendixes, glossary, index. This section summarizes contents remaining chapters appendixes. remainder this chapter describes notational conventions special terminology used throughout manual provides references related documentation. Chapter Architectural Overview describes device features some potential applications. Chapter Core Overview describes differences between this device Intel386SX processor core. Chapter System Register Organization describes organization system registers, address space, address decoding, addressing modes. Chapter Device Configuration explains configure device various applications. Chapter Interface Unit describes interface logic, states, cycles, instruction pipelining. Chapter System Management Mode describes Intel's System Management Mode (SMM). Chapter Clock Power Management Unit describes clock generation circuitry, power management modes, system reset logic.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Chapter Interrupt Control Unit describes interrupt sources priority options explains program interrupt control unit. Chapter Timer/Counter Unit describes timer/counters their available count formats operating modes. Chapter Asynchronous Serial (SIO) Unit explains universal asynchronous receiver/transmitters (UARTs) transmit receive serial data. Chapter Controller describes enhanced direct memory access controller allows internal external devices transfer data directly from system explains control arbitrated. Chapter Synchronous Serial (SSIO) Unit explains transmit receive data synchronously. Chapter Chip-select Unit explains chip-select channels access various external memory devices. Chapter Refresh Control Unit describes refresh control unit generates periodic refresh requests refresh addresses simplify interface dynamic memory devices. Chapter Input/Output Ports describes general-purpose ports explains configure each serve either controlled internal peripheral. Chapter Watchdog Timer Unit explains watchdog timer unit software watchdog, monitor, general-purpose timer. Chapter JTAG Test-logic Unit describes independent test-logic unit explains test device logic board-level connections. Appendix Signal Descriptions describes device pins signals lists states after system reset during powerdown, idle, hold. Appendix Compatibility with PC/AT* Architecture describes ways which device compatible with standard PC/AT architecture ways which departs from standard. Appendix Example Code Header Files contains header files called code examples that included several chapters this manual. Appendix System Register Quick Reference contains alphabetical list registers. Appendix Instruction Summary lists instructions their clock counts. Glossary defines terms with special meaning used throughout this manual. Index lists topics with page number references.
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NOTATIONAL CONVENTIONS
following notations used throughout this manual. Variables Terms Instructions pound symbol appended signal name indicates that signal active low. Variables shown italics. Variables must replaced with correct values. terms shown italics. Glossary brief definition commonly used terms. Instruction mnemonics shown upper case. When programming, instructions case sensitive. either upper lower case. Hexadecimal numbers represented string hexadecimal digits followed character zero prefix added numbers that begin with through (For example, shown 0FFH.) Decimal binary numbers represented their customary notations. (That decimal number 1111 1111 binary number. some cases, letter added clarity.) following abbreviations used represent units measure: Gbyte Kbyte Mbyte amps, amperes gigabytes kilobytes kilo-ohms milliamps, milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps, microamperes microfarads microseconds microwatts
Numbers
Units Measure
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Register Bits
When text refers more that bit, range appear numbers separated colon (example: 15:0). first shown example) most-significant second shown least-significant bit. Register names shown upper case. register name contains lowercase, italic character, represents more than register. example, PnCFG represents three registers: P1CFG, P2CFG, P3CFG. Signal names shown upper case. When several signals share common name, individual signal represented signal name followed number, while group represented signal name followed variable (n). example, lower chip-select signals named CS0#, CS1#, CS2#, they collectively called CSn#. pound symbol appended signal name identifies active-low signal. Port pins represented port abbreviation, period, number (e.g., P1.0, P1.1).
Register Names
Signal Names
SPECIAL TERMINOLOGY
following terms have special meanings this manual. Assert Deassert terms assert deassert refer making signal active inactive, respectively. active polarity (high/low) defined signal name. Active-low signals designated pound symbol suffix; active-high signals have suffix. assert drive low; assert HOLD drive high; deassert drive high; deassert HOLD drive low. Integrated peripherals that compatible with PC/AT system architecture mapped into PC/AT) addresses 03FFH. this manual, terms address PC/AT address synonymous. peripheral registers reside addresses 0F000H-0FFFFH. PC/AT-compatible integrated peripherals also mapped into PC/AT) address space (0H-03FFH). Integrated peripherals that compatible with PC/AT system architecture mapped into PC/AT DOS) addresses 03FFH. this manual, terms address PC/AT address synonymous. Processor refers Intel386 processor including integrated peripherals. refers processor core, which based static Intel386 processor.
Address
Expanded Address
PC/AT Address
Processor
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Reserved Bits
Reserved bits used this device, they used future implementations. Follow these guidelines ensure compatibility with future devices:
Avoid software dependence state undefined
register bits.
read-modify-write sequence load registers. Mask undefined bits when testing values defined bits. depend state undefined bits when storing
undefined bits memory another register.
depend ability retain information written
undefined bits. Clear terms clear refer value giving value. set, value "1"; setting gives value. clear, value "0"; clearing gives value.
RELATED DOCUMENTS
following documents contain additional information that useful designing systems that incorporate Intel386 processor. order documents, please call Intel Literature Fulfillment (1-800-548-4725 U.S. Canada; +44(0) 1793-431155 Europe).
Document Name
Intel386EX Embedded Microprocessor datasheet Intel386SX Microprocessor datasheet Intel386SX Microprocessor Programmer's Reference Manual Intel386SX Microprocessor Hardware Reference Manual Development Tools Buyer's Guide Intel386Embedded Processor Family Intel386EX Microprocessor Multiplexing
Packaging
Order Number 272420 240187 240331 240332 272326 272520 272587 240800
also want refer Standard 1149.1-1990, IEEE Standard Test Access Port Boundary-Scan Architecture supplement, Standard 1149.1a-1993.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
ELECTRONIC SUPPORT SYSTEMS
Intel's FaxBack* service application provide up-to-date technical information. Intel also maintains several forums CompuServe offers variety information World Wide Web. These systems available hours day, days week, providing technical information whenever need 1.5.1 FaxBack Service
FaxBack on-demand publishing system that sends documents your machine. product announcements, change notifications, product literature, device characteristics, design recommendations, quality reliability information from FaxBack hours day, days week. 1-800-525-3019 Canada) +44-1793-432509 (Europe) +65-256-5350 (Singapore) +852-2-844-4448 (Hong Kong) +886-2-514-0815 (Taiwan) +822-767-2594 (Korea) +61-2-975-3922 (Australia) 1-503-264-6835 (Worldwide) Think FaxBack service library technical documents that access with your phone. Just dial telephone number respond system prompts. After select document, system sends copy your machine. Each document order number listed subject catalog. first time FaxBack, should order appropriate subject catalogs complete list document order numbers. Catalogs updated twice monthly. addition, daily update catalogs list title, status, order number each document that been added, revised, deleted during past eight weeks. receive update subject catalog, enter subject catalog number followed zero. example, complete microcontroller flash catalog, request document number daily update microcontroller flash catalog, request document number following catalogs information available time publication:
Solutions subscription form Microcontroller flash catalog Development tools catalog Systems catalog Multimedia catalog Multibus iRMX software catalog file listings
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1.5.2
Microprocessor, PCI, peripheral catalog Quality reliability change notification catalog (Intel Architecture Labs) technology catalog Bulletin Board System (BBS)
bulletin board system (BBS) lets download files your computer. application latest ApBUILDER software, hypertext manuals datasheets, software drivers, firmware upgrades, code examples, application notes utilities, quality reliability data. system supports 1200- through 19200-baud modems. Typical modem settings 14400 baud, parity, data bits, stop (14400, access BBS, terminal program dial telephone number given below your area; once connected, respond system prompts. During your first session, enter your name location. system operator will your access account within hours. that time, access files BBS. 503-264-7999 44(0)1793-432955 U.S., Canada, Japan, Asia Pacific 19.2 Kbaud) Europe
NOTE
have problems accessing BBS, these settings your modem: 2400, Refer your terminal software documentation instructions changing these settings. 1.5.3 CompuServe Forums
CompuServe forums provide means gather information, share discoveries, debate issues. Type intel" access. information about CompuServe access service fees, call CompuServe 1-800-848-8199 (U.S.) 614-529-1340 (outside U.S.). 1.5.4 World Wide
offer variety information through World Wide (http://www.intel.com/). Select "Embedded Design Products" from Intel home page. TECHNICAL SUPPORT
U.S. Canada, technical support representatives available answer your questions between a.m. p.m. PST. also your questions (Please include your voice telephone number indicate whether prefer response phone fax). Outside U.S. Canada, please contact your local distributor. 1-800-628-8686 U.S. Canada 916-356-7599 U.S. Canada 916-356-6100 (fax) U.S. Canada
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
PRODUCT LITERATURE
order product literature from following Intel literature centers. 1-800-548-4725 U.S. Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only)
ARCHITECTURAL OVERVIEW
CHAPTER ARCHITECTURAL OVERVIEW
Intel386EX embedded processor (Figure 2-1) based static Intel386 processor. This highly integrated device retains those personal computer functions that useful embedded applications integrates peripherals that typically needed embedded systems. Intel386 processor provides PC-compatible development platform device that optimized embedded applications. integrated peripherals power management options make Intel386 processor ideal portable systems. integrated peripherals Intel386 processor compatible with standard desktop This allows existing software, including most industry's leading desktop embedded operating systems, easily implemented Intel386 processor-based platform. Using PC-compatible peripherals also allows development debugging application software standard platform. Typical applications using Intel386 processor include automated manufacturing equipment, cellular telephones, telecommunications equipment, machines, hand-held data loggers, high-precision industrial flow controllers, interactive television, medical equipment, modems, smart copiers. This chapter organized follows:
Intel386 Embedded Processor Core (see below) Integrated Peripherals (page 2-3)
Intel386 EMBEDDED PROCESSOR CORE
Intel386 processor contains modular, fully static Intel386 central processing unit (CPU). Intel386 processor enhanced Intel386 processor with addition System Management Mode (SMM) additional address lines. Intel386 processor 16-bit data 26-bit address bus, supporting Mbytes memory address space Kbytes address space. performance Intel386 processor closely reflects Intel386 performance same speeds. Chapter "CORE OVERVIEW" describes differences between Intel386 processor core Intel386 processor. Please refer Intel386SX Microprocessor Programmer's Reference Manual (order number 240331) applications system programming information; descriptions protected, real, virtual-8086 modes; details instruction set.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Interface Unit Chip-select Unit
Address
Data
JTAG Unit Address Intel386CX Core Core Enhancements Gate Reset
Clock Power Management Unit DRAM Refresh Control Unit Watchdog Timer Unit Monitor Asynchronous Serial channels (16450 compatible) Synchronous Serial channel, full duplex Timer/counter Unit channels (82C54 compatible)
Data
Ports
INTR
Interrupt Control Unit
Controller channels (8237A compatible) Arbiter Unit
A2849-02
Figure 2-1. Intel386EX Embedded Processor Block Diagram
ARCHITECTURAL OVERVIEW
INTEGRATED PERIPHERALS
Intel386 processor integrates both PC-compatible peripherals (Table 2-1) peripherals that specific embedded applications (Table 2-2).
Table 2-1. PC-compatible Peripherals
Name Interrupt Control Unit (ICU) Timer/counter Unit (TCU) Description Consists 82C59A programmable interrupt controllers (PICs) configured master slave. cascade external 82C59A PICs expand external interrupt lines Refer Chapter "INTERRUPT CONTROL UNIT." Provides three independent 16-bit down counters. programmable functionally equivalent three 82C54 counter/timers with enhancements allow remapping peripheral addresses interrupt assignments. Refer Chapter "TIMER/COUNTER UNIT." Features independent universal asynchronous receiver transmitter (UART) units which functionally equivalent National Semiconductor's NS16450. Each channel contains baud-rate generator, transmitter, receiver, modem control unit. Receive transmit interrupt signals connected controller controller. Refer Chapter "ASYNCHRONOUS SERIAL UNIT." Transfers internal external data between combination memory devices entire 26-bit address bus. independent channels operate 8-bit mode. Buffer chaining allows data transferred into noncontiguous memory buffers. channels tied serial devices support high data rates, minimizing processor interruptions. Provides special two-cycle mode that uses only channel memory-to-memory transfers. arbitration logic resolves priority conflicts between channels, refresh control unit, external master. SSIO interrupts connected high-speed transfers. Backward compatible with 8237A. Refer Chapter "DMA CONTROLLER."
Asynchronous Serial (SIO) Unit
Direct Memory Access (DMA) Controller
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 2-2. Embedded Application-specific Peripherals
Name System Management Mode (SMM) Description Intel386 processor provides mechanism system management with combination hardware microcode enhancements. externally generated system management interrupt (SMI#) allows execution system-wide routines that independent transparent operating system. system management mode (SMM) architectural extensions Intel386 described Chapter "SYSTEM MANAGEMENT MODE." external clock source provides input frequency. clock power management unit generates separate internal clock signals core peripherals (half input frequency), divides internal clock baud clock inputs SSIO, divides internal clock programmable divisor provide prescaled clock signal (various frequencies) SSIO. Power management provides idle powerdown modes (idle stops clock leaves peripheral clocks running; powerdown stops both peripheral clocks). external clockout signal also provided. Refer Chapter "CLOCK POWER MANAGEMENT UNIT." Synchronous Serial (SSIO) unit Chip-select Unit (CSU) Provides simultaneous, bidirectional high speed serial I/O. Consists transmit channel, receive channel, baud rate generator. Built-in protocols included, because these emulated using CPU. SSIO interrupts connected unit high-speed transfers. Refer Chapter "SYNCHRONOUS SERIAL UNIT." Programmable, eight-channel allows direct access eight devices. Each channel operate 8-bit mode generate wait states. interface with fastest memory slowest peripheral device. minimum address block memory address-configured channels Kbytes. size these address blocks increased powers Kbytes memory addresses multiples bytes addresses. Supports memory addressing provides ready generation programmable wait states. Refer Chapter "CHIP-SELECT UNIT." Provides means generate periodic refresh requests refresh addresses. Consists programmable interval timer unit, control unit, address generation unit. arbitration logic ensures that refresh requests have highest priority. refresh control unit (RCU) provided applications that DRAMs with simple EPLD-based DRAM controller PSRAMs that need separate controller. Refer Chapter "REFRESH CONTROL UNIT." Three ports facilitate data transfer between processor surrounding system circuitry. Intel386 processor unique that several functions multiplexed with each other with ports. This ensures maximum available pins maintains small package. Each multiplexed individually programmable peripheral function. Refer Chapter "INPUT/OUTPUT PORTS." When enabled, functions general purpose 32-bit timer, software timer, monitor. Refer Chapter "WATCHDOG TIMER UNIT." test-logic unit simplifies board-level testing. Consists test access port boundary-scan register. Fully compliant with Standard 1149.1-1990, IEEE Standard Test Access Port Boundary-Scan Architecture supplement, Standard 1149.1a-1993. Refer Chapter "JTAG TEST-LOGIC UNIT."
Clock Power Management Unit
Refresh Control Unit (RCU)
Parallel Ports
Watchdog Timer (WDT) Unit JTAG Testlogic Unit
CORE OVERVIEW
CHAPTER CORE OVERVIEW
Intel386EX processor core based upon Intel386 processor, which enhanced version Intel386 processor. This chapter describes Intel386 processor enhancements over Intel386 processor, internal architecture Intel386 processor, core interface Intel386 processor. This chapter organized follows:
Intel386 Processor Enhancements (see below) Intel386 Processor Internal Architecture (page 3-2) Core Intel386 Processor Interface (page 3-6)
Intel386 PROCESSOR ENHANCEMENTS
Intel386 processor, based Intel386 processor, adds system management mode additional address lines total address lines. 3.1.1 System Management Mode
Intel386 processor core provides mechanism system management with combination hardware microcode enhancements. externally generated System Management Interrupt (SMI#) allows execution system wide routines which independent transparent operating system. System Management Mode (SMM) architecture extensions Intel386 processor consist following elements:
Interrupt input (SMI#) invoke output identify execution state (SMIACT#) instruction (RSM, executable only from SMM) exit also added four execution clocks following instructions: INS, INS, OUT, OUT, POPA, HALT, CR0, SRC. INTR also need additional clocks interrupt latency. These cycles were added microcode modification implementation. Refer Appendix exact execution times. Otherwise, 100% Intel386 processor instructions execute Intel386 processor core.
Please refer Chapter more details System Management Mode. 3.1.2 Additional Address Lines
additional address lines were added Intel386 processor core total This expands physical address space from Mbytes Mbytes.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Intel386 PROCESSOR INTERNAL ARCHITECTURE
internal architecture Intel386 processor consists functional units that operate parallel. Fetching, decoding, execution, memory management accesses several instructions performed simultaneously. This parallel operation called pipelined instruction processing. With pipelining, each instruction performed stages, processing several instructions different stages overlap, shown Figure 3-1. pipelined processing Intel386 processor results higher performance enhanced throughput rate over nonpipelined processors.
Elapsed Time Typical Processor
Fetch
Decode
Execute
Fetch
Decode
Execute
Intel386SX CPU/Intel376CPU 386SX CPU/376CPU
Unit Decode Unit Execution Unit
Fetch
Fetch
Fetch
Fetch
Store Result
Fetch
Fetch
Decode
Decode
Decode
Decode
Decode
Execute
Execute
Execute Addr
Execute
Addr
A2850-01
Figure 3-1. Instruction Pipelining
CORE OVERVIEW
Figure shows internal architecture Intel386 processor.
Segmentation Unit
Effective Address
Paging Unit Adder
Core Plus Unit HOLD, INTR, NMI,
Physical Address
3-Input Adder Descriptor Register Limit Attribute
Request RESET, HLDA, Prioritizer SMI#, SMIACT#,
PEREQ
ERROR#,BUSY#,
Effective Address
Page Cache Control Attribute
BE0#, BE1#, A25:1
Linear Address
Displacement
Protection Test Unit
Code fetch Page Table Fetch
Address Driver
M/IO#, D/C#, W/R#, LOCK#, ADS#, NA#, READY#
Internal Control
Pipeline/ Size Control
Control
MUX/ Transceivers Barrel Shifter, Adder Multiply/ Divide Register File Control Control Control Instruction Predecode
Dedicated
D15:0
Status Flags
Decode Sequencing
Instruction Decoder
Prefetcher Limit Checker
Decoded Instruction Queue
Code Stream
Byte Code Queue
Instruction Prefetch
A2851-02
Figure 3-2. Intel386CX Processor Internal Block Diagram
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
functional units Intel386 processor are:
Core Unit Instruction Prefetch Unit Instruction Decode Unit Execution Unit Segmentation Unit Paging Unit Core Unit
3.2.1
Core Unit provides interface between processor environment. accepts internal requests instruction fetches (from Instruction Prefetch Unit) data transfers (from Execution Unit), prioritizes requests. same time, generates processes signals perform current cycle. These signals include address, data, control outputs accessing external memory I/O. Core Unit also controls interface external masters coprocessors. 3.2.2 Instruction Prefetch Unit
Instruction Prefetch Unit performs program look ahead function CPU. When Core Unit performing cycles execute instruction, Instruction Prefetch Unit uses Core Unit fetch sequentially along instruction byte stream. These prefetched instructions stored Instruction Queue await processing Instruction Decode Unit. Instruction prefetches given lower priority than data transfers; assuming zero wait state memory access, prefetch activity never delays execution. other hand, when there data transfer requested, prefetching uses cycles that would otherwise idle. 3.2.3 Instruction Decode Unit
Instruction Decode Unit takes instruction stream bytes from Prefetch Queue translates them into microcode. decoded instructions then stored three-deep Instruction Queue (FIFO) await processing Execution Unit. Immediate data opcode offsets also taken from Prefetch Queue. decode unit works parallel with other units begins decoding when there free slot FIFO there bytes prefetch queue. Opcodes decoded rate byte clock. Immediate data offsets decoded clock regardless their length.
CORE OVERVIEW
3.2.4
Execution Unit
Execution Unit executes instructions from Instruction Queue therefore communicates with other units required complete instruction. functions three subunits given below.
Control Unit contains microcode special parallel hardware that speeds multiply,
divide, effective address calculation.
Data Unit contains (Arithmetic Logic Unit) ALU, file eight 32-bit generalpurpose registers, 64-bit barrel shifter (which performs multiple shifts clock). Data Unit performs data operations requested Control Unit.
Protection Test Unit checks segmentation violations under control
microcode. speed execution memory reference instructions, Execution Unit partially overlaps execution memory reference instruction with previous instruction. 3.2.5 Segmentation Unit
Segmentation Unit translates logical addresses into linear addresses request Execution Unit. on-chip Segment Descriptor Cache stores currently used segment descriptors speed this translation. same time performs translation, Segmentation Unit checks bus-cycle segmentation violations. (These checks separate from static segmentation violation checks performed Protection Test Unit.) translated linear address truncated 24-bit physical address. 3.2.6 Paging Unit
When Intel386 processor paging mechanism enabled, Paging Unit translates linear addresses generated Segmentation Unit Instruction Prefetch Unit into physical addresses. (When paging enabled, physical address same linear address, translation necessary.) Page Descriptor Cache stores recently used Page Directory Page Table entries Translation Lookaside Buffer (TLB) speed this translation. Paging Unit forwards physical addresses Core Unit perform memory accesses.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
CORE Intel386 PROCESSOR INTERFACE
Intel386 processor peripherals connected Intel386 processor core through internal Interface Unit (BIU). controls internal peripheral accesses external memory accesses. Because between Intel386 processor core external bus, Intel386 processor timings identical those Intel386 processor Intel386 processor. Intel386 processor numeric coprocessor interface maintained brought Intel386 processor pins. same addresses used Intel386 processor used Intel386 processor, even though there more address lines. line high coprocessor cycles. Refer "Interface Intel387SX Math Coprocessor" page 6-38 more details.
SYSTEM REGISTER ORGANIZATION
CHAPTER SYSTEM REGISTER ORGANIZATION
This chapter provides overview system registers incorporated Intel386EX processor, focusing register organization from address architecture viewpoint. chapters that cover individual peripherals describe registers detail. This chapter organized follows:
Overview (see below) Address Space PC/AT Systems (page 4-2) Expanded Address Space (page 4-3) Organization Peripheral Registers (page 4-5) Address Decoding Techniques (page 4-6) Addressing Modes (page 4-9) Peripheral Register Addresses (page 4-15) OVERVIEW
Intel386 processor register resources following categories:
Intel386 processor core architecture registers:
General purpose registers Segment registers Instruction pointer flags Control registers System address registers (protected mode) Debug registers Test registers
Intel386 processor peripheral registers:
Configuration space control registers Interrupt control unit registers Timer/counter unit registers unit registers (8237A-compatible enhanced function registers) Asynchronous serial (SIO) registers Clock generation selector registers
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Power management control registers Chip-select unit control registers Refresh control unit registers Watchdog timer control registers Synchronous serial control registers Parallel port control registers 4.1.1 Intel386 Processor Core Architecture Registers
These registers superset 8086 80286 processor registers. 16-bit 8086 80286 registers contained within 32-bit Intel386 processor core registers. detailed description Intel386 processor architecture base registers found Intel386SX Microprocessor Programmer's Reference Manual (order number 240331). 4.1.2 Intel386 Processor Peripheral Registers
Intel386 processor contains some peripherals that common compatible with PC/AT* system architecture others that useful embedded applications. peripheral registers control access these peripherals enable configure on-chip system resources such timer/counters, power management, chip selects, watchdog timer. peripheral registers reside physically expanded address space (addresses 0F000H- 0FFFFH). Peripherals that compatible with PC/AT system architecture also mapped into address space (addresses 0H-03FFH, 10-bit decode). following rules apply accessing peripheral registers after system reset:
Registers within address space accessible. Registers within expanded address space accessible only after expanded
address space enabled. ADDRESS SPACE PC/AT SYSTEMS
Intel386 processor's address space Kbytes. PC/AT platforms, operating system applications assume that only Kbyte total 64-Kbyte address space used. first bytes (addresses 00000H-00FFH) reserved platform (motherboard) resources such interrupt controllers, remaining bytes (addresses 0100H-03FFH) available "general" peripheral card resources. Since only Kbyte address space supported, add-on peripheral cards typically decode only lower address lines. Because upper address lines decoded, platform address locations address locations repeated times 1-Kbyte boundaries), covering entire 64-Kbyte address space. (See Figure 4-1.) Generally, add-on peripheral cards addresses reserved platform resources. Software running platform repetitions address locations reserved accessing platform resources.
SYSTEM REGISTER ORGANIZATION
FFFFH (64K) General Slot FD00H Platform (Reserved) FC00H (63K)
0C00H (3K) General Slot 0900H Platform (Reserved) 0800H (2K) General Slot 0500H Platform (Reserved) 0400H (1K) General Slot 0100H (256) Platform (Reserved) 0000H
A2498-01
Figure 4-1. PC/AT Address Space (10-bit Decode)
EXPANDED ADDRESS SPACE
Intel386 processor's address scheme similar that Extended Industry Standard Architecture (EISA) Enhanced Industry Standard Architecture (E-ISA) bus. Both standards maintain backward software compatibility with architecture. Platform (0-100H) accessed with 16-bit address decode located first locations. General Slot that typically used add-in boards repeated throughout Kbyte address range their 10-bit only decode. This allows repetitions first address locations every Kbyte block allocated specific slots. Each slot Kbyte size, allowing total slots. partitioning such that four groups address locations assigned each slot, total 1024 specific address locations slot.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
(See Figure 4-2.) Thus, each slot Kbyte addresses four 256-byte segments) that potentially contain extended peripheral registers.
FFFFH (64K) General Slot Slot General Slot Slot General Slot Slot General Slot Slot F000H (60K) F400H (61K) F800H (62K) FC00H (63K)
1FFFH (8K) General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot Platform 0000H (0K)
A2499-02
1C00H (7K)
1800H (6K)
1400H (5K)
1000H (4K)
0C00H (3K)
0800H (2K)
0400H (1K)
Figure 4-2. Expanded Address Space (16-bit Decode)
SYSTEM REGISTER ORGANIZATION
Intel386 processor uses slot registers needed integrated peripherals. Using this slot avoids conflicts with other devices EISA system, since EISA systems typically slot ORGANIZATION PERIPHERAL REGISTERS
registers associated with integrated peripherals physically located slot space. There sixteen Kbyte address slots space. Slot refers 0H-0FFFH; slot refers 0F000H-0FFFFH. Table shows address peripheral registers slot Note that addresses fall address ranges 0F000H-0F0FFH, 0F400H-0F4FFH, 0F800H-0F8FFH; utilizing unique sets addresses Slot
Table 4-1. Peripheral Register Address Slot
Register Description Controller Master Interrupt Controller Programmable Interval Timer Page Registers Slave Interrupt Controller Math Coprocessor Chip Select Unit Synchronous Serial Unit DRAM Refresh Control Unit Watchdog Timer Unit Asynchronous Serial Channel (COM1) Clock Generation Power Management Unit External/Internal Interface Unit Chip Configuration Registers Parallel Ports Asynchronous Serial Channel (COM2) Address Range 0F000H 0F020H 0F040H 0F080H 0F0A0H 0F0F0H 0F400H 0F480H 0F4A0H 0F4C0H 0F4F8H 0F800H 0F810H 0F820H 0F860H 0F8F8H 0F01FH 0F03FH 0F05FH 0F09FH 0F0BFH 0F0FFH 0F47FH 0F49FH 0F4BFH 0F4CFH 0F4FFH 0F80FH 0F81FH 0F83FH 0F87FH 0F8FFH
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
ADDRESS DECODING TECHNIQUES
features Intel386 processor that configurable compatibility with standard PC/AT architecture. PC/AT system, platform resources located slot address space. Intel386 processor, this means that PC/AT-compatible internal peripherals should reflected slot space operating system application software access manipulate them properly. This discussion leads concepts space expanded space. Space Expanded Space space refers lower Kbyte addresses, where only PC/AT-compatible peripherals mapped. Expanded space refers Kbytes addresses, where peripheral registers physically located. remainder this section explains special address decoding schemes manipulate register addresses within these spaces.
4.5.1
Address Configuration Register
address locations space offer special case. These address locations used access peripheral registers PC/AT system. Intel386 microprocessor other integrated solutions them enable extra address space required configuration registers specific these products. Intel386 processor, these address locations used hide peripheral registers expanded space. expanded space enabled (registers visible) disabled (registers hidden). 16-bit register location also used control mapping various internal peripherals address space. This register, REMAPCFG, defined Figure 4-3. remap bits this register control whether internal compatible peripherals mapped into space. Setting peripheral makes peripheral accessible only expanded space. Clearing peripheral makes peripheral accessible both space expanded space. access REMAPCFG register, must first enable expanded address space described next section. reset, this register cleared, mapping internal PC/AT-compatible peripherals into space.
SYSTEM REGISTER ORGANIZATION
Address Configuration Register REMAPCFG
Expanded Addr: PC/AT Address: Reset State:
0022H 0022H 0000H
Number 14-7
Mnemonic
Function Disables expanded space Enables expanded space Reserved. Makes serial channel (COM2) accessible both space expanded space Remaps serial channel (COM2) address into expanded space Makes serial channel (COM1) accessible both space expanded space Remaps serial channel (COM1) address into expanded space Makes slave 82C59A interrupt controller accessible both space expanded space Remaps slave 82C59A interrupt controller address into expanded space Makes master 82C59A interrupt controller accessible both space expanded space Remaps master 82C59A interrupt controller address into expanded space Makes address accessible both space expanded space Remaps address into expanded space Reserved. Makes timer control unit accessible both space expanded space Remaps timer control unit address into expanded space
Figure 4-3. Address Configuration Register (REMAPCFG)
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
4.5.2
Enabling Disabling Expanded Space
Intel386 processor's expanded space enabled specific write sequence addresses (Figure 4-4). Once expanded space enabled, internal peripherals (timers, DMA, interrupt controllers serial communication channels) mapped space (using REMAPCFG register) registers associated with other internal peripherals (such chip-select unit, power management unit, watchdog timer) accessed.
4.5.2.1 Programming REMAPCFG Example
expanded space enable (ESE) REMAPCFG register only three sequential write operations addresses described Figure 4-4. Once set, REMAPCFG on-chip registers expanded address range 0F000H- 0FFFFH accessed. remap bits REMAPCFG still effect even after cleared.
;;disable interrupts Enable expanded space Intel386(tm) processor peripheral initialization. 08000H Enable expanded space 23H, unlock re-map bits XCHG 22H, 22H, this point PC/AT peripherals mapped example, on-chip channels from space (slot 22H, Disables expanded space 23H, Re-enable Interrupts
Figure 4-4. Setting Code Example
REMAPCFG register write-protected until expanded space enabled. When enabling write sequence executed, sets bit. program check this whether access expanded space registers. Clearing disables expanded space. This done byte write with value address 23H. This again locks REMAPCFG register makes read-only.
SYSTEM REGISTER ORGANIZATION
ADDRESSING MODES
Combinations value individual remap bits REMAPCFG register yield four different peripheral addressing modes address decoding. 4.6.1 DOS-compatible Mode
DOS-compatible mode achieved clearing peripheral remap bits. this mode, PC/AT-compatible peripherals mapped into space. Only address lines A9:0 decoded internal peripherals. Accesses PC/AT-compatible peripherals valid, while other internal peripherals inaccessible (see Figure 4-5). This mode useful accessing internal timer, interrupt controller, serial ports, controller DOS-compatible environment.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
3FFH On-chip UART-0
On-chip UART-1
FFFFH
On-chip 8259A-2
On-chip Timer
REMAPCFG Register
F000H On-chip 8259A-1 Expanded Space
On-chip Space
Note: Shaded area indicates that expanded space peripherals accessible
A2495-02
Figure 4-5. DOS-Compatible Mode
4-10
SYSTEM REGISTER ORGANIZATION
4.6.2
Nonintrusive Mode
This mode achieved first setting (using three sequential writes), setting individual peripherals' remap bits, then clearing bit. Peripherals whose remap bits mapped space. Like DOS-compatible mode, only address lines A9:0 decoded internally. This mode useful connecting external peripheral instead using integrated peripheral. example, system might external 8237A rather than using internal unit. this configuration, bit, remap associated with unit then clear bit. this case, external 8237A accessible space, while internal accessed only after expanded space enabled. (See Figure 4-6.) 4.6.3 Enhanced Mode
This mode achieved setting clearing PC/AT-compatible peripherals' remap bits. Address lines A15:0 decoded internally. expanded space enabled PC/AT-compatible internal peripherals accessible either space expanded space. (See Figure 4-7.) application frequently requires additional peripherals, same time wants maintain compatibility ease development, this most useful mode. 4.6.4 Non-DOS Mode
This mode achieved setting setting peripherals' remap bits. Address lines A15:0 decoded internally. expanded space enabled peripherals accessed only expanded space. This mode useful systems that don't require compatibility have other custom peripherals slot space. (See Figure 4-8.) peripherals, lower bits space expanded space identical (except UARTs, whose lower bits identical). This makes correlation their respective offsets expanded spaces easier. Also, UARTs have fixed addresses. This differs from standard PC/AT configurations, which these address ranges programmable.
4-11
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
3FFH On-chip UART-0
On-chip UART-1
FFFFH
On-chip 8259A-2
On-chip Timer
REMAPCFG Register
F000H On-chip 8259A-1 Expanded Space
Internal Space
Note: Shaded area indicates that on-chip expanded space peripherals accessible
A2496-02
Figure 4-6. Example Nonintrusive DOS-Compatible Mode
4-12
SYSTEM REGISTER ORGANIZATION
3FFH On-chip UART-2
On-chip UART-1
FFFFH Other Peripherals
On-chip 8259A-2
UART-0 UART-1
On-chip Timer
Timer 8259A-2
REMAPCFG Register
8259A-1 On-chip Expanded Space
F000H
On-chip 8259A-1
On-chip Space
A2501-02
Figure 4-7. Enhanced Mode
4-13
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
3FFH
FFFFH Other Peripherals
UART-0 UART-1 Timer 8259A-2 REMAPCFG Register 8259A-1 On-chip F000H Expanded Space
Space
A2502-02
Figure 4-8. NonDOS Mode
4-14
SYSTEM REGISTER ORGANIZATION
PERIPHERAL REGISTER ADDRESSES
Table lists addresses names user-accessible peripheral registers. Registers accessed bytes words. Word accesses byte registers result sequential 8-bit transfers. default (reset) value each register shown Reset Value column. this column signifies that register bits undefined. Some address values access registers, decoded provide logic control signal. These addresses listed register Reset column.
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address PC/AT Address Access Type (Byte/Word) Register Name Reset Value
Controller Arbiter F000H F001H F002H F003H F004H F005H F006H F007H F008H F009H F00AH F00BH F00CH F00DH F00EH F00FH F010H F011H F012H F013H F014H F015H F016H F017H 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte DMA0TAR0/1 (Note DMA0BYC0/1 (Note DMA1TAR0/1 (Note DMA1BYC0/1 (Note Reserved Reserved Reserved Reserved DMACMD1/DMASTS DMASRR DMAMSK DMAMOD1 DMACLRBP DMACLR DMACLRMSK DMAGRPMSK DMA0REQ0/1 DMA0REQ2/3 DMA1REQ0/1 DMA1REQ2/3 Reserved Reserved Reserved Reserved register register register
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-15
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address F018H F019H F01AH F01BH F01CH F01DH F01EH PC/AT Address Access Type (Byte/Word) Byte Byte Byte Byte Byte Byte Byte Register Name DMABSR DMACHR/DMAIS DMACMD2 DMAMOD2 DMAIEN DMAOVFE DMACLRTC Reset Value X1X10000B register
Master Interrupt Controller F020H F021H 0020H 0021H Byte Byte ICW1m/IRRm/ISRm/ OCW2m/OCW3m ICW2m/ICW3m/ICW4m/ OCW1m/POLLm
Address Configuration Register 0022H 0022H Word REMAPCFG 0000H
Timer/counter Unit F040H F041H F042H F043H 0040H 0041H 0042H 0043H Byte Byte Byte Byte TMR0 TMR1 TMR2 TMRCON
Page Registers F080H F081H F082H F083H F084H F085H F086H F087H F088H F089H F08AH F08BH F08CH 0089H 008AH 008BH 0087H Byte Byte Byte 0081H 0082H 0083H Byte Reserved Reserved Reserved DMA1TAR2 Reserved DMA1TAR3 DMA0TAR3 DMA0TAR2 Reserved Reserved Reserved Reserved Reserved
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-16
SYSTEM REGISTER ORGANIZATION
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address F08DH F08EH F08FH F098H F099H F09AH F09BH Byte Byte PC/AT Address Access Type (Byte/Word) Register Name Reserved Reserved Reserved DMA0BYC2 DMA1BYC2 Reserved Reserved A20GATE Fast Reset F092H 0092H Byte PORT92 XXXXXX10B Reset Value
Slave Interrupt Controller F0A0H F0A1H 00A0H 00A1H Byte Byte ICW1s/IRRs/ISRs/ OCW2s/OCW3s ICW2s/ICW3s/ICW4s/ OCW1s/POLLs
Chip-select Unit F400H F402H F404H F406H F408H F40AH F40CH F40EH F410H F412H F414H F416H F418H F41AH F41CH F41EH F420H F422H Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word CS0ADL CS0ADH CS0MSKL CS0MSKH CS1ADL CS1ADH CS1MSKL CS1MSKH CS2ADL CS2ADH CS2MSKL CS2MSKH CS3ADL CS3ADH CS3MSKL CS3MSKH CS4ADL CS4ADH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-17
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address F424H F426H F428H F42AH F42CH F42EH F430H F432H F434H F436H F438H F43AH F43CH F43EH PC/AT Address Access Type (Byte/Word) Word Word Word Word Word Word Word Word Word Word Word Word Word Word Register Name CS4MSKL CS4MSKH CS5ADL CS5ADH CS5MSKL CS5MSKH CS6ADL CS6ADH CS6MSKL CS6MSKH UCSADL UCSADH UCSMSKL UCSMSKH Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FF6FH FFFFH FFFFH FFFFH
Synchronous Serial Unit F480H F482H F484H F486H F488H F48AH Word Word Byte Byte Byte Byte SSIOTBUF SSIORBUF SSIOBAUD SSIOCON1 SSIOCON2 SSIOCTR 0000H 0000H
Refresh Control Unit F4A0H F4A2H F4A4H F4A6H Word Word Word Word RFSBAD RFSCIR RFSCON RFSADD 0000H 0000H 0000H 00FFH
Watchdog Timer Unit F4C0H F4C2H F4C4H F4C6H F4C8H Word Word Word Word Word WDTRLDH WDTRLDL WDTCNTH WDTCNTL WDTCLR 003FH FFFFH 003FH FFFFH register
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-18
SYSTEM REGISTER ORGANIZATION
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address F4CAH PC/AT Address Access Type (Byte/Word) Byte Register Name WDTSTATUS Reset Value
Asynchronous Serial Channel (COM1) F4F8H F4F9H F4FAH F4FBH F4FCH F4FDH F4FEH F4FFH 03F8H 03F9H 03FAH 03FBH 03FCH 03FDH 03FEH 03FFH Byte Byte Byte Byte Byte Byte Byte Byte RBR0/TBR0/DLL0 IER0/DLH0 IIR0 LCR0 MCR0 LSR0 MSR0 SCR0 XX/XX/02H 00H/00H
Clock Generation Power Management F800H F804H Byte Word PWRCON CLKPRS 0000H
Device Configuration Registers F820H F822H F824H F826H F830H F832H F834H F836H Byte Byte Byte Byte Byte Byte Byte Byte P1CFG P2CFG P3CFG PINCFG DMACFG INTCFG TMRCFG SIOCFG
Parallel Ports F860H F862H F864H F868H F86AH F86CH F870H F872H F874H Byte Byte Byte Byte Byte Byte Byte Byte Byte P1PIN P1LTC P1DIR P2PIN P2LTC P2DIR P3PIN P3LTC P3DIR
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-19
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 4-2. Peripheral Register Addresses (Sheet
Expanded Address PC/AT Address Access Type (Byte/Word) Register Name Reset Value
Asynchronous Serial Channel (COM2) F8F8H F8F9H F8FAH F8FBH F8FCH F8FDH F8FEH F8FFH 02F8H 02F9H 02FAH 02FBH 02FCH 02FDH 02FEH 02FFH Byte Byte Byte Byte Byte Byte Byte Byte RBR1/TBR1/DLL1 IER1/DLH1 IIR1 LCR1 MCR1 LSR1 MSR1 SCR1 XX/XX/02H 00H/00H
NOTES: Byte pointer flip-flop determines which register accessed. Shaded rows indicate reserved areas.
4-20
DEVICE CONFIGURATION
CHAPTER DEVICE CONFIGURATION
Intel386EX processor provides many possible signal connections well peripheral peripheral connections. This chapter describes available configurations configure them. This chapter organized follows:
Introduction (see below) Peripheral Configuration (page 5-3) Configuration (page 5-23) Device Configuration Procedure (page 5-28) Configuration Example (page 5-28) INTRODUCTION
Device configuration process setting microprocessor's on-chip peripherals particular system design. Specifically, device configuration consists programming registers connect peripheral signals package pins interconnect peripherals. peripherals include following:
Controller (DMA) Interrupt Control Unit (ICU) Timer/counter Unit (TCU) Asynchronous Serial Units (SIO0, SIO1) Synchronous Serial Unit (SSIO) Refresh Control Unit (RCU) Chip-select Unit (CSU) Watchdog Timer Unit (WDT)
addition, configuration registers control connections from coprocessor core connections arbiter.
this chapter, terms "peripheral" "on-chip peripheral" used interchangeably. "off-chip peripheral" external Intel386 processor.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Figure shows Peripheral connections other peripherals package pins. "Internal Connection Logic" provides three kinds connections:
Connections between peripherals Connections package pins multiplexers Direct connections package pins without multiplexers
internal connection logic controlled Peripheral configuration register. Each multiplexer ("Pin Mux") connects internal signals pin. peripheral signal. second signal port signal signal from/to another peripheral. multiplexers controlled configuration registers. Some input-only pins without multiplexers ("Shared Pins Muxes") routed different peripherals. Your design should only inputs disable ignore input going second peripheral. Together, peripheral configuration registers configuration registers allow select peripherals used, interconnect them your design requires, bring selected signals package pins.
Peripherals
Microprocessor Peripheral Internal Connection Logic Peripheral Configuration Register
Pins with Muxes Muxes Control Shared Pins Muxes
Control
Configuration Registers
A2535-01
Figure 5-1. Peripheral Connections
DEVICE CONFIGURATION
PERIPHERAL CONFIGURATION
This section describes configuration each on-chip peripheral. more detailed information peripheral itself, chapter describing that peripheral. symbology used signals that share device shown Figure 5-2. signal names pin, upper signal associated with peripheral figure. lower signal parentheses alternate signal, which connects different peripheral core. When multiplexer, shown switch, register that controls noted above switch. 5.2.1 Controller, Arbiter, Refresh Unit Configuration
Figure shows controller, arbiter, refresh unit configuration. Requests data transfer shown inputs multiplexer:
serial transmitter (TXEDMA0, TXEDMA1) receiver (RBFDMA0, RBFDMA1) synchronous serial transmitter (SSTBE) receiver (SSRBF) timer (OUT1, OUT2) external source (DRQ0, DRQ1)
inputs selected configuration register (see Figure 5-3).
5.2.1.1 Using Unit with External Devices
each channel, three bits configuration register (Figure 5-3) select external request input seven request inputs from peripherals. Another enables disables that channel's acknowledge signal (DACKn#) device pin. Enable DACKn# signal only when using external request signal (DRQn) need DACKn#. acknowledge signals routed on-chip peripherals, therefore, these peripherals cannot initiate single-cycle (fly-by) transfers. external master cannot talk directly internal peripheral modules because external address lines outputs only. However, external device could channel transfer data from internal peripheral because generates addresses. This transaction would two-cycle transaction.
5.2.1.2 Service SSIO Peripheral
unit useful servicing SSIO peripheral operating high baud rate. high baud rates, interrupt response time core long allow serial channels interrupt service receive-buffer-full condition. time interrupt service routine (ISR) ready transfer receive-buffer data memory, data would have been loaded into buffer. issue interrupt latency which amount time processor takes from recognizing interrupt executing first line code ISR. This interrupt latency needs calculated determine handle high baud rate. Interrupt Latency high, data transfers from serial channels occur within cycles time that serial unit ready move data using appropriately
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
configured channel. SSIO inputs selected configuration register (Figure 5-3).
5.2.1.3 Using Timer Initiate Transfers
timer output (OUT1, OUT2) initiate periodic data transfers DMA. channel programmed transfer, then timer output pulse triggers transfer. most useful timer combinations this type transfer periodic timer modes (mode mode with block-transfer mode programmed. Chapter "TIMER/COUNTER UNIT," Chapter "DMA CONTROLLER," more information program peripherals.
5.2.1.4 Limitations Signal Multiplexing
signal multiplexing preclude simultaneous channel another peripheral specific peripheral signal (see Figure 5-2). example, using channel with external requester device precludes using channel multiplexed signal pairs DRQ1/RXD1 DACK1#/TXD1. Please refer Intel386EX Microprocessor Multiplexing (Order Number 272587) complete diagram multiplexed signals.
DEVICE CONFIGURATION
DMACFG.2:0
DREQ0
RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO) OUT1 (TCU) RBFDMA1 (SIO1) TXEDMA0 (SIO0) SSRBF (SSIO)
SIO1
DRQ0 (DCD1#)
DMACFG.3
PINCFG.4
DMAACK0# DMACFG.6:4 DREQ1
From
DACK0# (CS5#)
RBFDMA1 (SIO1 TXEDMA0 (SIO0) SSRBF (SSIO) OUT2 (TCU) RBFDMA0 (SIO0) TXEDMA1 (SIO1) SSTBE (SSIO)
SIO1
DRQ1 (RXD1)
DMACFG.7
PINCFG.2
DMAACK1# DMAINT Process
From SIO1
DACK1# (TXD1)
PINCFG.3
From SIO1
EOP# (CTS1#) HOLD (P1.6)
P1CFG.6
HOLD To/From Port
Core HOLD
Arbiter
P1CFG.7
HLDA To/From Port Refresh Unit
From Core HLDA
HLDA (P1.7)
PINCFG.6
REFRESH# From
REFRESH# (CS6#)
Alternate signals parentheses.
A2516-02
Figure 5-2. Configuration DMA, Arbiter, Refresh Unit
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Configuration DMACFG (read/write) D1MSK D1REQ2 D1REQ1 D1REQ0
Expanded Addr: Addr: Reset State:
F830H
D0MSK
D0REQ2
D0REQ1
D0REQ0
Number
Mnemonic D1MSK Acknowledge Mask:
Function
channel acknowledge (DMAACK1#) signal masked. Masks channel acknowledge (DMAACK1#) signal. Useful when channel request (DREQ1) input connected internal peripheral. D1REQ2:0 Channel Request Connection: Connects eight possible hardware sources channel request input (DREQ1). D0MSK DRQ1 (external peripheral) channel receive buffer full signal (RBFDMA1) channel transmit buffer empty signal (TXEDMA0) SSIO receive holding buffer full signal (SSRBF) counter output signal (OUT2) channel receive buffer full signal (RBFDMA0) channel transmit buffer empty signal (TXEDMA1) SSIO transmit holding buffer empty signal (SSTBE)
Acknowledge Mask: channel acknowledge (DMAACK0#) signal masked. Masks channel acknowledge (DMAACK0#) signal. Useful when channel request (DREQ0) input connected internal peripheral.
D0REQ2:0
Channel Request Connection: Connects eight possible hardware sources channel request input (DREQ0). DRQ0 (external peripheral) channel receive buffer full signal (RBFDMA0) channel transmit buffer empty signal (TXEDMA1) SSIO transmit holding buffer empty signal (SSTBE) counter output signal (OUT1) channel receive buffer full signal (RBFDMA1) channel transmit buffer empty signal (TXEDMA0) SSIO receive holding buffer full signal (SSRBF)
Figure 5-3. Configuration Register (DMACFG)
DEVICE CONFIGURATION
5.2.2
Interrupt Control Unit Configuration
interrupt control unit (ICU) comprises 82C59A interrupt controllers connected cascade, shown Figure 5-4. (See Chapter more information.) Figure describes interrupt configuration register (INTCFG). receives requests from eight internal sources:
Three outputs from timer/counter unit (OUT2:0) output from each serial units (SIOINT1:0) output from synchronous serial unit (SSIOINT) output from unit (DMAINT) output from unit (WDTOUT#)
addition, controls interrupt sources external pins:
INT3:0 (multiplexed with port signals P3.5:2) enabled disabled P3CFG
register (see Figure 5-18).
INT7:4 share their package pins with four inputs: TMRGATE1, TMRCLK1,
TMRGATE0, TMRCLK0. These signal pairs multiplexed; however, inputs enabled disabled INTCFG register.
INT9:8 share their pins with TMROUT1, TMROUT0, P3.1, P3.0
three cascade outputs (CAS2:0) should enabled when external 82C59A module connected INT9:8 INT3:0 signals. cascade outputs ORed with address lines A18:16. "Interrupt Acknowledge Cycle" page 6-23 details. Tables configure functionality master 82C59A's IR3, inputs, associated external pins.
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 5-1. Master's Connections
Function connected SIOINT1 P3.1 selected (P3.1) connected SIOINT1 OUT1 connected (TMROUT1) internally driven P3.1 selected (P3.1) connected (INT8) connected SIOINT1 P3.1 selected (P3.1) connected SIOINT1 (INT8) must left floating NOTE: don't care INTCFG.6 MCR1.3 P3CFG.1
Table 5-2. Master's Connections
Function connected SIOINT0 P3.0 selected (P3.0) connected SIOINT0 OUT0 connected (TMROUT0) internally driven P3.0 selected (P3.0) connected (INT9) connected SIOINT0 P3.0 selected (P3.0) connected SIOINT0 (INT9) must left floating NOTE: don't care INTCFG.5 MCR0.3 P3CFG.0
DEVICE CONFIGURATION
8259A Master INTR core)
P3CFG.2 INTCFG.6
OUT0 (TCU) To/From Port SIOINT1
P3CFG.2
MCR1.3 SIOINT1 INTCFG.6
INT0 (P3.2)
P3CFG.1
OUT1(TCU) INTCFG.5 P3CFG.3 P3CFG.4 CAS2:0 P3CFG.5 INTCFG.0 8259A Slave INTCFG.4 DMAINT INTCFG.1 SSIOINT OUT1(TCU) OUT2(TCU) To/From Port SIOINT0
P3.1
INT8 TMROUT1 (P3.1)
MCR0.3 SIOINT0
INTCFG.5 P3GFG.0 INT9 TMROUT0 P3.0 OUT0(TCU) (P3.0) P3CFG.3 INT1 (P3.3) To/From Port P3CFG.4 INT2 (P3.4) To/From Port
P3CFG.5
INT3 (P3.5)
INT4 (TMRCLK0) INT5 (TMRGATE0)
INT6 (TMRCLK1)
CAS2:0
INTCFG.2
INTCFG.3 INT7 INTCFG.7 CAS2:0 (A18:16) (TMRGATE1)
WDTOUT#
A18:16
Alternate signals parentheses Heavier lines indicate multiple signals.
A2522-03
Figure 5-4. Interrupt Control Unit Configuration
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Interrupt Configuration INTCFG (read/write) SWAP
Expanded Addr: Addr: Reset State:
F832H
IR5/IR4
Number
Mnemonic Cascade Enable:
Function
Disables cascade signals CAS2:0 from appearing A18:16 address lines during interrupt acknowledge cycles. Enables cascade signals CAS2:0, providing access external slave 82C59A devices. cascade signals used address specific slaves. enabled, slave appear A18:16 address lines during interrupt acknowledge cycles, high during idle cycles. SWAP Internal Master Connection: Table page configuration options. Internal Master Connection: Table page configuration options. INT6/DMAINT Connection: Connects DMAINT slave IR4. Connects INT6 slave IR5. Connects INT6 slave IR4. Connects DMAINT slave IR5. Internal Slave Connection: Connects slave signal. Connects INT7 slave signal. IR5/IR4 Internal Slave Connection: These depend whether INTCFG.4 clear. Connects slave signal. Connects either INT6 DMAINT slave signal. Internal Slave Connection: Connects SSIO interrupt signal (SSIOINT) slave signal. Connects INT5 slave signal. Internal Slave Connection: Connects slave signal. Connects INT4 slave signal.
Figure 5-5. Interrupt Configuration Register (INTCFG)
5-10
DEVICE CONFIGURATION
5.2.3
Timer/counter Unit Configuration
three-channel Timer/counter Unit (TCU) configuration register (TMRCFG) shown Figure Figure 5-7. clock inputs external signals (TMRCLK2:0) on-chip programmable clock (PSCLK). clock inputs held programming bits TMRCFG register. gate inputs controlled through software using TMRCFG.6 appropriate GTnCON bits TMRCFG register. Several timer signals interrupt control unit (see Figure 5-4). Timer/counter0 Timer/counter1 signals selected individually. contrast, Timer/counter2 signals (TMRCLK2, TMRGATE2, TMROUT2) selected group. Note that using Timer/counter2 signals precludes coprocessor signals (PEREQ, BUSY#, ERROR#). CLKINn GATEn inputs Timer/counter0 Timer/counter1 routed directly shared input pins, TMRCLK0/INT4, TMRCLK1/INT6, TMRGATE0/INT5 TMRGATE1/INT7. OUTn inputs these counters connected pins TMROUT0/INT9/P3.0 TMROUT1/INT8/P3.1 respectively, using bits registers P3CFG INTCFG.
5-11
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Timer/Counter Unit CLKIN0 TMRCFG.6 GATE0
TMRCFG.7 TMRCFG.0 PSCLK TMRCFG.1 P3CFG.0 TMROUT0 (INT9) (P3.0) TMRGATE0 (INT5) TMRCLK0 (INT4)
TMRCFG.1
OUT0 To/From Port TMRCFG.2 CLKIN1 TMRCFG.6 GATE1 TMRCFG.3 PSCLK
TMRCFG.3 ICU, P3CFG.1
TMRCLK1 (INT6)
TMRGATE1 (INT7) TMROUT1 (INT8) (P3.1)
OUT1 To/From Port TMRCFG.4 CLKIN2 Core TMRCFG.6 GATE2 TMRCFG.5 TMRCFG.5 Core PSCLK
PINCFG.5
TMRCLK2 (PEREQ) TMRGATE2 (BUSY#)
ICU, OUT2 Core Alternate signals parentheses.
TMROUT2 (ERROR#)
A2517-03
Figure 5-6. Timer/Counter Unit Configuration
5-12
DEVICE CONFIGURATION
Timer Configuration TMRCFG (read/write)
Expanded Addr: Addr: Reset State: GT2CON CK2CON GT1CON CK1CON
F834H
TMRDIS Number
SWGTEN Mnemonic TMRDIS
GT0CON
CK0CON
Function Timer Disable: Enables CLKINn signals. Disables CLKIN signals.
SWGTEN
Software GATEn Enable Connects GATE either TMRGATEn pin. Enables GT2CON, GT1CON, GT0CON control connections GATE2, GATE1 GATE0 respectively.
GT2CON
Gate Connection: SWGTEN GT2CON
Connects GATE2 VCC. Connects GATE2 TMRGATE2 pin. Turns GATE2 off. Turns GATE2
CK2CON
Clock Connection: Connects CLKIN2 internal PSCLK signal. Connects CLKIN2 TMRCLK2 pin.
GT1CON
Gate Connection: SWGTEN GT1CON
Connects GATE1 VCC. Connects GATE1 TMRGATE1 pin. Turns GATE1 off. Turns GATE1
CK1CON
Clock Connection: Connects CLKIN1 internal PSCLK signal. Connects CLKIN1 TMRCLK1 pin.
GT0CON
Gate Connection: SWGTEN GT0CON
Connects GATE0 VCC. Connects GATE0 TMRGATE1 pin. Turns GATE0 off. Turns GATE0
CK0CON
Clock Connection: Connects CLKIN0 internal PSCLK signal. Connects CLKIN0 TMRCLK0 pin.
Figure 5-7. Timer Configuration Register (TMRCFG)
5-13
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
5.2.4
Asynchronous Serial Configuration
Figures show asynchronous serial unit configuration, consisting channels SIO0 SIO1. Each channel output (SIOINT0, SIOINT1) interrupt control unit (see Figure 5-4) outputs unit. (These signals package pins.) SIOINTn active when status signals (receiver line status, receiver buffer full, transmit buffer empty, modem status) enabled. SIO0 pins multiplexed with port signals. Using SIO1 precludes using channel external requests multiplexing transmit receive signals with signals (RXD1/DRQ1, TXD1/DACK1#).
NOTE
Using SIO1 modem signals RTS1#, DSR1#, DTR1#, RI1# precludes SSIO unit.
5-14
DEVICE CONFIGURATION
SIO0
SIOCFG.0 P3CFG.7 COMCLK (P3.7) SERCLK To/From Port
BCLKIN
Receive Data SIOINT0 RBFDMA0 TXEDMA0 Transmit Data SIOCFG.6 To/From Port To/From Port
P2CFG.5 RXD0 (P2.5)
To/From Port
P2CFG.6 P2CFG.7 TXD0 (P2.6) CTS0# (P2.7)
Clear Send
Request Send To/From Port
P1CFG.1 RTS0# (P1.1) DSR0# (P1.3)
Data Ready To/From Port
P1CFG.3
Data Carrier Detect To/From Port
P1CFG.0 DCD0# (P1.0)
Data Terminal Ready
To/From Port
P1CFG.2 P1CFG.4 DTR0# (P1.2) RI0# (P1.4)
Ring Indicator
To/From Port
Alternate signals parentheses.
A2521-02
Figure 5-8. Serial Unit Configuration
5-15
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
SIO1
SIOCFG.1 P3CFG.7 COMCLK (P3.7) SERCLK To/From Port
BCLKIN
Receive Data SIOINT1 RBFDMA1 TXEDMA1 Transmit Data SIOCFG.7
RXD1 (DRQ1)
From
PINCFG.2 PINCFG.3 TXD1 (DACK1#) CTS1# (EOP#)
Clear Send
To/From
Request Send From SSIO
PINCFG.0 RTS1# (SSIOTX) DSR1# (STXCLK)
Data Ready
To/From SSIO
Data Carrier Detect
DCD1# (DRQ0)
Data Terminal Ready
To/From SSIO SSIO
PINCFG.1 DTR1# (SRXCLK) RI1# (SSIORX)
Ring Indicator
Alternate signals parentheses.
A2519-02
Figure 5-9. Serial Unit Configuration
5-16
DEVICE CONFIGURATION
SSIO Configuration SIOCFG (read/write)
Expanded Addr: Addr: Reset State:
F836H
SSBSRC
S1BSRC
S0BSRC
Number
Mnemonic
Function SIO1 Modem Signal Connections: Connects SIO1 modem input signals package pins. Connects SIO1 modem input signals internally.
SIO0 Modem Signal Connections: Connects SIO0 modem input signals package pins. Connects SIO0 modem input signals internally.
SSBSRC
Reserved. These bits undefined; compatibility with future devices, modify these bits. SSIO Baud-rate Generator Clock Source: Connects internal PSCLK signal SSIO baud-rate generator. Connects internal SERCLK signal SSIO baud-rate generator.
S1BSRC
SIO1 Baud-rate Generator Clock Source: Connects COMCLK SIO1 baud-rate generator. Connects internal SERCLK signal SIO1 baud-rate generator.
S0BSRC
SIO0 Baud-rate Generator Clock Source: Connects COMCLK SIO0 baud-rate generator. Connects internal SERCLK signal SIO0 baud-rate generator.
Figure 5-10. SSIO Configuration Register (SIOCFG)
5-17
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
5.2.5
Synchronous Serial Configuration
synchronous serial unit (SSIO) shown Figure 5-11. single configuration register SIOCFG register (Figure 5-10). transmit buffer empty receive buffer full signals (SSTBE SSRBF) unit (Figure 5-2), interrupt signal (SSIOINT) goes (Figure 5-4). Depending settings SSIOCON1 register (see Chapter 13), SSIOINT asserted conditions: receive buffer full transmit buffer empty. Note that using SSIO signals precludes four SIO1 modem signals.
SSIO
SIOCFG.2 PSCLK SERCLK SSIORX (RI1#)* PINCFG.0 SSIOTX (RTS1#) STXCLK (DSR1#) PINCFG.1 SRXCLK (DTR1#)
BCLKIN
SSTBE SSRBF SSIOINT Receive Data
SIO1 Transmit Data From SIO1 Transmit Clock SIO1 Receive Clock From SSIO1 *Alternate signals parentheses.
A2518-02
Figure 5-11. SSIO Unit Configuration
5-18
DEVICE CONFIGURATION
5.2.6
Chip-select Unit Clock Power Management Unit Configuration
Figure 5-12 shows multiplexing signals Chip-select Unit Clock Power Management Unit. Chip-select signals, CS6# CS5# multiplexed with REFRESH# signal from Refresh Control Unit DACK0# signal from Unit, respectively. Bits PINCFG register (see Figure 5-15) control these multiplexers. CS3#, CS2#, CS1# CS0# multiplexed with Port signals, P2.3, P2.2, P2.1 P2.0, respectively. Bits P2CFG register (see Figure 5-17) control these multiplexers. PWRDOWN output signal Clock Power Management Unit multiplexed with Port signal, P3.6. P3CFG register (see Figure 5-18) controls this multiplexer.
5-19
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
CS0# To/From Port CS1# To/From Port CS2# To/From Port CS3# To/From Port CS4# To/From Port CS5# DACK0# (DMA) CS6# REFRESH# (RCU)
P2CFG.0 P2CFG.1 P2CFG.2 P2CFG.3 P2CFG.4 PINCFG.4 PINCFG.6
CSO# (P2.0) CS1# (P2.1) CS2# (P2.2) CS3# (P2.3) CS4# (P2.4) CS5# (DACK0#) CS6# (REFRESH#)
Clock Power Management Unit
P3CFG.6 PWRDOWN To/From Port
PWRDOWN (P3.6)
A3380-01
Figure 5-12. Configuration Chip-select Unit Clock Power Management Unit
5-20
DEVICE CONFIGURATION
5.2.7
Core Configuration
Three coprocessor signals (ERROR#, PEREQ, BUSY# Figure 5-13) routed core, determined PINCFG register (see Figure 5-15). signal multiplexing pins, coprocessor Timer/counter2 cannot used simultaneously.
Core
PINCFG.5 PINCFG.5 ERROR# (TMROUT2)
ERROR#
From
PEREQ
PEREQ (TMRCLK2)
BUSY# RESET Timing Generation RESET From Chip RESET PORT92.1 Chip-select Unit LOCK# To/From Port P1CFG.5 LOCK# (P1.5) BUSY# (TMRGATE2)
PORT92.0
Alternate signals parentheses.
A2520-02
Figure 5-13. Core Configuration
5-21
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Setting PORT92 register (see Figure 5-14) resets core without resetting peripherals. Unlike RESET pin, which asynchronous used synchronize internal clocks CLK2, this core-only reset synchronized with on-chip clocks does affect on-chip clock synchronization. After CPU-RESET this still must cleared then cause another core-only reset. Clearing PORT92 register forces address line This affects only addresses generated core; addresses generated refresh control unit affected.
Port Configuration PORT92 (read/write) A20G Expanded Addr: Addr: Reset State: F092H 0092H XXXXXX10B CPURST
Number
Mnemonic A20G
Function Reserved. These bits undefined; compatibility with future devices, modify these bits. Grounded: Clearing this forces address line This affects addresses generated only core. Addresses generated Refresh Unit affected this bit. Setting this leaves core-generated addresses unmodified.
CPURST
Reset: Clearing this performs operation. Setting this resets core without resetting peripherals. This must cleared before issuing another reset.
Figure 5-14. Port Configuration Register (PORT92)
5-22
DEVICE CONFIGURATION
CONFIGURATION
Most microprocessor's package pins support peripheral functions. Some these pins routed peripheral inputs without multiplexer. These input-signal pairs listed Table 5-3. connected both peripheral inputs. remaining pins supporting signals have multiplexers. each such pin, configuration register enables signals. Table lists bits each four configuration registers. These abbreviated register tables discussed "Configuration Example" page 5-28. When configuring ports INT8 INT9, first appropriate INTCFG bit, then P3CFG bit. Setting bits this order avoids potential contention INT8 INT9.
Table 5-3. Signal Pairs Pins without Multiplexer
Names DRQ0/ DCD1# Signal Descriptions External Request indicates that off-chip peripheral requires service. Data Carrier Detect SIO1 indicates that modem data detected asynchronous serial channel's data carrier. External Request1 indicates that off-chip peripheral requires service. Receive Data SIO1 accepts serial data from modem data asynchronous serial channel SIO1. Data Ready SIO1 indicates that modem data ready establish communication link with asynchronous serial channel SIO1. SSIO Transmit Clock synchronizes data being sent synchronous serial port. RI1#/ SSIORX Ring Indicator SIO1 indicates that modem data received telephone ringing signal. SSIO Receive Serial Data accepts serial data (most-significant first) being sent synchronous serial port. TMRCLK0/ INT4 Timer/Counter0 Clock Input serve external clock input timer/counter0. (The timer/counters also clocked internally.) Interrupt undedicated external interrupt. TMRGATE0/ INT5 Timer/Counter0 Gate Input control timer/counter0's counting (enable, disable, trigger, depending programmed mode). Interrupt undedicated external interrupt. TMRCLK1/ INT6 Timer/Counter1 Clock Input serve external clock input timer/counter1. (The timer/counters also clocked internally.) Interrupt undedicated external interrupt. TMRGATE1/ INT7 Timer/Counter1 Gate Input control timer/counter1's counting (enable, disable, trigger, depending programmed mode). Interrupt undedicated external interrupt.
DRQ1/ RXD1
DSR1#/ STXCLK
5-23
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Configuration PINCFG (read/write)
Expanded Addr: Addr: Reset State:
F826H
Number
Mnemonic
Function Reserved. This undefined; compatibility with future devices, modify this bit. Mode: Selects CS6# package pin. Selects REFRESH# package pin.
Mode: Selects coprocessor signals, PEREQ, BUSY#, ERROR#, package pins. Selects timer control unit signals, TMROUT2, TMRCLK2, TMRGATE2, package pins.
Mode: Selects DACK0# package pin. Selects CS5# package pin.
Mode: Selects EOP# package pin. Selects CTS1# package pin.
Mode: Selects DACK1# package pin. Selects TXD1 package pin.
Mode: Selects SRXCLK package pin. Selects DTR1# package pin.
Mode: Selects SSIOTX package pin. Selects RTS1# package pin.
Figure 5-15. Configuration Register (PINCFG)
5-24
DEVICE CONFIGURATION
Port Configuration P1CFG (read/write)
Expanded Addr: Addr: Reset State:
F820H
Number
Mnemonic Mode:
Function
Selects P1.7 package pin. Selects HLDA package pin. Mode: Selects P1.6 package pin. Selects HOLD package pin. Mode: Selects P1.5 package pin. Selects LOCK# package pin. Mode: Selects P1.4 package pin. Selects RI0# package pin. Mode: Selects P1.3 package pin. Selects DSR0# package pin. Mode: Selects P1.2 package pin. Selects DTR0# package pin. Mode: Selects P1.1 package pin. Selects RTS0# package pin. Mode: Selects P1.0 package pin. Selects DCD0# package pin.
Figure 5-16. Port Configuration Register (P1CFG)
5-25
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Port Configuration P2CFG (read/write)
Expanded Addr: Addr: Reset State:
F822H
Number
Mnemonic Mode:
Function
Selects P2.7 package pin. Selects CTS0# package pin. Mode: Selects P2.6 package pin. Selects TXD0 package pin. Mode: Selects P2.5 package pin. Selects RXD0 package pin. Mode: Selects P2.4 package pin. Selects CS4# package pin. Mode: Selects P2.3 package pin. Selects CS3# package pin. Mode: Selects P2.2 package pin. Selects CS2# package pin. Mode: Selects P2.1 package pin. Selects CS1# package pin. Mode: Selects P2.0 package pin. Selects CS0# package pin.
Figure 5-17. Port Configuration Register (P2CFG)
5-26
DEVICE CONFIGURATION
Port Configuration P3CFG (read/write)
Expanded Addr: Addr: Reset State:
F824H
Number
Mnemonic Mode:
Function
Selects P3.7 package pin. Selects COMCLK package pin. Mode: Selects P3.6 package pin. Selects PWRDOWN package pin. Mode: Selects P3.5 package pin. Connects master package (INT3). Mode: Selects P3.4 package pin. Connects master package (INT2). Mode: Selects P3.3 package pin. Connects master package (INT1). Mode: Selects P3.2 package pin. Connects master package (INT0). Mode: Table page configuration options. Mode: Table page configuration options.
Figure 5-18. Port Configuration Register (P3CFG)
5-27
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
DEVICE CONFIGURATION PROCEDURE
Before configuring microprocessor, make following selections:
peripherals used signals available package pins desired peripheral-peripheral peripheral-core connections
Although final decisions regarding these selections influenced possible configurations, recommend that initially make selections without regard limitations configurations. suggest following procedure configuring device your design. aide recording steps procedure example configuration given "Configuration Example" page 5-28. Configuration. each desired signal, consult peripheral configuration diagram find value configuration register that connects signal device pin. When signal shares that multiplexer, make note companion signal. Peripheral Configuration. each peripheral your design, consult peripheral configuration diagram peripheral configuration register find values your desired internal connections. Configuration Review. Review results steps configuration registers have conflicting values. conflicts exist, follow steps Attempt resolve configuration conflicts first. some cases find that using different peripheral channel resolves conflict. Attempt resolve peripheral configuration conflicts.
conflicts remain, consider peripheral substitutions. CONFIGURATION EXAMPLE
This section presents example PC/AT*-compatible configuration. last tables blank; them worksheets follow steps configuration process. 5.5.1 Example Design Requirements
example PC/AT-compatible design with following requirements:
Interrupt Control Unit:
External interrupt inputs available package pins: INT1:0, INT7:4
Timer Control Unit:
Counters Clock input on-chip programmable clock (PSCLK); signals connected externally.
5-28
DEVICE CONFIGURATION
Counter Clock input on-chip programmable clock (PSCLK); signals connected package pins
Unit:
Used
Asynchronous Serial channel (SIO0):
Clock input internal clock SERCLK RXD0, TXD0 connected package pins Modem Signals connected internally.
Asynchronous Serial channel (SIO1):
Clock input internal clock SERCLK Modem signals externally connected
Synchronous Serial (SSIO):
Used
Chip Select:
Chip select signals CS6#, CS5:1#, UCS# connected package pins
Core Arbiter:
Coprocessor signals connected package pins HOLD HLDA connected package pins LOCK# PWRDOWN connected package pins 5.5.2 Example Design Solution
configuration register values example design recorded following abbreviated register tables. Blank worksheets provided when designing your system. Table summarizes selections would need make configuration registers implement example design. Tables through summarize selections would make peripheral configuration registers.
5-29
Intel386EX EMBEDDED MICROPROCESSOR USER'S MANUAL
P1CFG P1.7 HLDA
Value
P2CFG P2.7 CTS0#
Value
P3CFG P3.7 COMCLK
Value
P1.6 HOLD
P2.6 TXD0
P3.6 PWRDOWN
P1.5 LOCK#
P2.5 RXD0
P3.5 INT3
P1.4 RIO#
P2.4 CS4#
P3.4 INT2
P1.3 DSR0#
P2.3 CS3#
P3.3 INT1
P1.2 DTR0#
P2.2 CS2#
P3.2 INT0
P1.1 RTS0#
P2.1 CS1#
P3.1
P1.0 DCD0#
P2.0 CS0#
P3.0
PINCFG Reserved CS6# REFRESH#
Value
Pins Muxes DRQ0 DCD1# DRQ1
Pins Muxes TMRCLK0 INT4 TMRGATE0
Coprocessor Sigs.1 TMR2 Signals2
RXD1 DSR1#
INT5 TMRCLK1
DACK0# CS5#
STXCLK RI1#
INT6 TMRGATE1
EOP# CTS1#
SSIORX
INT7
DACK1# TXD1
NOTES:
SRXCLK DTR1#
PEREQ, BUSY#, ERROR# TMROUT2, TMRCLK2, TMRGATE2
SSIOTX RTS1#
Table 5-4. Example Configuration Registers
5-30
DEVICE CONFIGURATION
Enables DACK1# chip Disables DACK1# chip
DMACFG
Value
DRQ1 (external peripheral) connected DREQ1 channel receive buffer full signal (RBFDMA1) connected DREQ1 channel transmit buffer empty signal (TXEDMA0) DREQ1 =SSIO receive holding buffer full signal (SSRBF) DREQ1 counter output signal (OUT2) DREQ1 channel receive buffer full signal (RBFDMA0) DREQ1 channel transmit buffer empty signal (TXEDMA1) DREQ1 SSIO transmit hol

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