Operation Integrated Floating-Point Unit Speed-Multiplying Technology

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EMBEDDED WRITE-BACK ENHANCED IntelDX4PROCESSOR
Operation Integrated Floating-Point Unit Speed-Multiplying Technology 32-Bit RISC Technology Core 16-Kbyte Write-Back Cache Technology Data Parity Generation Checking Boundary Scan (JTAG) 3.3-Volt Processor, MHz,
208-Lead Shrink Quad Flat Pack (SQFP)
Core Operation with Tolerant 3.3-Volt Processor, MHz,
208-Lead Shrink Quad Flat Pack (SQFP) 168-Pin Grid Array (PGA) Burst Cycles Binary Compatible with Large Software Dynamic Sizing 16-bit Data Base Devices Buffers
64-Bit Interunit Transfer
32-Bit Data 32-Bit Data Linear Address
CLKMUL Core Clock Clock Multiplier
Barrel Shifter Register File
Base/ Index
Segmentation Unit Descriptor Registers Limit Attribute
Interface Cache Unit
A31-A2 BE3#- BE0#
Paging Unit
Address Drivers Write Buffers Data Transceivers Control
ADS# W/R# D/C# M/IO# RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR SMI# SMIACT# FERR# IGNNE# STPCLK# D31-D0
Physical Address
Translation Lookaside Buffer
Kbyte Cache
Displacement
Request Sequencer Prefetcher Burst Control 32-Byte Code Queue Bytes Size Control Cache Control Parity Generation Control Boundary Scan Control
MicroInstruction
BRDY# BLAST#
BS16# BS8#
Floating Point Unit
Control Protection Test Unit
Code Stream Instruction Decode
KEN# FLUSH# AHOLD EADS# CACHE# HITM# WB/WT#
Floating Point Register File
Control
Decoded Instruction Path
PCHK# DP3-DP0
A3232-01
Figure Embedded Write-Back Enhanced IntelDX4Processor Block Diagram
Information this document provided connection with Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes these specifications time, without notice. Microprocessor products have minor variations this specification known errata. INTEL CORPORATION, 1995 October 1995 Order Number: 272771-001
CONTENTS
EMBEDDED WRITE-BACK ENHANCED IntelDX4PROCESSOR
INTRODUCTION Features Family Members THIS DOCUMENT DESCRIPTIONS Assignments Quick Reference ARCHITECTURAL FUNCTIONAL OVERVIEW CPUID Instruction 4.1.1 Operation CPUID Instruction Identification After Reset Boundary Scan (JTAG) 4.3.1 Device Identification 4.3.2 Boundary Scan Register Bits Order ELECTRICAL SPECIFICATIONS Maximum Ratings Specifications Specifications Capacitive Derating Curves MECHANICAL DATA Package Dimensions Package Thermal Specifications FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Embedded Write-Back Enhanced IntelDX4Processor Block Diagram Package Diagram 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4Processor Package Diagram 168-Pin Embedded Write-Back Enhanced IntelDX4Processor Waveform Input Setup Hold Timing Input Setup Hold Timing PCHK# Valid Delay Timing Output Valid Delay Timing Maximum Float Delay Timing Waveform Test Signal Timing Diagram
Figure Figure Figure Figure TABLES Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
CONTENTS
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition 208-Lead SQFP Package Dimensions Principal Dimensions Data 168-Pin Grid Array Package
Embedded Write-Back Enhanced IntelDX4Processor Pinout Differences 208-Lead SQFP Package Assignment 208-Lead SQFP Package Cross Reference 208-Lead SQFP Package Pinout Differences 168-Pin Package Assignment 168-Pin Package Cross Reference 168-Pin Package Embedded Write-Back Enhanced IntelDX4Processor Descriptions Output Pins Input/Output Pins Test Pins Input Pins CPUID Instruction Description Boundary Scan Component Identification Code (Write-Through/Standard Mode) Boundary Scan Component Identification Code (Write-Back/Enhanced Mode) Absolute Maximum Ratings Operating Supply Voltages Specifications Values Characteristics Specifications Test Access Port 168-Pin Ceramic Package Dimensions Ceramic Package Dimension Symbols Thermal Resistance, (°C/W) Thermal Resistance, (°C/W) Maximum Tambient, (°C)
INTRODUCTION
Embedded Write-Back Enhanced IntelDX4Processor
Features
embedded Write-Back Enhanced IntelDX4processor provides high performance 32-bit, embedded applications. Designed applications that need floating-point unit, processor ideal embedded designs running Microsoft* Windows*, OS/2*, UNIX* applications written Intel architecture. Projects completed quickly using wide range software tools, utilities, assemblers compilers that available desktop computer systems. Also, developers find advantages using existing chipsets peripheral components their embedded designs. embedded Write-Back Enhanced IntelDX4 processor binary compatible with Intel386and earlier Intel processors. Compared with Intel386 processor, provides faster execution many commonly-used instructions. also provides benefits integrated, 16-Kbyte, write-back cache code data. data operate burst mode which provides 106-Mbyte-persecond transfers cache-line fills instruction prefetches. Intel's technology incorporated embedded Write-Back Enhanced IntelDX4 processor. Utilizing Intel's System Management Mode (SMM) enables designers develop energyefficient systems. component packages available: 168-pin Grid Array (PGA) 208-lead Shrink Quad Flat Pack (SQFP) processor operates either three times external frequency. times external frequency processor operates MHz, (33-MHz CLK). three times external frequency processor operates (33-MHz CLK).
embedded Write-Back Enhanced IntelDX4 processor offers these features: 32-bit RISC-Technology Core embedded Write-Back Enhanced IntelDX4 processor performs complete arithmetic logical operations 16-, 32-bit data types using full-width eight general purpose registers. Single Cycle Execution Many instructions execute single clock cycle. Instruction Pipelining Overlapped instruction fetching, decoding, address translation execution. On-Chip Floating-Point Unit Intel486processors support 32-, 64-, 80-bit formats specified IEEE standard 754. unit binary compatible with 8087, Intel287TM, Intel387coprocessors, Intel OverDrive® processor. On-Chip Cache with Cache Consistency Support 16-Kbyte internal cache used both data instructions. configurable write-back write-through line-by-line basis. internal cache implements modified MESI protocol, which applicable uniprocessor systems. Cache hits provide zero wait-state access times data within cache. activity tracked detect alterations memory represented internal cache. internal cache invalidated flushed that external cache controller maintain cache consistency. External Cache Control Write-back flush controls external cache provided processor maintain cache consistency. On-Chip Memory Management Unit Address management memory space protection mechanisms maintain integrity memory multitasking virtual memory environment. Both memory segmentation paging supported. Burst Cycles Burst transfers allow double-word read from memory each clock cycle. This capability especially useful instruction prefetch filling internal cache. Data written from processor memory also burst transfers.
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Embedded Write-Back Enhanced IntelDX4Processor
Write Buffers processor contains four write buffers enhance performance consecutive writes memory. processor continue internal operations after write these buffers, without waiting write completed external bus. Backoff When another master needs control during processor initiated cycle, embedded Write-Back Enhanced IntelDX4 processor floats signals, then restarts cycle when becomes available again. Instruction Restart Programs continue execution following exception generated unsuccessful attempt access memory. This feature important supporting demand-paged virtual memory applications. Dynamic Sizing External controllers dynamically alter effective width data bus. widths bits used. Boundary Scan (JTAG) Boundary Scan provides in-circuit testing components printed circuit boards. Intel Boundary Scan implementation conforms with IEEE Standard Test Access Port Boundary Scan Architecture. Enhanced Mode definitions some signals have been changed support write-back cache mode. Intel's technology provides these features: Intel System Management Mode (SMM) unique Intel architecture operating mode provides dedicated special purpose interrupt address space that used implement intelligent power management other enhanced functions manner that completely transparent operating system applications software.
Restart instruction interrupted System Management Interrupt (SMI#) automatically restarted following execution instruction. Stop Clock embedded Write-Back Enhanced IntelDX4 processor stop clock control mechanism that provides low-power states: Stop Grant state (20-50 typical, depending input clock frequency) Stop Clock state (~600 typical, with input clock frequency MHz). Auto HALT Power Down After execution HALT instruction, embedded Write-Back Enhanced IntelDX4 processor issues normal Halt cycle clock input processor core automatically stopped, causing processor enter Auto HALT Power Down state (20-50 typical, depending input clock frequency). Auto Idle Power Down This function allows processor reduce core frequency frequency when both core idle. Auto Idle Power Down software transparent does affect processor performance. Auto Idle Power Down provides average power savings only applicable clock multiplied processors.
Family Members
Table shows embedded Write-Back Enhanced IntelDX4 processors briefly describes their characteristics.
Table Embedded Write-Back Enhanced IntelDX4Processor Family Product FC80486DX4WB75 FC80486DX4WB100 A80486DX4WB100 Supply Voltage
Maximum Processor Frequency
Maximum External Frequency
Package 208-Lead SQFP 208-Lead SQFP 168-Pin
Embedded Write-Back Enhanced IntelDX4Processor
THIS DOCUMENT
DESCRIPTIONS Assignments
complete documentation related embedded Write-Back Enhanced IntelDX4 processor, this document conjunction with following reference documents: Intel486Processor Family datasheet Order 242202 Intel486 Microprocessor Family Programmer's Reference Manual Order 240486 Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction Order 241618 information reference documents IntelDX4 processor applies embedded WriteBack Enhanced IntelDX4 processor. Some IntelDX4 processor information duplicated this document minimize dependence reference documents.
following figures tables show assignments each package type embedded Write-Back Enhanced IntelDX4 processor. Tables provided showing differences between embedded Write-Back Enhanced IntelDX4 processor other embedded Intel486 processor products. 208-Lead SQFP Quad Flat Pack Figure Package Diagram 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4Processor (pg. Table Pinout Differences 208-Lead SQFP Package (pg. Table Assignment 208-Lead SQFP Package (pg. Table Cross Reference 208-Lead SQFP Package (pg. 168-Pin Grid Array Figure Package Diagram 168-Pin Embedded Write-Back Enhanced IntelDX4Processor (pg. Table Pinout Differences 168-Pin Package (pg. Table Assignment 168-Pin Package (pg. Table Cross Reference 168-Pin Package (pg.
Embedded Write-Back Enhanced IntelDX4Processor
VCC5 PCHK# BRDY# BOFF# BS16# BS8# CLKMUL RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3# M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
LOCK# PLOCK# BLAST# ADS# RESERVED
208-Lead SQFP Embedded Write-Back Enhanced IntelDX4Processor
View
SRESET SMIACT# HITM# WB/WT# SMI# FERR# CACHE# IGNNE# STPCLK#
A3230-01
Figure Package Diagram 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4Processor
Embedded Write-Back Enhanced IntelDX4Processor
Table Pinout Differences 208-Lead SQFP Package Embedded Intel486SX Processor
VCC1 INC2
Embedded IntelDX2Processor
FERR# IGNNE#
Embedded Write-Back Enhanced IntelDX4Processor
VCC5 CLKMUL HITM# WB/WT# FERR# CACHE# IGNNE#
NOTES: This location VCC5 embedded IntelDX4 processor. compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this should connected trace, plane. INC. Internal Connect. These pins connected internal pad. However, signals defined location pins embedded IntelDX4 processor. system design accommodate these processors provided purpose each understood before used.
Embedded Write-Back Enhanced IntelDX4Processor
Description
Table Assignment 208-Lead SQFP Package (Sheet Pin#
Description
VCC5 PCHK# BRDY# BOFF# BS16# BS8# CLKMUL RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3#
Pin#
Description
SRESET SMIACT# HITM# WB/WT# SMI# FERR# CACHE# IGNNE# STPCLK#
Pin#
Pin#
Description
Pin#
Embedded Write-Back Enhanced IntelDX4Processor
Table Assignment 208-Lead SQFP Package (Sheet Description
M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
Pin#
Description
Pin#
Description
Pin#
Description
RESERVED ADS# BLAST# PLOCK# LOCK#
NOTE: Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors.
Embedded Write-Back Enhanced IntelDX4Processor
VCC5
Table Cross Reference 208-Lead SQFP Package (Sheet Address Data Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CACHE# CLKMUL D/C# EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR KEN# LOCK# M/IO#
Address Data
Embedded Write-Back Enhanced IntelDX4Processor
Table Cross Reference 208-Lead SQFP Package (Sheet Control PCHK# PLOCK# RDY# RESERVED RESET SMI# SMIACT# SRESET STPCLK# WB/WT# W/R# VCC5
Embedded Write-Back Enhanced IntelDX4Processor
VCC5
VOLDET
168-Pin Embedded Write-Back Enhanced IntelDX4Processor
SMI#
SRESET
Side View
RESERVED
HITM# CACHE# SMIACT#
WB/WT#
FERR#
IGNNE#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
BE2#
BE0#
D/C#
LOCK#
BREQ
INTR
RESET
BS8#
RDY#
BE1#
M/IO#
PLOCK# BLAST#
AHOLD EADS# BS16# BOFF#
BE3#
W/R#
PCHK# CLKMUL ADS#
A3231-01
Figure Package Diagram 168-Pin Embedded Write-Back Enhanced IntelDX4Processor
Embedded Write-Back Enhanced IntelDX4Processor
Table Pinout Differences 168-Pin Package Embedded IntelDX2Processor Embedded Write-Back Enhanced IntelDX4Processor HITM# CACHE# WB/WT# VCC5 CLKMUL VOLDET
Embedded Write-Back Enhanced IntelDX4Processor
Description HLDVCC
Table Assignment 168-Pin Package (Sheet Description
Description BOFF#
HOLD
KEN# RDY# BE3#
BREQ PLOCK# PCHK#
HITM# IGNNE# INTR AHOLD
STPCLK#
BRDY#
VCC5
SMI#
BE2# BE1#
CACHE# WB/WT# EADS#
BE0#
Description
Embedded Write-Back Enhanced IntelDX4Processor
Table Assignment 168-Pin Package (Sheet Description
Description BLAST# CLKMUL VOLDET
SRESET RESERVED SMIACT# FERR# FLUSH# RESET BS16# A20M# BS8#
D/C#
LOCK# M/IO# W/R#
ADS#
Embedded Write-Back Enhanced IntelDX4Processor
Vcc5
Table Cross Reference 168-Pin Package (Sheet Address Data Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLKMUL CACHE# D/C# EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR KEN# LOCK# M/IO#
Address Data
Embedded Write-Back Enhanced IntelDX4Processor
Table Cross Reference 168-Pin Package (Sheet Control PCHK# PLOCK# RDY# RESERVED RESET SMI# SMIACT# SRESET STPCLK# VOLDET WB/WT# W/R# Vcc5
Embedded Write-Back Enhanced IntelDX4Processor
Quick Reference
following brief description. detailed signal descriptions refer "Signal Description" section Intel486Processor Family datasheet. Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Symbol Type Name Function Clock provides fundamental timing internal operating frequency embedded Write-Back Enhanced IntelDX4 processor. external timing parameters specified with respect rising edge CLK. Address Lines A31-A2, together with byte enable signals, BE3#-BE0#, define physical area memory input/output space accessed. Address lines A31-A4 used drive addresses into embedded Write-Back Enhanced IntelDX4 processor perform cache line invalidation. Input signals must meet setup hold times t23. A31-A2 driven during address hold. Byte Enable signals indicate active bytes during read write cycles. During first cycle cache fill, external system should assume that byte enables active. BE3#-BE0# active driven during hold. BE3# applies D31-D24 BE2# applies D23-D16 BE1# applies D15-D8 BE0# applies D7-D0 Data Lines. D7-D0 define least significant byte data bus; D31-D24 define most significant byte data bus. These signals must meet setup hold times proper operation reads. These pins driven during second subsequent clocks write cycles. There Data Parity each byte data bus. Data parity generated write data cycles with same timing data driven embedded Write-Back Enhanced IntelDX4 processor. Even parity information must driven back into processor data parity pins with same timing read information ensure that correct parity check status indicated embedded Write-Back Enhanced IntelDX4 processor. signals read these pins affect program execution. Input signals must meet setup hold times t23. DP3-DP0 must connected through pull-up resistor systems that parity. DP3- active HIGH driven during second subsequent clocks write cycles. PCHK# Parity Status driven PCHK# clock after ready read operations. parity status data sampled previous clock. parity error indicated PCHK# being LOW. Parity status only checked enabled bytes indicated byte enable size signals. PCHK# valid only clock immediately after read data returned processor. other times PCHK# inactive (HIGH). PCHK# never floated.
ADDRESS A31-A4 A3-A2
BE3# BE2# BE1# BE0#
DATA D31-D0
DATA PARITY DP3-DP0
Symbol M/IO# D/C# W/R# Type CYCLE DEFINITION
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Name Function Memory/Input-Output, Data/Control Write/Read lines primary definition signals. These signals driven valid ADS# signal asserted. M/IO# D/C# W/R# Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) Read Write Code Read Reserved Memory Read Memory Write HALT/Special Cycle Cycle Name Shutdown HALT Stop Grant cycle LOCK# BE3# BE0# 1110 1011 1011 A4-A2
Lock indicates that current cycle locked. embedded Write-Back Enhanced IntelDX4 processor does allow hold when LOCK# asserted (address holds allowed). LOCK# goes active first clock first locked cycle goes inactive after last clock last locked cycle. last locked cycle ends when Ready returned. LOCK# active driven during hold. Locked read cycles transformed into cache fill cycles when KEN# returned active. Pseudo-Lock indicates that current transaction requires more than cycle complete. embedded Write-Back Enhanced IntelDX4 processor, examples such operations segment table descriptor reads bits) cache line fills (128 bits). Intel486 processors with on-chip FloatingPoint Unit, floating-point long reads writes bits) also require more than cycle complete. embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active until addresses last cycle transaction driven, regardless whether RDY# BRDY# have been returned. Normally PLOCK# BLAST# inverse each other. However, during first cycle 64-bit floating-point write (for Intel486 processors with on-chip Floating-Point Unit) both PLOCK# BLAST# asserted. PLOCK# function BS8#, BS16# KEN# inputs. PLOCK# should sampled only clock which Ready returned. PLOCK# active driven during hold.
PLOCK#
CONTROL ADS# Address Status output indicates that valid cycle definition address available cycle definition lines address bus. ADS# driven active same clock which addresses driven. ADS# active driven during hold.
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Symbol RDY# Type Name Function Non-burst Ready input indicates that current cycle complete. RDY# indicates that external system presented valid data data pins response read that external system accepted data from embedded Write-Back Enhanced IntelDX4 processor response write. RDY# ignored when idle first clock cycle. RDY# active during address hold. Data returned embedded WriteBack Enhanced IntelDX4 processor while AHOLD active. RDY# active provided with internal pull-up resistor. RDY# must satisfy setup hold times proper chip operation. BURST CONTROL BRDY# Burst Ready input performs same function during burst cycle that RDY# performs during non-burst cycle. BRDY# indicates that external system presented valid data response read that external system accepted data response write. BRDY# ignored when idle first clock cycle. BRDY# sampled second subsequent clocks burst cycle. Data presented data strobed into embedded Write-Back Enhanced IntelDX4 processor when BRDY# sampled active. RDY# returned simultaneously with BRDY#, BRDY# ignored burst cycle prematurely aborted. BRDY# active provided with small pull-up resistor. BRDY# must satisfy setup hold times t17. BLAST# Burst Last signal indicates that next time BRDY# returned, burst cycle complete. BLAST# active both burst non-burst cycles. BLAST# active driven during hold. Reset input forces embedded Write-Back Enhanced IntelDX4 processor begin execution known state. processor cannot begin executing instructions until least after VCC, have reached their proper specifications. RESET must remain active during this time ensure proper processor operation. However, warm resets, RESET should remain active least periods. RESET active HIGH. RESET asynchronous must meet setup hold times recognition specific clock. Maskable Interrupt indicates that external interrupt been generated. When internal interrupt flag EFLAGS, active interrupt processing initiated. embedded Write-Back Enhanced IntelDX4 processor generates locked interrupt acknowledge cycles response INTR going active. INTR must remain active until interrupt acknowledges have been performed ensure processor recognition interrupt. INTR active HIGH provided with internal pull-down resistor. INTR asynchronous, must meet setup hold times recognition specific clock.
INTERRUPTS RESET
INTR
Symbol Type
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Name Function Non-Maskable Interrupt request signal indicates that external non-maskable interrupt been generated. rising-edge sensitive must held least four periods before this rising edge. provided with internal pull-down resistor. asynchronous, must meet setup hold times recognition specific clock. Soft Reset duplicates functionality RESET except that SMBASE register retains previous value. soft resets, SRESET must remain active least periods. SRESET active HIGH. SRESET asynchronous must meet setup hold times recognition specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# falling-edge triggered signal which forces embedded Write-Back Enhanced IntelDX4 processor into completion current instruction. SMI# recognized instruction boundary each iteration repeat string instructions. SMI# does break LOCKed cycles cannot interrupt currently executing SMM. embedded Write-Back Enhanced IntelDX4 processor latches falling edge pending SMI# signal while executing existing SMI#. nested SMI# recognized until after execution Resume (RSM) instruction. System Management Interrupt Active, active output, indicates that embedded Write-Back Enhanced IntelDX4 processor operating SMM. asserted when processor begins execute SMI# state save sequence remains active until processor executes last state restore cycle SMRAM. Stop Clock Request input signal indicates request made turn change input frequency. When embedded Write-Back Enhanced IntelDX4 processor recognizes STPCLK#, stops execution next instruction boundary (unless superseded higher priority interrupt), empties internal pipelines write buffers, generates Stop Grant cycle. STPCLK# active LOW. STPCLK# asynchronous signal, must remain active until embedded Write-Back Enhanced IntelDX4 processor issues Stop Grant cycle. STPCLK# de-asserted time after processor issued Stop Grant cycle. Request signal indicates that embedded Write-Back Enhanced IntelDX4 processor internally generated request. BREQ generated whether processor driving bus. BREQ active HIGH never floated. Hold Request allows another master complete control embedded Write-Back Enhanced IntelDX4 processor bus. response HOLD going active, processor floats most output input/output pins. HLDA asserted after completing current cycle, burst cycle sequence locked cycles. embedded Write-Back Enhanced IntelDX4 processor remains this state until HOLD de-asserted. HOLD active HIGH provided with internal pull-down resistor. HOLD must satisfy setup hold times proper operation.
SRESET
SMI#
SMIACT#
STPCLK#
ARBITRATION BREQ
HOLD
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Symbol HLDA Type Name Function Hold Acknowledge goes active response hold request presented HOLD pin. HLDA indicates that embedded Write-Back Enhanced IntelDX4 processor given another local master. HLDA driven active same clock that processor floats bus. HLDA driven inactive when leaving hold. HLDA active HIGH remains driven during hold. Backoff input forces embedded Write-Back Enhanced IntelDX4 processor float next clock. processor floats pins normally floated during hold HLDA asserted response BOFF#. BOFF# higher priority than RDY# BRDY#; both returned same clock, BOFF# takes effect. embedded Write-Back Enhanced IntelDX4 processor remains hold until BOFF# negated. cycle progress when BOFF# asserted cycle restarted. BOFF# active must meet setup hold times proper operation. Address Hold request allows another master access embedded WriteBack Enhanced IntelDX4 processor's address cache invalidation cycle. processor stops driving address clock following AHOLD going active. Only address floated during address hold, remainder remains active. AHOLD active HIGH provided with small internal pull-down resistor. proper operation, AHOLD must meet setup hold times t19. External Address This signal indicates that valid external address been driven onto embedded Write-Back Enhanced IntelDX4 processor address pins. This address used perform internal cache invalidation cycle. EADS# active provided with internal pull-up resistor. EADS# must satisfy setup hold times proper operation. Cache Enable used determine whether current cycle cacheable. When embedded Write-Back Enhanced IntelDX4 processor generates cycle that cached KEN# active clock before RDY# BRDY# during first transfer cycle, cycle becomes cache line fill cycle. Returning KEN# active clock before RDY# during last read cache line fill causes line placed on-chip cache. KEN# active provided with small internal pull-up resistor. KEN# must satisfy setup hold times proper operation. Cache Flush input forces embedded Write-Back Enhanced IntelDX4 processor flush entire internal cache. FLUSH# active need only asserted clock. FLUSH# asynchronous setup hold times must recognition specific clock.
BOFF#
CACHE INVALIDATION AHOLD
EADS#
CACHE CONTROL KEN#
FLUSH#
Symbol Type PAGE CACHEABILITY
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Name Function Page Write-Through Page Cache Disable pins reflect state page attribute bits, PCD, page table entry, page directory entry control register (CR3) when paging enabled. When paging disabled, embedded Write-Back Enhanced IntelDX4 processor ignores bits assumes they zero purpose caching driving pins. have same timing cycle definition pins (M/IO#, D/C#, W/R#). active HIGH driven during hold. masked cache disable (CD) Control Register Size Size pins (bus sizing pins) cause embedded WriteBack Enhanced IntelDX4 processor multiple cycles complete request from devices that cannot provide accept bits data single cycle. sizing pins sampled every clock. processor uses state these pins clock before Ready determine size. These signals active provided with internal pull-up resistors. These inputs must satisfy setup hold times proper operation. Address Mask pin, when asserted, causes embedded Write-Back Enhanced IntelDX4 processor mask physical address (A20) before performing lookup internal cache driving memory cycle bus. A20M# emulates address wraparound Mbyte, which occurs 8086 processor. A20M# active should asserted only when embedded Write-Back Enhanced IntelDX4 processor real mode. This asynchronous should meet setup hold times recognition specific clock. proper operation, A20M# should sampled HIGH falling edge RESET. Test Clock, input embedded Write-Back Enhanced IntelDX4 processor, provides clocking function required JTAG Boundary scan feature. used clock state information (via TMS) data (via TDI) into component rising edge TCK. Data clocked component (via TDO) falling edge TCK. provided with internal pull-up resistor. Test Data Input serial input used shift JTAG instructions data into processor. sampled rising edge TCK, during SHIFT-IR SHIFT-DR Test Access Port (TAP) controller states. During other controller states, "don't care." provided with internal pull-up resistor. Test Data Output serial output used shift JTAG instructions data component. driven falling edge during SHIFT-IR SHIFT-DR controller states. other times driven high impedance state. Test Mode Select decoded JTAG select test logic operation. sampled rising edge TCK. guarantee deterministic behavior controller, provided with internal pull-up resistor.
SIZE CONTROL BS16# BS8#
ADDRESS MASK A20M#
TEST ACCESS PORT
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Symbol FERR# Type Name Function Floating Point Error driven active when floating point error occurs. FERR# similar ERROR# Intel387Math CoProcessor. FERR# included compatibility with systems using type floating point error reporting. FERR# will active errors masked register. FERR# active LOW, floated during hold. When Ignore Numeric Error asserted processor will ignore numeric error continue executing non-control floating point instructions, FERR# will still activated processor. When IGNNE# de-asserted processor will freeze non-control floating point instruction, previous floating point instruction caused error. IGNNE# effect when control register set. IGNNE# active provided with small internal pull-up resistor. IGNNE# asynchronous setup hold times must ensure recognition specific clock. CACHE# output indicates internal cacheability read cycles burst writeback write cycles. CACHE# asserted cacheable reads, cacheable code fetches write-backs. driven inactive non-cacheable reads, cycles, special cycles, write-through cycles. Cache FLUSH# existing that operates differently processor configured Enhanced mode (write-back). FLUSH# causes processor write back modified lines flush (invalidate) cache. FLUSH# asynchronous, must meet setup hold times recognition specific clock. Hit/Miss Modified Line cache coherency protocol that driven only Enhanced mode. When snoop cycle run, HITM# indicates that processor contains snooped line that line been modified. Assertion HITM# implies that line will written back entirety, unless processor already process doing replacement write-back same line. Invalidation Request cache coherency protocol that used only Enhanced mode. sampled processor EADS#-driven snoop cycles. necessary assert this effect processor invalidate cycle write-through-only lines. also invalidates write-back lines. However, snooped line modified, line will written back then invalidated. must satisfy setup hold times proper operation. Enhanced mode, Pseudo-Lock Output always driven inactive. this mode, 64-bit data read (caused operand access segment descriptor read) treated multiple cycle read request, which burst non-burst access based whether BRDY# RDY# returned system. Because only write-back cycles (caused snoop write-back replacement write-back) write burstable, 64-bit write will driven nonburst cycles. BLAST# asserted during both writes.
NUMERIC ERROR REPORTING
IGNNE#
WRITE-BACK ENHANCED MODE CACHE#
FLUSH#
HITM#
PLOCK#
Symbol SRESET Type
Embedded Write-Back Enhanced IntelDX4Processor
Table Embedded Write-Back Enhanced IntelDX4Processor Descriptions (Sheet Name Function embedded Write-Back Enhanced IntelDX4 processor, Soft RESET operates similar other Intel486 processors. SRESET, internal SMRAM base register retains previous value, does flush, write-back disable internal cache. Because SRESET treated interrupt, possible have cycle while SRESET asserted. SRESET serviced only instruction boundary. SRESET asynchronous must meet setup hold times recognition specific clock. Write-Back/Write-Through enables Enhanced mode (write-back cache). also defines cached line write-through write-back. cache configuration, WB/WT# must valid during RESET active least clocks before clocks after RESET de-asserted. define write-back write-through configuration line, WB/WT# sampled same clock first RDY# BRDY# returned during line fill (allocation) cycle. Clock Multiplier input, defined during device RESET, defines ratio internal core frequency external frequency. sampled low, core frequency operates twice external frequency (speed doubled mode). driven high left floating, speed triple mode selected. CLKMUL internal pull-up speed left floating designs that select speed tripled clock mode. reference voltage input reference voltage 5V-tolerant buffers. This signal should connected with logic. inputs from logic, this should connected 3.3V. Voltage Detect signal allows external system logic distinguish between Intel486 processor 3.3V IntelDX4 processor. This signal active 3.3V IntelDX4 processor. This available only version embedded Write-Back Enhanced IntelDX4 processor. Reserved reserved future use. This MUST connected external pull-up resistor circuit. recommended resistor value kOhms. pull-up resistor must connected only RESERVED pin. share this resistor with other pins requiring pull-ups.
WB/WT#
CLKMUL, VCC5, VOLDET CLKMUL
VCC5
VOLDET
RESERVED PINS RESERVED
Embedded Write-Back Enhanced IntelDX4Processor
Output Signal During Stop Grant Stop Clock States
Previous State1 HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State
Table Output Pins Name
BREQ HLDA BE3#-BE0# PWT, W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# FERR# A3-A2 SMIACT# CACHE# HITM# VOLDET
Active Level
HIGH HIGH HIGH HIGH/LOW HIGH
Floated During Address Hold
Floated During Hold
Previous State Previous State HIGH2 HIGH2
NOTES: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating. case snoop cycles (via EADS#) during Stop Grant state, CACHE# HITM# active depending snoop internal cache.
Table Input/Output Pins Output Signal Name D31-D0 DP3-DP0 A31-A4 Active Level HIGH HIGH HIGH Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States Floated Floated Previous State
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Test Pins Name Input Output Input Input Output Input Sampled/ Driven Rising Edge Failing Edge Rising Edge
Name RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR IGNNE# RESERVED SMI# STPCLK# WB/WT# CLKMUL
Embedded Write-Back Enhanced IntelDX4Processor
Table Input Pins Active Level Synchronous/ Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Down Pull-Up1 Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Internal Pull-Up/ Pull-Down
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH/LOW HIGH HIGH HIGH HIGH
NOTE: Even though STPCLK# CLKMUL have internal pull-up resistors, they cannot left floating. external 10-K pullup resistor needed STPCLK# unused. CLKMUL must driven valid logic level. tied HIGH, external 10-K pull-up resistor recommended.
Embedded Write-Back Enhanced IntelDX4Processor
ARCHITECTURAL FUNCTIONAL OVERVIEW
embedded Write-Back Enhanced IntelDX4 processor architecture essentially same IntelDX4 processor. Refer Intel486Processor Family datasheet (242202) description IntelDX4 processor. With some minor exceptions, following datasheet sections apply embedded Write-Back Enhanced IntelDX4 processor: Architectural Overview Real Mode Architecture Protected Mode Architecture On-Chip Cache System Management Mode (SMM) Architectures Hardware Interface Operation Testability Debugging Support Instruction Summary Differences Between Intel486 Processors Intel386Processors Exceptions these sections datasheet are: References Upgrade Power Down Mode apply. embedded Write-Back Enhanced IntelDX4 processor does have signal does support Intel OverDrive® processor.
embedded Write-Back Enhanced IntelDX4 processor reserved possible future use. This pin, input signal, called RESERVED must connected 10-K pull-up resistor. pull-up resistor must connected only RESERVED pin. share this resistor with other pins requiring pull-ups.
CPUID Instruction
embedded Write-Back Enhanced IntelDX4 processor supports CPUID instruction (see Table 13). Because Intel processors support CPUID instruction, simple test determine instruction supported. test involves processor's Flag, which EFLAGS register. software change value this flag, CPUID instruction available. actual state Flag irrelevant provides significance hardware. This cleared (reset zero) upon device reset (RESET SRESET) compatibility with Intel486 processor designs that support CPUID instruction. CPUID-instruction details provided here embedded Write-Back Enhanced IntelDX4 processor. Refer Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction (Order 241618) description that covers aspects CPUID instruction pertains other Intel processors. 4.1.1 Operation CPUID Instruction
CPUID instruction requires software developer pass input parameter processor register. processor response returned registers EAX, EBX, EDX, ECX.
Table CPUID Instruction Description CODE Instruction CPUID Processor Core Clocks Parameter passed
(Input Value)
Description Vendor (Intel) String Processor Identification Undefined Use)
High Value Vendor String (ASCII Characters)
Embedded Write-Back Enhanced IntelDX4Processor
Vendor String When parameter passed (zero), register values returned upon instruction execution shown following table. 31-24 (75) (49) (6C) 23-16 (6E) (65) (65) 15-8 (65) (6E) (74) (47) (69) (6E)
values EBX, indicate Intel processor. When taken proper order, they decode string "GenuineIntel." state WB/WT# input sampled processor falling edge RESET signal. WB/WT# LOW, processor configured operate Write-Through/Standard mode. HIGH, configured operate Write-Back/Enhanced mode. value "Model" field processor signature register depends mode which processor configured. Processor Identification When parameter passed (one), register values returned upon instruction execution are:
31-14 Processor Signature Write-Through/Standard mode Processor Signature WriteBack/Enhanced mode Use) Intel Reserved 13,12 Processor Type 11-8 0100 Family 1000 Model XXXX Stepping
Use) Intel Reserved
Processor Type
0100 Family
1001 Model
XXXX Stepping
(Intel releases information about stepping numbers needed) 31-0 Intel Reserved Use) Intel Reserved Intel Reserved 31-2 Feature Flags
Embedded Write-Back Enhanced IntelDX4Processor
11-8 0100 Family 1000 Model XXXX Stepping
Identification After Reset
31-14 13,12 Processor Type
Processor Identification Upon reset, register contains processor signature:
Processor Signature Write-Through/Standard mode Processor Signature WriteBack/Enhanced mode Use) Intel Reserved
Use) Intel Reserved
Processor Type
0100 Family
1001 Model
XXXX Stepping
(Intel releases information about stepping numbers needed)
4.3.1
Boundary Scan (JTAG)
Device Identification
Tables show 32-bit code embedded Write-Back Enhanced IntelDX4 processor. This code loaded into Device Identification Register. Table Boundary Scan Component Identification Code (Write-Through/Standard Mode)
Version 1=3.3 Part Number Model 01000 embedded WriteBack Enhanced IntelDX4 processor 16-12 01000 009H Intel
Intel Architecture Type
26-21 000001
Family 0100 Intel486 Family
31-28 XXXX
20-17 0100
11-1 00000001001
(Intel releases information about version numbers needed) Boundary Scan Component Identification Code x828 8013 (Hex)
Table Boundary Scan Component Identification Code (Write-Back/Enhanced Mode)
Version 1=3.3 Intel Architecture Type Part Number Family 0100 Intel486 Family Model 01001 embedded WriteBack Enhanced IntelDX4 processor 16-12 01001 009H Intel
31-28 XXXX
26-21 000001
20-17 0100
11-1 00000001001
(Intel releases information about version numbers needed)
Boundary Scan Component Identification Code x828 9013 (Hex)
4.3.2
Embedded Write-Back Enhanced IntelDX4Processor
Boundary Scan Register Bits Order
WRCTL controls D31-D0 DP3-DP0 ABUSCTL controls A31-A2 BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, PCD, CACHE# MISCCTL controls PCHK#, HLDA, BREQ, HITM# following order embedded WriteBack Enhanced IntelDX4 processor boundary scan register:
boundary scan register contains cell each well cells control bidirectional three-state pins. There "Reserved" bits which correspond no-connect (N/C) signals embedded Write-Back Enhanced IntelDX4 processor. Control registers WRCTL, ABUSCTL, BUSCTL, MISCCTL used select direction bidirectional three-state output signal pins. these cells designates that associated bits floated pins three-state, selected input they bidirectional.
RESERVED, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, DP1, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, IGNNE#, INV, CACHE#, FERR#, SMI#, WB/WT#, HITM#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, AHOLD, HOLD, KEN#, RDY#, CLKMUL, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
Embedded Write-Back Enhanced IntelDX4Processor
ELECTRICAL SPECIFICATIONS Maximum Ratings
Specifications
Table stress rating only. Extended exposure Maximum Ratings affect device reliability. Furthermore, although embedded Write-Back Enhanced IntelDX4 processor contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields. Functional operating conditions given Section 5.2, Specifications Section 5.3, Specifications. Table Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Voltage with Respect Ground Supply Voltage with Respect Reference Voltage VCC5 with Respect Transient Voltage Input +110 +150 -0.5 VCC5 -0.5 +4.6 -0.5 +6.5 lesser VCC5
following tables show operating supply voltages, specifications, component power consumption embedded Write-Back Enhanced IntelDX4 processor. Table Operating Supply Voltages Product FC80486DX4WB75 FC80486DX4WB100 A80486DX4WB100
Current Sink VCC5
Embedded Write-Back Enhanced IntelDX4Processor
Table Specifications Functional Operating Range: VCC5 0.25 (Note TCASE=0 Symbol
VIHC
Parameter
Input Voltage Input HIGH Voltage Input HIGH Voltage Output Voltage (Address, Data, BEn) (Definition, Control)
Min.
-0.3 VCC5 -0.6
Typ.
Max.
+0.8 VCC5 +0.3 VCC5 +0.3 0.45 0.45 0.40 0.20
Unit
Notes
Note
ICC5 COUT CCLK
Output HIGH Voltage -2.0 VCC5 Leakage Current Input Leakage Current Input Leakage Current SRESET Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance -400 Note Note Note Note Note Note Note Note
NOTES: VCC5 should connected V-only systems. inputs except CLK. This parameter inputs without pull-up pull-down resistors VCC. This parameter VCC5 2.25 Typical value 100% tested. This parameter inputs with pull-down resistors 2.4V. This parameter inputs with pull-up resistors 0.4V. FC=1 MHz. 100% tested.
Embedded Write-Back Enhanced IntelDX4Processor
Table Values Functional Operating Range: ±0.3 VCC5 0.25 (Note TCASE +85°C Parameter Active (Power Supply) Active (Thermal Design) Stop Grant Stop Clock Operating Frequency 1075 Typ. Maximum 1100 1450 1300 Notes Note Notes Note Note
NOTES: VCC5 should connected V-only systems. This parameter proper power supply selection. measured using worst case instruction 3.6V. maximum current column thermal design power dissipation. measured using worst case instruction 3.3V. typical current column typical operating current system. This value measured system using typical device 3.3V, running Microsoft Windows idle condition. This typical value dependent upon specific system configuration. Typical values 100% tested. Stop Grant specification refers value once embedded Write-Back Enhanced IntelDX4 processor enters Stop Grant Auto HALT Power Down state. Stop Clock specification refers value once embedded Write-Back Enhanced IntelDX4 processor enters Stop Clock state. levels must equal respectively, order meet Stop Clock specifications.
Specifications
Embedded Write-Back Enhanced IntelDX4Processor
specifications embedded Write-Back Enhanced IntelDX4 processor given this section. Table Characteristics VCC5 0.25 (Note TCASE +85°C; 50pF, unless otherwise specified. (Sheet Product Symbol Parameter Frequency Period Period Stability WB75 ±250 WB100 ±250 Unit Adjacent clocks Note High Time Time Fall Time Rise Time A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, FERR#, CACHE#, HITM#, BREQ, HLDA Valid Delay A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, CACHE# Float Delay PCHK# Valid Delay BLAST#, PLOCK#, SMIACT# Valid Delay BLAST#, PLOCK# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS#, Setup Time EADS#, Hold Time KEN#, BS16#, BS8#, WB/WT# Setup Time KEN#, BS16#, BS8#, WB/WT# Hold Time RDY#, BRDY# Setup Time 0.8V 0.8V 0.8V Figure Notes Note
Note
Note Note
Embedded Write-Back Enhanced IntelDX4Processor
Table Characteristics VCC5 0.25 (Note TCASE +85°C; 50pF, unless otherwise specified. (Sheet Product Symbol t18a Parameter RDY#, BRDY# Hold Time HOLD, AHOLD Setup Time BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time WB75 WB100 Unit Figure Note Notes
Note
NOTES: VCC5 should connected V-only systems. 0-MHz operation guaranteed when STPCLK# Stop Grant cycle protocol used. 100% tested, guaranteed design characterization. reset pulse width cycles required warm resets (RESET SRESET). Power-up resets (cold resets) require RESET asserted least after stable.
Embedded Write-Back Enhanced IntelDX4Processor
Table Specifications Test Access Port ±0.3 VCC5 ±0.25 (Note TCASE +85°C; Symbol Frequency Period High Time Time Rise Time Fall Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Outputs (except TDO) Valid Delay Outputs (except TDO) Float Delay Inputs (except TDI, TMS, TCK) Setup Time Inputs (except TDI, TMS, TCK) Hold Time Parameter Unit 2.0V 0.8V Note Note Note Note Note Note Note Note Note Note Figure Notes Note
NOTES: VCC5 should connected ±0.3 V-only systems. inputs outputs level. period period. Rise/Fall times measured between 0.8V 2.0V. Rise/Fall times relaxed 10-ns increase period. Parameters measured from TCK.
Embedded Write-Back Enhanced IntelDX4Processor
input setup times input hold times, output float, valid hold times Figure Waveform
INV, EADS#
BS8#, BS16#, KEN#, WB/WT#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET, IGNNE# A31-A4 (READ)
Figure Input Setup Hold Timing
Embedded Write-Back Enhanced IntelDX4Processor
RDY#, BRDY#
D31-D0, DP3-DP0
Figure Input Setup Hold Timing
RDY#, BRDY#
D31-D0 DP3-DP0
VALID
PCHK#
VALID
Figure PCHK# Valid Delay Timing
Embedded Write-Back Enhanced IntelDX4Processor
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, FERR#, CACHE#, HITM#
VALID
VALID
D31-D0, DP3-DP0
VALID
VALID
SMIACT#, BLAST#, PLOCK#
VALID
VALID
Figure Output Valid Delay Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, CACHE#
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure Maximum Float Delay Timing
Embedded Write-Back Enhanced IntelDX4Processor
Figure Waveform
OUTPUT INPUT VALID VALID VALID VALID VALID
Figure Test Signal Timing Diagram
Embedded Write-Back Enhanced IntelDX4Processor
Capacitive Derating Curves
These graphs capacitive derating curves embedded Write-Back Enhanced IntelDX4 processor.
nom+7 nom+6 nom+5
Delay (ns)
nom+4 nom+3 nom+2 nom+1 nom-1 nom-2
Note:
Capacitive Load (pF)
This graph will linear outside capacitive range shown. nominal value from Characteristics table.
A3238-01
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition
nom+5 nom+4
Delay (ns)
nom+3 nom+2 nom+1 nom-1 nom-2
Capacitive Load (pF) Note: This graph will linear outside capacitive range shown. nominal value from Characteristics table.
A3237-01
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition
MECHANICAL
Embedded Write-Back Enhanced IntelDX4Processor
This section describes packaging dimensions thermal specifications embedded Write-Back Enhanced IntelDX4 processor.
Package Dimensions
30.6 0.25 28.0 0.10
1.14 (ref)
25.50 (ref)
21.20 0.10
0.13 0.12-0.08
0.60 0.10 1.30
0.50
View
Metal Heat Spreader
3.37 0.08 3.70
0.13 0.25
NOTE: Length measurements same width measurements 1.76 Tolerance Window Lead Skew from Theoretical True Position 0.10
Units:
A3260-01
Figure 208-Lead SQFP Package Dimensions
Embedded Write-Back Enhanced IntelDX4Processor
Figure Principal Dimensions Data 168-Pin Grid Array Package Table 168-Pin Ceramic Package Dimensions Symbol 1.52 Millimeters 3.56 0.64 1.14 0.43 44.07 40.51 2.29 2.54 2.54 0.060 4.57 1.14 1.40 0.51 44.83 40.77 2.79 3.30 SOLID SOLID Notes 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 0.100 Inches 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID SOLID Notes
Letter Symbol
Embedded Write-Back Enhanced IntelDX4Processor
Table Ceramic Package Dimension Symbols Description Dimensions Distance from seating plane highest point body Distance between seating plane base plane (lid) Distance from base plane highest point body Distance from seating plane bottom body Diameter terminal lead Largest overall package dimension length body length dimension, outer lead center outer lead center Linear spacing between true lead position centerlines Distance from seating plane lead Other body dimension, outer lead center edge body
NOTES: Controlling dimension: millimeter. Dimension "e1" ("e") non-cumulative. Seating plane (standoff) defined P.C. board hole size: 0.0415-0.0430 inch. Dimensions "B", "B1" nominal. Details identifier optional.
Package Thermal Specifications
embedded Write-Back Enhanced IntelDX4 processor specified operation when case temperature (TC) within range 85°C. measured environment determine whether processor within specified operating range. ambient temperature (TA) calculated from from following equations:
Where equals Junction, Ambient Case Temperature respectively. equals Junction-to-Case Junction-to-Ambient thermal Resistance, respectively. defined Maximum Power Consumption. Values given following tables each product maximum operating frequencies. Maximum shown each product operating maximum processor frequency (three times frequency). Refer Intel486Processor Family datasheet (242202) description methods used measure these characteristics.
Embedded Write-Back Enhanced IntelDX4Processor
(2.03) 13.0 (3.04) 11.5 (4.06) 10.0 1000 (5.07) 4.25
Table Thermal Resistance, (°C/W) Airflow ft/min. (m/sec) Package 168-Pin 168-Pin 208-Lead SQFP 208-Lead SQFP Heat Sink 17.5 13.5 12.5 10.5 (1.01) 15.0 10.0
Table Thermal Resistance, (°C/W) Package 168-Pin 168-Pin 208-Lead SQFP 208-Lead SQFP Heat Sink
Table Maximum Tambient, (°C) Airflow ft/min. (m/sec) Package 168-Pin 168-Pin 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP Heat Sink Freq. (MHz) 18.5 35.5 36.5 43.5 (1.01) 29.0 57.0 46.0 60.5 (2.03) 37.5 65.5 50.0 67.0 (3.04) 44.0 70.0 52.5 71.0

Operation Integrated Floating-Point Unit Speed-Multiplying Technology

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