Integrated Floating-Point Unit Speed-Multiplying Technology 32-Bit RIS

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EMBEDDED IntelDX2PROCESSOR
Integrated Floating-Point Unit Speed-Multiplying Technology 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Technology Data Parity Generation Checking Boundary Scan (JTAG) 3.3-Volt Processor, MHz,
208-Lead Shrink Quad Flat Pack (SQFP) 5-Volt Processor, MHz, Burst Cycles 168-Pin Grid Array (PGA) Dynamic Sizing 16-bit Data Binary Compatible with Large Software Devices Base
64-Bit Interunit Transfer
32-Bit Data 32-Bit Data Linear Address Core Clock
Clock Multiplier
Barrel Shifter Register File
Base/ Index
Segmentation Unit Descriptor Registers Limit Attribute
Interface
Paging Unit
Cache Unit
Address Drivers Write Buffers Data Transceivers Control
A31-A2 BE3#- BE0#
Physical Address Translation Lookaside Buffer
Kbyte Cache
D31-D0
Displacement
Prefetcher Request Sequencer 32-Byte Code Queue 2x16 Bytes Burst Control Size Control Cache Control
MicroInstruction
ADS# W/R# D/C# M/IO# RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR SMI# SMIACT# FERR# IGNNE# STPCLK#
BRDY# BLAST#
Floating Point Unit
Control Protection Test Unit
Code Stream Instruction Decode Decoded Instruction Path
BS16# BS8#
Floating Point Register File
KEN# FLUSH# AHOLD EADS#
Control
Parity Generation Control Boundary Scan Control
DP3-DP0 PCHK#
A3223-01
Figure Embedded IntelDX2Processor Block Diagram
Information this document provided connection with Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes these specifications time, without notice. Microprocessor products have minor variations this specification known errata. INTEL CORPORATION, 1995 October 1995 Order Number: 272770-001
CONTENTS
EMBEDDED IntelDX2PROCESSOR
INTRODUCTION Features Family Members THIS DOCUMENT DESCRIPTIONS Assignments Quick Reference ARCHITECTURAL FUNCTIONAL OVERVIEW CPUID Instruction 4.1.1 Operation CPUID Instruction Identification After Reset Boundary Scan (JTAG) 4.3.1 Device Identification 4.3.2 Boundary Scan Register Bits Order ELECTRICAL SPECIFICATIONS Maximum Ratings Specifications Specifications Capacitive Derating Curves MECHANICAL DATA Package Dimensions Package Thermal Specifications FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Embedded IntelDX2Processor Block Diagram Package Diagram 208-Lead SQFP Embedded IntelDX2Processor Package Diagram 168-Pin Embedded IntelDX2Processor Waveform Input Setup Hold Timing Input Setup Hold Timing PCHK# Valid Delay Timing Output Valid Delay Timing Maximum Float Delay Timing Waveform Test Signal Timing Diagram Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor
Figure Figure Figure Figure TABLES Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
CONTENTS
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor 208-Lead SQFP Package Dimensions Principal Dimensions Data 168-Pin Grid Array Package
Embedded IntelDX2Processor Family Pinout Differences 208-Lead SQFP Package Assignment 208-Lead SQFP Package Cross Reference 208-Lead SQFP Package Pinout Differences 168-Pin Package Assignment 168-Pin Package Cross Reference 168-Pin Package Embedded IntelDX2Processor Descriptions Output Pins Input/Output Pins Test Pins Input Pins CPUID Instruction Description Boundary Scan Component Identification Code (3.3 Volt Processor) Boundary Scan Component Identification Code Volt Processor) Absolute Maximum Ratings Operating Supply Voltages Specifications Values Specifications Values Characteristics Specifications Test Access Port 168-Pin Ceramic Package Dimensions Ceramic Package Dimension Symbols Thermal Resistance, (°C/W) Thermal Resistance, (°C/W) Maximum Tambient, (°C)
INTRODUCTION
embedded IntelDX2processor provides high performance 32-bit, embedded applications. Designed applications that need floating-point unit, processor ideal embedded designs running DOS*, Microsoft* Windows*, OS/2*, UNIX* applications written Intel architecture. Projects completed quickly utilizing wide range software tools, utilities, assemblers compilers that available desktop computer systems. Also, developers find advantages using existing chipsets peripheral components their embedded designs. embedded IntelDX2 processor binary compatible with Intel386and earlier Intel processors. Compared with Intel386 processor, provides faster execution many commonly-used instructions. also provides benefits integrated, 8Kbyte, write-through cache code data. data operate burst mode which provides 106-Mbyte-per-second transfers cache-line fills instruction prefetches. Intel's technology incorporated embedded IntelDX2 processor. Utilizing Intel's System Management Mode (SMM), enables designers develop energy-efficient systems. component packages available. 168-pin Grid Array (PGA) available 5-Volt designs 208-lead Shrink Quad Flat Pack (SQFP) available 3.3-Volt designs. processor operates twice external-bus frequency. processor operates (33-MHz CLK). processor operates (25-MHz CLK).
Embedded IntelDX2Processor
Single Cycle Execution Many instructions execute single clock cycle. Instruction Pipelining Overlapped instruction fetching, decoding, address translation execution. On-Chip Floating-Point Unit Intel486processors support 32-, 64-, 80-bit formats specified IEEE standard 754. unit binary compatible with 8087, Intel287TM, Intel387coprocessors, Intel OverDrive® processor. On-Chip Cache with Cache Consistency Support 8-Kbyte, write-through, internal cache used both data instructions. Cache hits provide zero wait-state access times data within cache. activity tracked detect alterations memory represented internal cache. internal cache invalidated flushed that external cache controller maintain cache consistency. External Cache Control Write-back flush controls external cache provided processor maintain cache consistency. On-Chip Memory Management Unit Address management memory space protection mechanisms maintain integrity memory multitasking virtual memory environment. Both memory segmentation paging supported. Burst Cycles Burst transfers allow double-word read from memory each clock cycle. This capability especially useful instruction prefetch filling internal cache. Write Buffers processor contains four write buffers enhance performance consecutive writes memory. processor continue internal operations after write these buffers, without waiting write completed external bus. Backoff When another master needs control during processor initiated cycle, embedded IntelDX2 processor floats signals, then restarts cycle when becomes available again. Instruction Restart Programs continue execution following exception generated unsuccessful attempt access memory. This feature important supporting demand-paged virtual memory applications.
Features
embedded IntelDX2 processor offers these features: 32-bit RISC-Technology Core embedded IntelDX2 processor performs complete arithmetic logical operations 16-, 32-bit data types using full-width eight general purpose registers.
Other brands names property their respective owners.
Embedded IntelDX2Processor
typical, depending input clock frequency) Stop Clock state (~100-200 typical, with input clock frequency MHz). Auto HALT Power Down After execution HALT instruction, embedded IntelDX2 processor issues normal Halt cycle clock input processor core automatically stopped, causing processor enter Auto HALT Power Down state (20-45 typical, depending input clock frequency). Auto Idle Power Down This function allows processor reduce core frequency frequency when both core idle. Auto Idle Power Down software transparent does affect processor performance. Auto Idle Power Down provides average power savings only applicable clock multiplied processors.
Dynamic Sizing External controllers dynamically alter effective width data bus. widths bits used. Boundary Scan (JTAG) Boundary Scan provides in-circuit testing components printed circuit boards. Intel Boundary Scan implementation conforms with IEEE Standard Test Access Port Boundary Scan Architecture. Intel's technology provides these features: Intel System Management Mode (SMM) unique Intel architecture operating mode provides dedicated special purpose interrupt address space that used implement intelligent power management other enhanced functions manner that completely transparent operating system applications software. Restart instruction interrupted System Management Interrupt (SMI#) automatically restarted following execution instruction. Stop Clock embedded IntelDX2 processor stop clock control mechanism that provides low-power states: Stop Grant state (20-45
Family Members
Table shows embedded IntelDX2 processors briefly describes their characteristics.
Table Embedded IntelDX2Processor Family Product SB80486DX2SC50 A80486DX2SA66 Supply Voltage
Maximum Processor Frequency
Maximum External Frequency
Package 208-Lead SQFP 168-Pin
THIS DOCUMENT
complete documentation related embedded IntelDX2 processor, this document conjunction with following reference documents: Intel486Processor Family datasheet Order 242202 Intel486 Microprocessor Family Programmer's Reference Manual Order 240486 Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction Order 241618 information reference documents IntelDX2 processor applies embedded IntelDX2 processor. Some IntelDX2 processor information duplicated this document minimize dependence reference documents.
Embedded IntelDX2Processor
DESCRIPTIONS Assignments
following figures tables show assignments each package type embedded IntelDX2 processor. Tables provided showing differences between embedded IntelDX2 processor other embedded Intel486 processor products. 208-Lead SQFP Quad Flat Pack Figure Package Diagram 208-Lead SQFP Embedded IntelDX2Processor (pg. Table Pinout Differences 208-Lead SQFP Package (pg. Table Assignment 208-Lead SQFP Package (pg. Table Cross Reference 208-Lead SQFP Package (pg. 168-Pin Grid Array Figure Package Diagram 168-Pin Embedded IntelDX2Processor (pg. Table Pinout Differences 168-Pin Package (pg. Table Assignment 168-Pin Package (pg. Table Cross Reference 168-Pin Package (pg.
Embedded IntelDX2Processor
PCHK# BRDY# BOFF# BS16# BS8# RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3# M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
LOCK# PLOCK# BLAST# ADS# RESERVED
208-Lead SQFP Embedded IntelDX2Processor
View
SRESET SMIACT# SMI# FERR# IGNNE# STPCLK#
A3227-01
Figure Package Diagram 208-Lead SQFP Embedded IntelDX2Processor
Embedded IntelDX2Processor
Table Pinout Differences 208-Lead SQFP Package Embedded Intel486SX Processor
VCC1 INC2
Embedded IntelDX2Processor
FERR# IGNNE#
Embedded Write-Back Enhanced IntelDX4Processor
VCC5 CLKMUL HITM# WB/WT# FERR# CACHE# IGNNE#
NOTES: This location VCC5 embedded IntelDX4 processor. compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this should connected trace, plane. INC. Internal Connect. These pins connected internal embedded IntelDX2 processor. However, signals defined location pins embedded IntelDX4 processor. system design accommodate these processors provided purpose each understood before used.
Embedded IntelDX2Processor
Description
SRESET SMIACT# INC2 INC2 SMI# FERR# INC2 INC2 IGNNE# STPCLK#
Table Assignment 208-Lead SQFP Package (Sheet Pin#
Description
VCC1 PCHK# BRDY# BOFF# BS16# BS8# INC2 RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1#
Pin#
Pin#
Description
Pin#
Description
Pin#
Embedded IntelDX2Processor
Table Assignment 208-Lead SQFP Package (Sheet Description
BE2# BE3# M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
Pin#
Description
Pin#
Description
Pin#
Description
RESERVED ADS# BLAST# PLOCK# LOCK#
NOTES: This location VCC5 embedded IntelDX4 processor. compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this should connected trace, plane. INC. Internal Connect. These pins connected internal embedded IntelDX2 processors. However, signals defined location pins IntelDX4 processor. system design accommodate these processors provided purpose each understood before used. Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors.
Embedded IntelDX2Processor
Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# D/C# EADS# FERR# FLUSH# HLDA HOLD IGNNE# INTR KEN# LOCK# M/IO# PCHK# PLOCK# RDY# RESERVED RESET
Table Cross Reference 208-Lead SQFP Package (Sheet Address Data
Address Data Control SMI# SMIACT# SRESET STPCLK# W/R#
Embedded IntelDX2Processor
Table Cross Reference 208-Lead SQFP Package (Sheet
Embedded IntelDX2Processor
168-Pin Embedded IntelDX2Processor
SMI#
SRESET
Side View
RESERVED
SMIACT#
FERR#
IGNNE#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
BE2#
BE0#
D/C#
LOCK#
BREQ
INTR
RESET
BS8#
RDY#
BE1#
M/IO#
PLOCK# BLAST#
AHOLD EADS# BS16# BOFF#
BE3#
W/R#
PCHK#
ADS#
A3226-01
Figure Package Diagram 168-Pin Embedded IntelDX2Processor
Embedded IntelDX2Processor
Embedded IntelDX2Processor
Table Pinout Differences 168-Pin Package Embedded Write-Back Enhanced IntelDX4Processor HITM# CACHE# WB/WT# VCC5 CLKMUL VOLDET
Embedded IntelDX2Processor
Description BOFF#
Table Assignment 168-Pin Package (Sheet Description
Description HLDVCC
HOLD
KEN# RDY# BE3#
BREQ PLOCK# PCHK#
INC1 INC1 IGNNE# INTR AHOLD
STPCLK#
BRDY#
SMI#
BE2# BE1#
INC1 INC1
Description EADS#
Embedded IntelDX2Processor
Table Assignment 168-Pin Package (Sheet Description
Description
BE0#
BLAST# INC1
SRESET RESERVED SMIACT# FERR# FLUSH# RESET BS16# A20M# BS8#
D/C#
LOCK# M/IO# W/R#
ADS#
NOTES: INC. Internal Connect. These pins connected internal embedded IntelDX2 processors. However, signals defined location pins IntelDX4 processor. system design accommodate these processors provided purpose each understood before used. Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors.
Embedded IntelDX2Processor
Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# D/C# EADS# FERR# FLUSH# HLDA HOLD IGNNE# INTR KEN# LOCK# M/IO# PCHK# PLOCK# RDY# RESERVED RESET
Table Cross Reference 168-Pin Package (Sheet Address Data
Address Data Control SMI# SMIACT# SRESET STPCLK# W/R#
Embedded IntelDX2Processor
Table Cross Reference 168-Pin Package (Sheet
Embedded IntelDX2Processor
Quick Reference
following brief description. detailed signal descriptions refer "Signal Description" section Intel486Processor Family datasheet. Table Embedded IntelDX2Processor Descriptions (Sheet Symbol Type Name Function Clock provides fundamental timing internal operating frequency embedded IntelDX2 processor. external timing parameters specified with respect rising edge CLK. Address Lines A31-A2, together with byte enable signals, BE3#-BE0#, define physical area memory input/output space accessed. Address lines A31-A4 used drive addresses into embedded IntelDX2 processor perform cache line invalidation. Input signals must meet setup hold times t23. A31-A2 driven during address hold. Byte Enable signals indicate active bytes during read write cycles. During first cycle cache fill, external system should assume that byte enables active. BE3#-BE0# active driven during hold. BE3# applies D31-D24 BE2# applies D23-D16 BE1# applies D15-D8 BE0# applies D7-D0 Data Lines. D7-D0 define least significant byte data bus; D31-D24 define most significant byte data bus. These signals must meet setup hold times proper operation reads. These pins driven during second subsequent clocks write cycles. There Data Parity each byte data bus. Data parity generated write data cycles with same timing data driven embedded IntelDX2 processor. Even parity information must driven back into processor data parity pins with same timing read information ensure that correct parity check status indicated embedded IntelDX2 processor. signals read these pins affect program execution. Input signals must meet setup hold times t23. DP3-DP0 must connected through pull-up resistor systems that parity. DP3- active HIGH driven during second subsequent clocks write cycles. PCHK# Parity Status driven PCHK# clock after ready read operations. parity status data sampled previous clock. parity error indicated PCHK# being LOW. Parity status only checked enabled bytes indicated byte enable size signals. PCHK# valid only clock immediately after read data returned processor. other times PCHK# inactive (HIGH). PCHK# never floated.
ADDRESS A31-A4 A3-A2
BE3# BE2# BE1# BE0#
DATA D31-D0
DATA PARITY DP3-DP0
Symbol M/IO# D/C# W/R# Type CYCLE DEFINITION
Embedded IntelDX2Processor
Table Embedded IntelDX2Processor Descriptions (Sheet Name Function Memory/Input-Output, Data/Control Write/Read lines primary definition signals. These signals driven valid ADS# signal asserted. M/IO# D/C# W/R# Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) Read Write Code Read Reserved Memory Read Memory Write HALT/Special Cycle Cycle Name Shutdown HALT Stop Grant cycle LOCK# BE3# BE0# 1110 1011 1011 A4-A2
Lock indicates that current cycle locked. embedded IntelDX2 processor does allow hold when LOCK# asserted (address holds allowed). LOCK# goes active first clock first locked cycle goes inactive after last clock last locked cycle. last locked cycle ends when Ready returned. LOCK# active driven during hold. Locked read cycles transformed into cache fill cycles when KEN# returned active. Pseudo-Lock indicates that current transaction requires more than cycle complete. embedded IntelDX2 processor, examples such operations segment table descriptor reads bits) cache line fills (128 bits). Intel486 processors with on-chip Floating-Point Unit, floating-point long reads writes bits) also require more than cycle complete. embedded IntelDX2 processor drives PLOCK# active until addresses last cycle transaction driven, regardless whether RDY# BRDY# have been returned. Normally PLOCK# BLAST# inverse each other. However, during first cycle 64-bit floating-point write (for Intel486 processors with on-chip Floating-Point Unit) both PLOCK# BLAST# asserted. PLOCK# function BS8#, BS16# KEN# inputs. PLOCK# should sampled only clock which Ready returned. PLOCK# active driven during hold.
PLOCK#
CONTROL ADS# Address Status output indicates that valid cycle definition address available cycle definition lines address bus. ADS# driven active same clock which addresses driven. ADS# active driven during hold.
Embedded IntelDX2Processor
Name Function
Table Embedded IntelDX2Processor Descriptions (Sheet Symbol RDY# Type
Non-burst Ready input indicates that current cycle complete. RDY# indicates that external system presented valid data data pins response read that external system accepted data from embedded IntelDX2 processor response write. RDY# ignored when idle first clock cycle. RDY# active during address hold. Data returned embedded IntelDX2 processor while AHOLD active. RDY# active provided with internal pull-up resistor. RDY# must satisfy setup hold times proper chip operation.
BURST CONTROL BRDY# Burst Ready input performs same function during burst cycle that RDY# performs during non-burst cycle. BRDY# indicates that external system presented valid data response read that external system accepted data response write. BRDY# ignored when idle first clock cycle. BRDY# sampled second subsequent clocks burst cycle. Data presented data strobed into embedded IntelDX2 processor when BRDY# sampled active. RDY# returned simultaneously with BRDY#, BRDY# ignored burst cycle prematurely aborted. BRDY# active provided with small pull-up resistor. BRDY# must satisfy setup hold times t17. BLAST# Burst Last signal indicates that next time BRDY# returned, burst cycle complete. BLAST# active both burst non-burst cycles. BLAST# active driven during hold. Reset input forces embedded IntelDX2 processor begin execution known state. processor cannot begin executing instructions until least after VCC, have reached their proper specifications. RESET must remain active during this time ensure proper processor operation. However, warm resets, RESET should remain active least periods. RESET active HIGH. RESET asynchronous must meet setup hold times recognition specific clock. Maskable Interrupt indicates that external interrupt been generated. When internal interrupt flag EFLAGS, active interrupt processing initiated. embedded IntelDX2 processor generates locked interrupt acknowledge cycles response INTR going active. INTR must remain active until interrupt acknowledges have been performed ensure processor recognition interrupt. INTR active HIGH provided with internal pull-down resistor. INTR asynchronous, must meet setup hold times recognition specific clock.
INTERRUPTS RESET
INTR
Symbol Type
Embedded IntelDX2Processor
Table Embedded IntelDX2Processor Descriptions (Sheet Name Function Non-Maskable Interrupt request signal indicates that external non-maskable interrupt been generated. rising-edge sensitive must held least four periods before this rising edge. provided with internal pull-down resistor. asynchronous, must meet setup hold times recognition specific clock. Soft Reset duplicates functionality RESET except that SMBASE register retains previous value. soft resets, SRESET must remain active least periods. SRESET active HIGH. SRESET asynchronous must meet setup hold times recognition specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# falling-edge triggered signal which forces embedded IntelDX2 processor into completion current instruction. SMI# recognized instruction boundary each iteration repeat string instructions. SMI# does break LOCKed cycles cannot interrupt currently executing SMM. embedded IntelDX2 processor latches falling edge pending SMI# signal while executing existing SMI#. nested SMI# recognized until after execution Resume (RSM) instruction. System Management Interrupt Active, active output, indicates that embedded IntelDX2 processor operating SMM. asserted when processor begins execute SMI# state save sequence remains active until processor executes last state restore cycle SMRAM. Stop Clock Request input signal indicates request made turn change input frequency. When embedded IntelDX2 processor recognizes STPCLK#, stops execution next instruction boundary (unless superseded higher priority interrupt), empties internal pipelines write buffers, generates Stop Grant cycle. STPCLK# active LOW. STPCLK# asynchronous signal, must remain active until embedded IntelDX2 processor issues Stop Grant cycle. STPCLK# de-asserted time after processor issued Stop Grant cycle. Request signal indicates that embedded IntelDX2 processor internally generated request. BREQ generated whether processor driving bus. BREQ active HIGH never floated. Hold Request allows another master complete control embedded IntelDX2 processor bus. response HOLD going active, processor floats most output input/output pins. HLDA asserted after completing current cycle, burst cycle sequence locked cycles. embedded IntelDX2 processor remains this state until HOLD de-asserted. HOLD active HIGH provided with internal pull-down resistor. HOLD must satisfy setup hold times proper operation.
SRESET
SMI#
SMIACT#
STPCLK#
ARBITRATION BREQ
HOLD
Embedded IntelDX2Processor
Name Function
Table Embedded IntelDX2Processor Descriptions (Sheet Symbol HLDA Type
Hold Acknowledge goes active response hold request presented HOLD pin. HLDA indicates that embedded IntelDX2 processor given another local master. HLDA driven active same clock that processor floats bus. HLDA driven inactive when leaving hold. HLDA active HIGH remains driven during hold. Backoff input forces embedded IntelDX2 processor float next clock. processor floats pins normally floated during hold HLDA asserted response BOFF#. BOFF# higher priority than RDY# BRDY#; both returned same clock, BOFF# takes effect. embedded IntelDX2 processor remains hold until BOFF# negated. cycle progress when BOFF# asserted cycle restarted. BOFF# active must meet setup hold times proper operation. Address Hold request allows another master access embedded IntelDX2 processor's address cache invalidation cycle. processor stops driving address clock following AHOLD going active. Only address floated during address hold, remainder remains active. AHOLD active HIGH provided with small internal pull-down resistor. proper operation, AHOLD must meet setup hold times t19. External Address This signal indicates that valid external address been driven onto embedded IntelDX2 processor address pins. This address used perform internal cache invalidation cycle. EADS# active provided with internal pull-up resistor. EADS# must satisfy setup hold times proper operation. Cache Enable used determine whether current cycle cacheable. When embedded IntelDX2 processor generates cycle that cached KEN# active clock before RDY# BRDY# during first transfer cycle, cycle becomes cache line fill cycle. Returning KEN# active clock before RDY# during last read cache line fill causes line placed on-chip cache. KEN# active provided with small internal pullup resistor. KEN# must satisfy setup hold times proper operation. Cache Flush input forces embedded IntelDX2 processor flush entire internal cache. FLUSH# active need only asserted clock. FLUSH# asynchronous setup hold times must recognition specific clock. Page Write-Through Page Cache Disable pins reflect state page attribute bits, PCD, page table entry, page directory entry control register (CR3) when paging enabled. When paging disabled, embedded IntelDX2 processor ignores bits assumes they zero purpose caching driving pins. have same timing cycle definition pins (M/IO#, D/C#, W/R#). active HIGH driven during hold. masked cache disable (CD) Control Register
BOFF#
CACHE INVALIDATION AHOLD
EADS#
CACHE CONTROL KEN#
FLUSH#
PAGE CACHEABILITY
Symbol BS16# BS8# Type SIZE CONTROL
Embedded IntelDX2Processor
Table Embedded IntelDX2Processor Descriptions (Sheet Name Function Size Size pins (bus sizing pins) cause embedded IntelDX2 processor multiple cycles complete request from devices that cannot provide accept bits data single cycle. sizing pins sampled every clock. processor uses state these pins clock before Ready determine size. These signals active provided with internal pull-up resistors. These inputs must satisfy setup hold times proper operation. Address Mask pin, when asserted, causes embedded IntelDX2 processor mask physical address (A20) before performing lookup internal cache driving memory cycle bus. A20M# emulates address wraparound Mbyte, which occurs 8086 processor. A20M# active should asserted only when embedded IntelDX2 processor real mode. This asynchronous should meet setup hold times recognition specific clock. proper operation, A20M# should sampled HIGH falling edge RESET. Test Clock, input embedded IntelDX2 processor, provides clocking function required JTAG Boundary scan feature. used clock state information (via TMS) data (via TDI) into component rising edge TCK. Data clocked component (via TDO) falling edge TCK. provided with internal pull-up resistor. Test Data Input serial input used shift JTAG instructions data into processor. sampled rising edge TCK, during SHIFT-IR SHIFT-DR Test Access Port (TAP) controller states. During other controller states, "don't care." provided with internal pull-up resistor. Test Data Output serial output used shift JTAG instructions data component. driven falling edge during SHIFT-IR SHIFT-DR controller states. other times driven high impedance state. Test Mode Select decoded JTAG select test logic operation. sampled rising edge TCK. guarantee deterministic behavior controller, provided with internal pull-up resistor.
ADDRESS MASK A20M#
TEST ACCESS PORT
Embedded IntelDX2Processor
Name Function
Table Embedded IntelDX2Processor Descriptions (Sheet Symbol FERR# Type
NUMERIC ERROR REPORTING Floating Point Error driven active when floating point error occurs. FERR# similar ERROR# Intel387Math CoProcessor. FERR# included compatibility with systems using type floating point error reporting. FERR# will active errors masked register. FERR# active LOW, floated during hold. When Ignore Numeric Error asserted processor will ignore numeric error continue executing non-control floating point instructions, FERR# will still activated processor. When IGNNE# de-asserted processor will freeze non-control floating point instruction, previous floating point instruction caused error. IGNNE# effect when control register set. IGNNE# active provided with small internal pull-up resistor. IGNNE# asynchronous setup hold times must ensure recognition specific clock. Reserved reserved future use. This MUST connected external pull-up resistor circuit. recommended resistor value kOhms. pull-up resistor must connected only RESERVED pin. share this resistor with other pins requiring pull-ups.
IGNNE#
RESERVED PINS RESERVED
Table Output Pins Name BREQ HLDA BE3#-BE0# PWT, W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# FERR# A3-A2 SMIACT# Active Level HIGH HIGH HIGH HIGH/LOW HIGH Floated During Address Hold
Embedded IntelDX2Processor
Output Signal Floated During Hold During Stop Grant Stop Clock States Previous State HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State Previous State Previous State
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Input/Output Pins Output Signal Name D31-D0 DP3-DP0 A31-A4 Active Level HIGH HIGH HIGH Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States Floated Floated Previous State
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Test Pins Name Input Output Input Input Output Input Sampled/ Driven Rising Edge Failing Edge Rising Edge
Embedded IntelDX2Processor
Table Input Pins Active Level Synchronous/ Asynchronous
Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down
Name
RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR IGNNE# RESERVED SMI# STPCLK#
Internal Pull-Up/ Pull-Down
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
NOTE: Though STPCLK# internal pull-up resistor, external 10-K pull-up resistor needed STPCLK# unused.
ARCHITECTURAL FUNCTIONAL OVERVIEW
Operation Testability Debugging Support Instruction Summary Differences Between Intel486 Processors Intel386Processors Exceptions these sections datasheet are: References Upgrade Power Down Mode apply. embedded IntelDX2 processor does have signal does support Intel OverDrive® processor.
embedded IntelDX2 processor architecture essentially same IntelDX2 processor. Refer Intel486Processor Family datasheet (242202) description IntelDX2 processor. With some minor exceptions, following datasheet sections apply embedded IntelDX2 processor: Architectural Overview Real Mode Architecture Protected Mode Architecture On-Chip Cache System Management Mode (SMM) Architectures Hardware Interface
embedded IntelDX2 processor reserved possible future use. This pin, input signal, called RESERVED must connected 10-K pull-up resistor. pull-up resistor must connected only RESERVED pin. share this resistor with other pins requiring pull-ups.
Embedded IntelDX2Processor
ware. This cleared (reset zero) upon device reset (RESET SRESET) compatibility with Intel486 processor designs that support CPUID instruction. CPUID-instruction details provided here embedded IntelDX2 processor. Refer Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction (Order 241618) description that covers aspects CPUID instruction pertains other Intel processors. 4.1.1 Operation CPUID Instruction
CPUID Instruction
embedded IntelDX2 processor supports CPUID instruction (see Table 13). Because Intel processors support CPUID instruction, simple test determine instruction supported. test involves processor's Flag, which EFLAGS register. software change value this flag, CPUID instruction available. actual state Flag irrelevant provides significance hard-
CPUID instruction requires software developer pass input parameter processor register. processor response returned registers EAX, EBX, EDX, ECX.
Table CPUID Instruction Description CODE Instruction CPUID Processor Core Clocks Parameter passed
(Input Value)
Description Vendor (Intel) String Processor Identification Undefined Use)
Vendor String When parameter passed (zero), register values returned upon instruction execution shown following table. 31-24 High Value Vendor String (ASCII Characters) (75) (49) (6C) 23-16 (6E) (65) (65) 15-8 (65) (6E) (74) (47) (69) (6E)
values EBX, indicate Intel processor. When taken proper order, they decode string "GenuineIntel."
Embedded IntelDX2Processor
13,12 Processor Type 11-8 0100 Family 0011 Model XXXX Stepping
Processor Identification When parameter passed (one), register values returned upon instruction execution are:
31-14 Processor Signature Use) Intel Reserved
(Intel releases information about stepping numbers needed) 31-0 Intel Reserved Use) Intel Reserved Intel Reserved 31-2 Feature Flags
Identification After Reset
31-14 Processor Signature Use) Intel Reserved 13,12 Processor Type 11-8 0100 Family 0011 Model XXXX Stepping
Processor Identification Upon reset, register contains processor signature:
(Intel releases information about stepping numbers needed)
4.3.1
Boundary Scan (JTAG)
Device Identification
Tables show 32-bit code embedded IntelDX2 processor. This code loaded into Device Identification Register. Table Boundary Scan Component Identification Code (3.3 Volt Processor)
Version 1=3.3 31-28 XXXX Part Number Model 00101 embedded IntelDX2 processor 16-12 00101 009H Intel
Intel Architecture Type
26-21 000001
Family 0100 Intel486 Family 20-17 0100
11-1 00000001001
(Intel releases information about version numbers needed) Boundary Scan Component Identification Code x828 5013 (Hex)
Version 1=3.3 31-28 XXXX Intel Architecture Type 26-21 000001 Part Number Family 0100 Intel486 Family 20-17 0100
Embedded IntelDX2Processor
Table Boundary Scan Component Identification Code Volt Processor)
Model 00101 embedded IntelDX2 processor 16-12 00101 009H Intel
11-1 00000001001
(Intel releases information about version numbers needed)
Boundary Scan Component Identification Code x028 5013 (Hex)
4.3.2
Boundary Scan Register Bits Order
following order embedded IntelDX2 processor boundary scan register:
boundary scan register contains cell each well cells control bidirectional three-state pins. There "Reserved" bits which correspond no-connect (N/C) signals embedded IntelDX2 processor. Control registers WRCTL, ABUSCTL, BUSCTL, MISCCTL used select direction bidirectional threestate output signal pins. these cells designates that associated bits floated pins three-state, selected input they bidirectional. WRCTL controls D31-D0 DP3-DP0 ABUSCTL controls A31-A2 BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, MISCCTL controls PCHK#, HLDA, BREQ
RESERVED, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, DP1, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, IGNNE#, FERR#, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
Embedded IntelDX2Processor
Specifications
following tables show operating supply voltages, specifications, component power consumption embedded IntelDX2 processor. Table Operating Supply Voltages Product SB80486DX2SC50 A80486DX2SA66 0.25
ELECTRICAL SPECIFICATIONS Maximum Ratings
Table stress rating only. Extended exposure Maximum Ratings affect device reliability. Furthermore, although embedded IntelDX2 processor contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields. Functional operating conditions given Section 5.2, Specifications Section 5.3, Specifications. Table Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Voltage with Respect Ground Supply Voltage with Respect +110 +150 -0.5 -0.5 +6.5
Embedded IntelDX2Processor
Table Specifications Functional Operating Range: TCASE=0 Symbol
VIHC
Parameter
Input Voltage Input HIGH Voltage Input HIGH Voltage Output Voltage
Min.
-0.3 -0.6
Max.
+0.8 +0.3 +0.3
Unit
Notes
Note
Output HIGH Voltage -2.0 -100 -0.2 -400
COUT CCLK
Input Leakage Current Input Leakage Current SRESET Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance
Note Note Note Note
Note Note Note
NOTES: inputs except CLK. This parameter inputs without pull-up pull-down resistors VCC. This parameter inputs with pull-down resistors 2.4V. This parameter inputs with pull-up resistors 0.4V. FC=1 MHz. 100% tested.
Embedded IntelDX2Processor
Table Values Functional Operating Range: ±0.3 TCASE +85°C Parameter Active (Power Supply) Active (Thermal Design) Stop Grant Stop Clock Operating Frequency Maximum Notes Note Notes Note Note
NOTES: This parameter proper power supply selection. measured using worst case instruction 3.6V. maximum current column thermal design power dissipation. measured using worst case instruction 3.3V. typical current column typical operating current system. This value measured system using typical device 3.3V, running Microsoft Windows idle condition. This typical value dependent upon specific system configuration. Typical values 100% tested. Stop Grant specification refers value once embedded IntelDX2 processor enters Stop Grant Auto HALT Power Down state. Stop Clock specification refers value once embedded IntelDX2 processor enters Stop Clock state. levels must equal respectively, meet Stop Clock specifications.
Symbol COUT CCLK Parameter Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Input Leakage Current Input Leakage Current SRESET Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance -0.3
Embedded IntelDX2Processor
Table Specifications Functional operating range: 0.25V; TCASE +85°C +0.8 VCC+0.3 0.45 -400 Unit Note Note Note Note Note Note Note Note Note Notes
NOTES: This parameter measured Address, Data, Definition, Control This parameter measured Address, Data, -1.0 Definition, Control -0.9 This parameter inputs without pull-ups pull-downs VCC. This parameter inputs with pull-downs 2.4V. This parameter inputs with pull-ups 0.45V. FC=1 MHz; 100% tested.
Embedded IntelDX2Processor
Table Values Functional Operating Range: ±0.25V; TCASE +85°C Parameter Active (Power Supply) Active (Thermal Design) Stop Grant Stop Clock Operating Frequency Maximum 1200 1145 Notes Note Notes Note Note
NOTES: This parameter proper power supply selection. measured using worst case instruction 5.25V. maximum current column thermal design power dissipation. measured using worst case instruction typical current column typical operating current system. This value measured system using typical device running Microsoft Windows idle condition. This typical value dependent upon specific system configuration. Typical values 100% tested. Stop Grant specification refers value once embedded IntelDX2 processor enters Stop Grant Auto HALT Power Down state. Stop Clock specification refers value once processor enters Stop Clock state. levels must equal respectively, order meet Stop Clock specifications.
Specifications
Embedded IntelDX2Processor
specifications embedded IntelDX2 processor given this section. Table Characteristics TCASE +85°C; 50pF, unless otherwise specified. (Sheet (Package) Symbol Parameter Frequency Period Period Stability High Time Time Fall Time Rise Time A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#, FERR# Valid Delay A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay BLAST#, PLOCK# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time EADS# Hold Time KEN#, BS16#, BS8# Setup Time KEN#, BS16#, BS8# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time HOLD, AHOLD Setup Time BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time 3.3V (208-Lead SQFP) ±250 (168-Pin PGA) ±250 Unit Adjacent clocks 0.8V 0.8V 0.8V Figure Notes Note
Note
t18a
Note Note
Embedded IntelDX2Processor
(Package) 3.3V (208-Lead SQFP) (168-Pin PGA) Unit Figure Notes Note
Table Characteristics TCASE +85°C; 50pF, unless otherwise specified. (Sheet
Symbol
Parameter FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time
Note
NOTES: 0-MHz operation guaranteed when STPCLK# Stop Grant cycle protocol used. 100% tested, guaranteed design characterization. reset pulse width cycles required warm resets (RESET SRESET). Power-up resets (cold resets) require RESET asserted least after stable.
Embedded IntelDX2Processor
Table Specifications Test Access Port (Both 3.3V SQFP Processors) TCASE +85°C; Symbol Frequency Period High Time Time Rise Time Fall Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Outputs (except TDO) Valid Delay Outputs (except TDO) Float Delay Inputs (except TDI, TMS, TCK) Setup Time Inputs (except TDI, TMS, TCK) Hold Time Parameter Unit 2.0V 0.8V Note Note Note Note Note Note Note Note Note Note Figure Notes Note
NOTES: period period. Rise/Fall times measured between 0.8V 2.0V. Rise/Fall times relaxed 10-ns increase period. Parameters measured from TCK.
input setup times input hold times, output float, valid hold times Figure Waveform
Embedded IntelDX2Processor
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET, IGNNE# A31-A4 (READ)
Figure Input Setup Hold Timing
RDY#, BRDY#
D31-D0, DP3-DP0
Figure Input Setup Hold Timing
Embedded IntelDX2Processor
RDY#, BRDY#
D31-D0, DP3-DP0
VALID
PCHK#
VALID
Figure PCHK# Valid Delay Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID
VALID
D31-D0, DP3-DP0
VALID
VALID
BLAST#, PLOCK#
VALID
VALID
Figure Output Valid Delay Timing
Embedded IntelDX2Processor
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, FERR#
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure Maximum Float Delay Timing
Figure Waveform
TMS, OUTPUT INPUT VALID VALID VALID VALID VALID
Embedded IntelDX2Processor
Figure Test Signal Timing Diagram
Embedded IntelDX2Processor
Capacitive Derating Curves
following graphs capacitive derating curves embedded IntelDX2 processor. nom+7 nom+6 nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2 Capacitive Load (pF) NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2 Capacitive Load (pF)
NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor
nom+5 nom+4
Embedded IntelDX2Processor
Delay (ns)
nom+3 nom+2 nom+1 nom-1 nom-2
Capacitive Load (pF) Note: This graph will linear outside capacitive range shown. nominal value from Characteristics table.
A3234-01
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor
nom+7 nom+6 nom+5 nom+4
Delay (ns)
nom+3 nom+2 nom+1 nom-1 nom-2
Note:
Capacitive Load (pF)
This graph will linear outside capacitive range shown. nominal value from Characteristics table.
A3235-01
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor
Embedded IntelDX2Processor
MECHANICAL
This section describes packaging dimensions thermal specifications embedded IntelDX2 processor.
Package Dimensions
30.6 0.25 28.0 0.10
1.14 (ref)
25.50 (ref)
0.13 0.12-0.08
0.60 0.10 1.30
0.50
View
3.37 0.08 3.70
0.13 0.25
NOTE: Length measurements same width measurements 1.76 Tolerance Window Lead Skew from Theoretical True Position 0.10
Units:
A3262-01
Figure 208-Lead SQFP Package Dimensions
Embedded IntelDX2Processor
Figure Principal Dimensions Data 168-Pin Grid Array Package Table 168-Pin Ceramic Package Dimensions Symbol 1.52 Millimeters 3.56 0.64 1.14 0.43 44.07 40.51 2.29 2.54 2.54 0.060 4.57 1.14 1.40 0.51 44.83 40.77 2.79 3.30 SOLID SOLID Notes 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 0.100 Inches 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID SOLID Notes
Embedded IntelDX2Processor
Description Dimensions Distance from seating plane highest point body Distance between seating plane base plane (lid) Distance from base plane highest point body Distance from seating plane bottom body Diameter terminal lead Largest overall package dimension length body length dimension, outer lead center outer lead center Linear spacing between true lead position centerlines Distance from seating plane lead Other body dimension, outer lead center edge body
Table Ceramic Package Dimension Symbols Letter Symbol
NOTES: Controlling dimension: millimeter. Dimension "e1" ("e") non-cumulative. Seating plane (standoff) defined P.C. board hole size: 0.0415-0.0430 inch. Dimensions "B", "B1" nominal. Details identifier optional.
Package Thermal Specifications
embedded IntelDX2 processor specified operation when case temperature (TC) within range 85°C. measured environment determine whether processor within specified operating range. ambient temperature (TA) calculated from from following equations:
Embedded IntelDX2Processor
Where equals Junction, Ambient Case Temperature respectively. equals Junction-to-Case Junction-to-Ambient thermal Resistance, respectively. defined Maximum Power Consumption. Values given following tables each product maximum operating frequencies. Maximum shown each product operating various processor frequencies (twice frequencies).
Table Thermal Resistance, (°C/W) Airflow ft/min. (m/sec) 208-Lead SQFP (3.3V) Without Heat Sink 168-Pin (5V) Without Heat Sink 168-Pin (5V) With Heat Sink*
*0.350" high omnidirectional heat sink.
(1.01) 17.0 14.5
(2.03) 15.0 12.5
(3.04) 13.0 11.0
(4.06) 10.0
1000 (5.07) 4.25
24.0 17.0 13.0
Table Thermal Resistance, (°C/W) Airflow ft/min. (m/sec) 208-Lead SQFP (3.3V) 168-Pin (5V) (1.01) (2.03) (3.04)
Table Maximum Tambient, (°C) Airflow ft/min. (m/sec) Freq. (MHz) IntelDX2Processor 208-Lead SQFP (3.3V) Without Heat Sink 168-Pin (5V) Without Heat Sink 168-Pin (5V) With Heat Sink (1.01) (2.03) (3.04)

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