High-Performance, 16-Bit Microcontrollers 2009 Microchip Technolo
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PIC24HJXXXGPX06/X08/X10 Data Sheet
High-Performance, 16-Bit Microcontrollers
2009 Microchip Technology Inc.
DS70175H
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS70175H-page
2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
High-Performance, 16-Bit Microcontrollers
Operating Range:
MIPS operation 3.0-3.6V): Industrial temperature range (-40°C +85°C)
On-Chip Flash SRAM:
Flash program memory, Kbytes Data SRAM, Kbytes (includes Kbytes RAM)
High-Performance CPU:
Modified Harvard architecture compiler optimized instruction 16-bit wide data path 24-bit wide instructions Linear program memory addressing instruction words Linear data memory addressing Kbytes base instructions: mostly word/1 cycle Sixteen 16-bit General Purpose Registers Flexible powerful Indirect Addressing modes Software stack multiply operations 32/16 16/16 divide operations ±16-bit data shifts
System Management:
Flexible clock options: External, crystal, resonator, internal Fully integrated Extremely jitter Power-up Timer Oscillator Start-up Timer/Stabilizer Watchdog Timer with oscillator Fail-Safe Clock Monitor Reset multiple sources
Power Management:
On-chip 2.5V voltage regulator Switch between clock sources real time Idle, Sleep Doze modes with fast wake-up
Direct Memory Access (DMA):
8-channel hardware Kbytes dual ported buffer area (DMA RAM) store data transferred DMA: Allows data transfer between peripheral while executing code cycle stealing) Most peripherals support
Timers/Capture/Compare/PWM:
Timer/Counters, nine 16-bit timers: pair make four 32-bit timers timer runs Real-Time Clock with external 32.768 oscillator Programmable prescaler Input Capture eight channels): Capture down both edges 16-bit capture input functions 4-deep FIFO each capture Output Compare eight channels): Single Dual 16-Bit Compare mode 16-bit Glitchless mode
Interrupt Controller:
5-cycle latency available interrupt sources five external interrupts Seven programmable priority levels FIve processor exceptions programmable digital pins Wake-up/Interrupt-on-Change pins Output pins drive from 3.0V 3.6V digital input pins tolerant sink pins
Digital I/O:
2009 Microchip Technology Inc.
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Communication Modules:
3-wire modules): Framing supports interface simple codecs Supports 8-bit 16-bit data Supports serial clock formats sampling modes I2C(up modules): Full Multi-Master Slave mode support 7-bit 10-bit addressing collision detection arbitration Integrated signal conditioning Slave address masking UART modules): Interrupt address detect Interrupt UART error Wake-up Start from Sleep mode 4-character FIFO buffers support IrDA® encoding decoding hardware High-Speed Baud mode Hardware Flow Control with Enhanced (ECANmodule) 2.0B active modules): eight transmit receive buffers receive filters masks Loopback, Listen Only Listen Messages modes diagnostics monitoring Wake-up message Automatic processing Remote Transmission Requests FIFO mode using DeviceNetaddressing support
Analog-to-Digital Converters:
Analog-to-Digital Converter (ADC) modules device 10-bit, Msps 12-bit, ksps conversion: Two, four, eight simultaneous samples input channels with auto-scanning Conversion start manual synchronized with four trigger sources Conversion possible Sleep mode integral nonlinearity differential nonlinearity
CMOS Flash Technology:
Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial temperature Low-power consumption
Packaging:
100-pin TQFP (14x14x1 12x12x1 64-pin TQFP (10x10x1 Note: device variant tables exact peripheral features device.
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PIC24HJXXXGPX06/X08/X10
PIC24H PRODUCT FAMILIES
PIC24H Family devices ideal wide variety 16-bit embedded applications. device names, counts, memory sizes peripheral availability each device listed below, followed their pinout diagrams.
PIC24H Family Controllers
Output Compare Std. Program Flash Memory (KB) Pins (Max)(2) Channels Input Capture Timer 16-bit RAM(1) (KB) Codec Interface UART CCAN
PIC24HJ64GP206 PIC24HJ64GP210 PIC24HJ64GP506 PIC24HJ64GP510 PIC24HJ128GP206 PIC24HJ128GP210 PIC24HJ128GP506 PIC24HJ128GP510 PIC24HJ128GP306 PIC24HJ128GP310 PIC24HJ256GP206 PIC24HJ256GP210 PIC24HJ256GP610 Note
ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC,
Device
Pins
Packages
size inclusive Kbytes RAM. Maximum count includes pins shared peripheral functions.
2009 Microchip Technology Inc.
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PIC24HJXXXGPX06/X08/X10
Diagrams
64-Pin TQFP
RG13 RG12 RG14 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
Pins tolerant
RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0
PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
Note:
PIC24HJ64GP206 device does have SCL2 SDA2 pins.
PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5
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PIC24HJXXXGPX06/X08/X10
Diagrams (Continued)
64-Pin TQFP
RG13 RG12 RG14 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
Pins tolerant
RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0
PIC24HJ128GP306
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
2009 Microchip Technology Inc.
PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5
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PIC24HJXXXGPX06/X08/X10
Diagrams (Continued)
64-Pin TQFP
RG13 RG12 RG14 C1TX/RF1 C1RX/RF0 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
Pins tolerant
RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0
PIC24HJ64GP506 PIC24HJ128GP506
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5
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Diagrams (Continued)
100-Pin TQFP
Pins tolerant
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210
2009 Microchip Technology Inc.
PGEC1/AN6/OCFA/RB6 PGED1PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
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PIC24HJXXXGPX06/X08/X10
Diagrams (Continued)
100-Pin TQFP
Pins tolerant
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C1TX/RF1 C1RX/RF0 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ64GP510 PIC24HJ128GP510
PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
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2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Diagrams (Continued)
100-Pin TQFP
Pins tolerant
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0
PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ256GP610
2009 Microchip Technology Inc.
PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
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PIC24HJXXXGPX06/X08/X10
Table Contents
PIC24H Product Families. Device Overview Guidelines Getting Started with 16-Bit Microcontrollers CPU. Memory Organization Flash Program Memory Reset Interrupt Controller Direct Memory Access (DMA) Oscillator Configuration 10.0 Power-Saving Features. 11.0 Ports 12.0 Timer1 13.0 Timer2/3, Timer4/5, Timer6/7 Timer8/9 14.0 Input Capture. 15.0 Output Compare. 16.0 Serial Peripheral Interface (SPI). 17.0 Inter-Integrated Circuit(I2CTM) 18.0 Universal Asynchronous Receiver Transmitter (UART) 19.0 Enhanced (ECANTM) Module 20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) 21.0 Special Features 22.0 Instruction Summary 23.0 Development Support. 24.0 Electrical Characteristics 25.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
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Most Current Data Sheet
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Errata
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DS70175H-page
2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Note:
DEVICE OVERVIEW
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. However, intended comprehensive reference source. complement information this data sheet, refer latest family reference sections "PIC24H Family Reference Manual", which available from Microchip site (www.microchip.com).
This makes these families suitable wide variety high-performance digital signal control applications. devices compatible with dsPIC33F family devices, also share very high degree compatibility with dsPIC30F family devices. This allows easy migration between device families necessitated specific functionality, computational resource system cost requirements application. PIC24HJXXXGPX06/X08/X10 device family employs powerful 16-bit architecture, ideal applications that rely high-speed, repetitive computations, well control. multiplier, hardware support division operations, multi-bit data shifter, large array 16-bit working registers wide variety data addressing modes, together provide PIC24HJXXXGPX06/X08/X10 Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible deterministic interrupt handling, coupled with powerful array peripherals, renders PIC24HJXXXGPX06/X08/X10 devices suitable control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer data between several peripherals dedicated RAM. Reliable, field programmable Flash program memory ensures scalability applications that PIC24HJXXXGPX06/X08/X10 devices. Figure shows general block diagram various core peripheral modules PIC24HJXXXGPX06/X08/X10 family devices, while Table lists functions various pins shown pinout diagrams.
This document contains device specific information following devices: PIC24HJ64GP206 PIC24HJ64GP210 PIC24HJ64GP506 PIC24HJ64GP510 PIC24HJ128GP206 PIC24HJ128GP210 PIC24HJ128GP506 PIC24HJ128GP510 PIC24HJ128GP306 PIC24HJ128GP310 PIC24HJ256GP206 PIC24HJ256GP210 PIC24HJ256GP610
PIC24HJXXXGPX06/X08/X10 device family includes devices with different counts pins), different program memory sizes Kbytes, Kbytes Kbytes) different sizes Kbytes Kbytes).
2009 Microchip Technology Inc.
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PIC24HJXXXGPX06/X08/X10
FIGURE 1-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Address Latch Address Generator Units Controller
PORTB
PIC24HJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM
Data Data Latch
PORTA
PORTC
Address Latch
Program Memory Data Latch Latch
Literal Data PORTD
Instruction Decode Control Control Signals Various Blocks
OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Instruction
PORTE
Multiplier Register Array
PORTF
Divide Support
16-bit
PORTG
VCAP/VDDCORE
VDD,
MCLR
Timers
ADC1,2
ECAN1,2
UART1,2
IC1-8
PWM1-8
CN1-23
SPI1,2
I2C1,2
Note:
pins features implemented device pinout configurations. pinout diagrams specific pins features present each device.
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TABLE 1-1:
Name AN0-AN31 AVDD AVSS CLKI CLKO
PINOUT DESCRIPTIONS
Type Buffer Type Analog Analog input channels. Positive supply analog modules. This must connected times. Ground reference analog modules. Description
ST/CMOS External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Input change notification inputs. software programmed internal weak pull-ups inputs. ECAN1 receive pin. ECAN1 transmit pin. ECAN2 receive pin. ECAN2 transmit pin. Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Capture inputs through External interrupt External interrupt External interrupt External interrupt External interrupt Master Clear (Reset) input. This active-low Reset device. Compare Fault input (for Compare Channels Compare Fault input (for Compare Channels Compare outputs through
CN0-CN23 C1RX C1TX C2RX C2TX PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 IC1-IC8 INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OC1-OC8 OSC1 OSC2 RA0-RA7 RA9-RA10 RA12-RA15 RB0-RB15 RC1-RC4 RC12-RC15 RD0-RD15 RE0-RE7 RF0-RF8 RF12-RF13 RG0-RG3 RG6-RG9 RG12-RG15
ST/CMOS Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. PORTA bidirectional port.
PORTB bidirectional port. PORTC bidirectional port. PORTD bidirectional port. PORTE bidirectional port. PORTF bidirectional port. PORTG bidirectional port.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels
Analog Analog input Output
Power Input
2009 Microchip Technology Inc.
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TABLE 1-1:
Name SCK1 SDI1 SDO1 SCK2 SDI2 SDO2 SCL1 SDA1 SCL2 SDA2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VCAP/VDDCORE VREF+ VREF-
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type Description Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI2. SPI2 data SPI2 data out. SPI2 slave synchronization frame pulse I/O. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Synchronous serial clock input/output I2C2. Synchronous serial data input/output I2C2.
ST/CMOS 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Analog Analog JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input. UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. UART2 clear send. UART2 ready send. UART2 receive. UART2 transmit. Positive supply peripheral logic pins. logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels
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PIC24HJXXXGPX06/X08/X10
GUIDELINES GETTING STARTED WITH 16-BIT MICROCONTROLLERS
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", which available from Microchip website (www.microchip.com).
Decoupling Capacitors
Note:
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD AVSS required. Consider following criteria when using decoupling capacitors: Value type capacitor: Recommendation (100 nF), 10-20V. This capacitor should low-ESR have resonance frequency range higher. recommended that ceramic capacitors used. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor within one-quarter inch length. Handling high frequency noise: board experiencing high frequency noise, upward tens MHz, second ceramic-type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible. example, parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum thereby reducing track inductance.
Basic Connection Requirements
Getting started with PIC24HJXXXGPX06/X08/X10 family 16-bit Microcontrollers (MCUs) requires attention minimal device connections before proceeding with development. following list names, which must always connected: pins (see Section "Decoupling Capacitors") AVDD AVSS pins (regardless module used) (see Section "Decoupling Capacitors") VCAP/VDDCORE (see Section "Capacitor Internal Voltage Regulator (VCAP/VDDCORE)") MCLR (see Section "Master Clear (MCLR) Pin") PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section "ICSP Pins") OSC1 OSC2 pins when external oscillator source used (see Section "External Oscillator Pins") Additionally, following pins required: VREF+/VREF- pins used when external voltage reference module implemented Note: AVDD AVSS pins must connected independent voltage reference source.
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FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Ceramic
Master Clear (MCLR)
MCLR provides specific device functions: Device Reset Device programming debugging During device programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements.
VCAP/VDDCORE
MCLR
PIC24H
AVDD AVSS
Ceramic
Ceramic
Ceramic
Ceramic
example, shown Figure 2-2, recommended that capacitor isolated from MCLR during programming debugging operations. Place components shown Figure within one-quarter inch from MCLR pin.
2.2.1
TANK CAPACITORS
FIGURE 2-2:
boards with power traces running longer than inches length, suggested tank capacitor integrated circuits including MCUs supply local power source. value tank capacitor should determined based trace resistance that connects power supply source device, maximum current drawn device application. other words, select tank capacitor that meets acceptable voltage device. Typical values range from
EXAMPLE MCLR CONNECTIONS
MCLR PIC24H
Capacitor Internal Voltage Regulator (VCAP/VDDCORE)
Note
low-ESR Ohms) capacitor required VCAP/VDDCORE pin, which used stabilize voltage regulator output voltage. VCAP/VDDCORE must connected VDD, must have capacitor between connected ground. type ceramic tantalum. Refer Section 24.0 "Electrical Characteristics" additional information. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed one-quarter inch mm). Refer Section 21.2 "On-Chip Voltage Regulator" details.
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met.
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ICSP Pins External Oscillator Pins
PGECx PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes, capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. Ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB MPLAB REAL ICETM. more information REAL connection requirements, refer following documents that available Microchip website. "MPLAB® In-Circuit Debugger User's Guide" DS51331 "Using MPLAB® (poster) DS51265 "MPLAB® Design Advisory" DS51566 "Using MPLAB® In-Circuit Debugger" (poster) DS51765 "MPLAB® Design Advisory" DS51764 "MPLAB® REAL ICEIn-Circuit Emulator User's Guide" DS51616 "Using MPLAB® REAL ICETM" (poster) DS51749 Many MCUs have options least oscillators: high-frequency primary oscillator low-frequency secondary oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Also, place oscillator circuit close respective oscillator pins, exceeding one-half inch distance between them. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate them from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Main Oscillator Guard Ring Guard Trace Secondary Oscillator
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Oscillator Value Conditions Device Start-up
target device enabled configured device start-up oscillator, maximum oscillator source frequency must limited comply with device start-up conditions. This means that external oscillator frequency outside this range, application must start-up mode first. default settings after with oscillator frequency outside this range will violate device operating speed. Once device powers application firmware initialize SFRs, CLKDIV PLLDBF suitable value, then perform clock switch Oscillator clock source. Note that clock switching must enabled device Configuration word.
Configuration Analog Digital Pins During ICSP Operations
MPLAB REAL selected debugger, automatically initializes input pins (ANx) "digital" pins, setting bits AD1PCFGL register. bits this register that correspond pins that initialized MPLAB REAL ICE, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits AD1PCFGL register during initialization module. When MPLAB REAL used programmer, user application firmware must correctly configure AD1PCFGL register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic `0', which affect user application functionality.
Unused I/Os
Unused pins should configured outputs driven logic-low state. Alternatively, connect resistor unused pins drive output logic low.
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Note:
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "CPU" (DS70245), which available from Microchip website (www.microchip.com).
Data Addressing Overview
data space linearly addressed words Kbytes using Address Generation Unit (AGU). upper Kbytes data space memory optionally mapped into program space program word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. data space also includes Kbytes RAM, which primarily used data transfers, used general purpose RAM.
PIC24HJXXXGPX06/X08/X10 module 16-bit (data) modified Harvard architecture with enhanced instruction addressing modes. 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses bits user program memory space. actual amount program memory implemented varies device. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double word move (MOV.D) instruction table instructions. Overhead-free, single-cycle program loop constructs supported using REPEAT instruction, which interruptible point. PIC24HJXXXGPX06/X08/X10 devices have sixteen, 16-bit working registers programmer's model. Each working registers serve data, address address offset register. 16th working register (W15) operates software Stack Pointer (SP) interrupts calls. PIC24HJXXXGPX06/X08/X10 instruction includes many addressing modes designed optimum compiler efficiency. most instructions, PIC24HJXXXGPX06/X08/X10 capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing operations executed single cycle. block diagram shown Figure 3-1, programmer's model PIC24HJXXXGPX06/X08/X10 shown Figure 3-2.
Special Features
PIC24HJXXXGPX06/X08/X10 features 17-bit 17-bit, single-cycle multiplier. multiplier perform signed, unsigned mixed-sign multiplication. Using 17-bit 17-bit multiplier 16-bit 16-bit multiplication makes mixed-sign multiplication possible. PIC24HJXXXGPX06/X08/X10 supports 16/16 32/16 integer divide operations. divide instructions iterative operations. They must executed within REPEAT loop, resulting total execution time instruction cycles. divide operation interrupted during those cycles without loss data. multi-bit data shifter used perform 16-bit, left right shift single cycle.
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FIGURE 3-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data
PIC24HJXXXGPX06/X08/X10 CORE BLOCK DIAGRAM
Data Latch Address Latch
Address Latch Address Generator Units Controller
Program Memory Data Latch Latch Literal Data
Instruction Decode Control
Instruction Multiplier
Control Signals Various Blocks
Divide Support
Register Array
16-bit
Peripheral Modules
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FIGURE 3-2: PIC24HJXXXGPX06/X08/X10 PROGRAMMER'S MODEL
W0/WREG W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers
Shadow
PUSH.S Shadow
Legend
PC22 TBLPAG PSVPAG Data Table Page Address
Program Counter
Program Space Visibility Page Address RCOUNT REPEAT Loop Counter
CORCON
Core Configuration Register
IPL2 IPL1 IPL0
STATUS Register
Control Registers
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REGISTER 3-1:
R/W-0(1) Legend: Clear only only 15-9 Readable Writable cleared Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte sized data) low-order (for word sized data) result occurred carry-out from low-order (for byte sized data) low-order (for word sized data) result occurred IPL<2:0>: Interrupt Priority Level Status bits(2) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow This used signed arithmetic (2's complement). indicates overflow magnitude which causes sign change state. Overflow occurred signed arithmetic this arithmetic operation) overflow occurred Zero operation which affects some time past most recent operation which affects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant (MSb) result occurred carry-out from Most Significant result occurred Unimplemented bit, read Value unknown R/W-0(2) IPL<2:0>(2) R/W-0(2) R/W-0 R/W-0 R/W-0
STATUS REGISTER
R/W-0 R/W-0
Note IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read only when NSTDIS (INTCON1<15>).
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REGISTER 3-2:
Legend: Readable cleared 15-4 Clear only Writable unknown
CORCON: CORE CONTROL REGISTER
R/C-0 IPL3(1) R/W-0
Value Unimplemented bit, read
Unimplemented: Read IPL3: Interrupt Priority Level Status 3(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read
Note IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form interrupt priority level.
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Arithmetic Logic Unit (ALU)
3.4.2 DIVIDER
PIC24HJXXXGPX06/X08/X10 bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location. Refer "dsPIC30F/33F Programmer's Reference Manual" (DS70157) information bits affected each instruction. PIC24HJXXXGPX06/X08/X10 incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division. divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
3.4.3
MULTI-BIT DATA SHIFTER
multi-bit data shifter capable performing 16-bit arithmetic logic right shifts, 16-bit left shifts single cycle. source either working register memory location. shifter requires signed binary value determine both magnitude (number bits) direction shift operation. positive value shifts operand right. negative value shifts operand left. value does modify operand.
3.4.1
MULTIPLIER
Using high-speed 17-bit 17-bit multiplier, supports unsigned, signed mixed-sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
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Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Data Memory" (DS70237), which available from Microchip website (www.microchip.com).
Program Address Space
program address memory space PIC24HJXXXGPX06/X08/X10 devices instructions. space addressable 24-bit value derived from either 23-bit Program Counter (PC) during program execution, from table operation data space remapping described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (0x000000 0x7FFFFF). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24HJXXXGPX06/X08/X10 family devices shown Figure 4-1.
PIC24HJXXXGPX06/X08/X10 architecture features separate program data memory spaces buses. This architecture also allows direct access program memory from data space during code execution.
FIGURE 4-1:
PROGRAM MEMORY PIC24HJXXXGPX06/X08/X10 FAMILY DEVICES
PIC24HJ64XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ128XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ256XXXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
User Memory Space
User Program Flash Memory (22K instructions)
User Program Flash Memory (44K instructions)
User Program Flash Memory (88K instructions)
0x00ABFE 0x00AC00 0x0157FE 0x015800
Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's)
0x7FFFFE 0x800000 0x02ABFE 0x02AC00
Reserved Configuration Memory Space
Reserved
Reserved
Device Configuration Registers
Device Configuration Registers
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80010
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
0xFEFFFE 0xFF0000 0xFFFFFE
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4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT TRAP VECTORS
program memory space organized wordaddressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 4-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24HJXXXGPX06/X08/X10 devices reserve addresses between 0x00000 0x000200 hardcoded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 0x000000, with actual address start code 0x000002. PIC24HJXXXGPX06/X08/X10 devices also have interrupt vector tables, located from 0x000004 0x0000FF 0x000100 0x0001FF. These vector tables allow each many device interrupt sources handled separate Interrupt Service Routines (ISRs). more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
FIGURE 4-2:
Address 0x000001 0x000003 0x000005 0x000007
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 0x000000 0x000002 0x000004 0x000006 Address (lsw Address)
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Data Address Space
PIC24HJXXXGPX06/X08/X10 separate 16-bit wide data memory space. data space accessed using separate Address Generation Units (AGUs) read write operations. Data memory maps devices with different sizes shown Figure Figure 4-4. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This arrangement gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 4.4.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24HJXXXGPX06/X08/X10 devices implement Kbytes data memory. Should point location outside this area, all-zero word byte will returned. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap generated. error occurred read, instruction underway completed; occurred write, instruction will executed write does occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte (MSB) modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear Most Significant Byte register executing zero-extend (ZE) instruction appropriate address.
4.2.1
DATA SPACE WIDTH
4.2.3
SPACE
data memory space organized byte addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes each word have even addresses, while Most Significant Bytes have addresses.
first Kbytes Near Data Space, from 0x0000 0x07FF, primarily occupied Special Function Registers (SFRs). These used PIC24HJXXXGPX06/X08/X10 core peripheral modules controlling operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. complete listing implemented SFRs, including their addresses, shown Table through Table 4-33. Note: actual peripheral features interrupts varies device. Please refer corresponding device tables pinout diagrams device-specific information.
4.2.2
DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24HJXXXGPX06/X08/X10 instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through wordaligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word that contains byte, using Least Significant (LSb) determine which byte select. selected byte placed onto Least Significant Byte (LSB) data path. That data memory registers organized parallel byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register which matches byte address.
4.2.4
NEAR DATA SPACE
8-Kbyte area between 0x0000 0x1FFF referred Near Data Space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing mode with 16-bit address field, using Indirect Addressing mode using working register Address Pointer.
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FIGURE 4-3: DATA MEMORY PIC24HJXXXGPX06/X08/X10 DEVICES WITH
Address Kbyte Space 0x0001 Space 0x07FF 0x0801 0x07FE 0x0800 Kbyte Near Data Space Address 0x0000
bits
Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801
Data
0x1FFE 0x2000 0x27FE 0x2800
0x8001
0x8000
Optionally Mapped into Program Memory
Data Unimplemented
0xFFFF
0xFFFE
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FIGURE 4-4: DATA MEMORY PIC24HJXXXGPX06/X08/X10 DEVICES WITH
Address Kbyte Space 0x0001 Space 0x07FF 0x0801 Address 0x0000 0x07FE 0x0800 Kbyte Near Data Space
bits
0x1FFF Data Kbyte SRAM Space 0x3FFF 0x4001 0x47FF 0x4801
0x1FFE
0x3FFE 0x4000 0x47FE 0x4800
0x8001
0x8000
Data Unimplemented Optionally Mapped into Program Memory
0xFFFF
0xFFFE
4.2.5
Every PIC24HJXXXGPX06/X08/X10 device contains Kbytes dual ported located data space. Memory locations space accessible simultaneously controller module. utilized controller store data transferred various peripherals using DMA, well data transferred from
various peripherals using DMA. accessed controller without having steal cycles from CPU. When controller attempt concurrently write same location, hardware ensures that given precedence accessing location. Therefore, provides reliable means transferring data without ever having stall CPU. Note: used general purpose data storage function required application.
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TABLE 4-1:
Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT BSRAM SSRAM Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 0750 0752
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL<2:0> IPL3 IW_BSR IW_SSR IR_BSR IR_SSR RL_BSR RL_SSR 0000 0000 0000 xxxx 0000 0000 xxxx 0000 0000
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Register Program Counter Word Register
Repeat Loop Counter Register
Disable Interrupts Counter Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
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TABLE 4-2:
Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJXXXGPX10 DEVICES
CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN9PUE CN8IE CN8PUE CN7IE CN23IE CN7PUE CN6IE CN22IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN20IE CN4PUE CN3IE CN19IE CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-3:
Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJXXXGPX08 DEVICES
CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN9PUE CN8IE CN8PUE CN7IE CN7PUE CN6IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN20IE CN4PUE CN3IE CN19IE CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
PIC24HJXXXGPX06/X08/X10
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-4:
Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJXXXGPX06 DEVICES
CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN9PUE CN8IE CN8PUE CN7IE CN7PUE CN6IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN20IE CN4PUE CN3IE CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CN21PUE CN20PUE
CN18PUE CN17PUE CN16PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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TABLE 4-5:
Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC14 IPC15 IPC16 IPC17 INTTREG Legend: Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C0 00C2 00C4 00C6 00E0
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT U2TXIF T6IF U2TXIE T6IE DISI DMA1IF U2RXIF DMA4IF DMA1IE U2RXIE DMA4IE AD1IF INT2IF DMA5IF AD1IE INT2IE DMA5IE T1IP<2:0> T2IP<2:0> U1RXIP<2:0> CNIP<2:0> IC8IP<2:0> T4IP<2:0> U2TXIP<2:0> C1IP<2:0> IC5IP<2:0> OC7IP<2:0> T6IP<2:0> T8IP<2:0> C2RXIP<2:0> C2TXIP<2:0> U1TXIF T5IF OC8IF U1TXIE T5IE OC8IE U1RXIF T4IF OC7IF U1RXIE T4IE OC7IE OC4IF OC6IF OC4IE OC6IE OC3IF OC5IF OC3IE OC5IE OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> IC7IP<2:0> OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0> IC4IP<2:0> OC6IP<2:0> DMA4IP<2:0> MI2C2IP<2:0> INT4IP<2:0> U2EIP<2:0> C1TXIP<2:0> ILR<3:0> T3IF DMA2IF IC6IF C2IF T3IE DMA2IE IC6IE C2IE T2IF IC8IF IC5IF C2RXIF C2TXIF T2IE IC8IE IC5IE C2RXIE C2TXIE OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF IC1IE SPI2IE SI2C2IE U1EIE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> IC6IP<2:0> OC8IP<2:0> T7IP<2:0> T9IP<2:0> C2IP<2:0> DMA6IP<2:0> INT0EP INT0IF SI2C1IF SPI2EIF T7IF INT0IE SPI2EIE T7IE Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4044 4444 4444 4444 4444 4444 4444 4404 4444 4444 0004 0040 0440 4444 0000
DIV0ERR DMACERR MATHERR ADDRERR STKERR OC2IF IC7IF IC4IF INT4IF C1TXIF OC2IE IC7IE IC4IE INT4IE C1TXIE IC2IF AD2IF IC3IF INT3IF DMA7IF IC2IE AD2IE IC3IE INT3IE DMA7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> AD1IP<2:0> MI2C1IP<2:0> AD2IP<2:0> OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> OC5IP<2:0> SI2C2IP<2:0> INT3IP<2:0> DMA5IP<2:0> U1EIP<2:0> DMA7IP<2:0> INT4EP DMA0IF INT1IF DMA3IF T9IF DMA6IF DMA0IE INT1IE DMA3IE T9IE DMA6IE INT3EP T1IF CNIF C1IF T8IF T1IE CNIE C1IE T8IE VECNUM<6:0> INT2EP OC1IF C1RXIF MI2C2IF U2EIF OC1IE C1RXIE MI2C2IE U2EIE
SPI1IF SPI1EIF
SPI1IE SPI1EIE
MI2C1IE SI2C1IE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-6:
Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON TMR4 TMR5HLD TMR5 T4CON T5CON TMR6 TMR7HLD TMR7 T6CON T7CON TMR8 TMR9HLD TMR9 T8CON T9CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 0122 0124 0126 0128 012A 012C 012E 0130 0132 0134 0136 0138 013A 013C
TIMER REGISTER
Resets xxxx FFFF TGATE TCKPS<1:0> TSYNC 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> 0000 0000 xxxx
Timer1 Register Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TSIDL
Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS<1:0> TCKPS<1:0>
PIC24HJXXXGPX06/X08/X10
xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF
Timer6 Register Timer7 Holding Register (for 32-bit operations only) Timer7 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS<1:0> TCKPS<1:0>
0000 0000 xxxx xxxx xxxx FFFF FFFF
Timer8 Register Timer9 Holding Register (for 32-bit operations only) Timer9 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS<1:0> TCKPS<1:0>
0000 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 4-7:
Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON IC6BUF IC6CON IC7BUF IC7CON IC8BUF IC8CON Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E
INPUT CAPTURE REGISTER
Resets xxxx ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICOV ICOV ICOV ICOV ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000
Input Capture Register ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR Input Capture Register Input Capture Register Input Capture Register Input Capture Register Input Capture Register Input Capture Register Input Capture Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-8:
Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON OC6RS OC6R OC6CON OC7RS OC7R OC7CON OC8RS OC8R OC8CON Legend: Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE
OUTPUT COMPARE REGISTER
Resets xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0>
Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM<2:0> Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM<2:0> Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM<2:0> Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM<2:0>
PIC24HJXXXGPX06/X08/X10
0000 xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 4-9:
Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2C1 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-10:
Name I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Addr 0210 0212 0214 0216 0218 021A 021C
I2C2 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-11:
Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228
UART1 REGISTER
UARTEN UTXISEL1 UTXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN URXINV RIDLE BRGH PERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
PDSEL<1:0> FERR OERR
URXISEL<1:0>
UART Transmit Register UART Receive Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-12:
Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0230 0232 0234 0236 0238
UART2 REGISTER
UARTEN UTXISEL1 UTXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN URXINV RIDLE BRGH PERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
PDSEL<1:0> FERR OERR
URXISEL<1:0>
UART Transmit Register UART Receive Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-13:
Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: Addr 0240 0242 0244 0248
SPI1 REGISTER
SPIEN FRMEN SPIFSD SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF Resets 0000 0000 0000 0000
PIC24HJXXXGPX06/X08/X10
PPRE<1:0>
SPI1 Transmit Receive Buffer Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-14:
Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0260 0262 0264 0268
SPI2 REGISTER
SPIEN FRMEN SPIFSD SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF Resets 0000 0000 0000 0000
PPRE<1:0>
SPI2 Transmit Receive Buffer Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 4-15:
File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGH(1) AD1PCFGL AD1CSSH(1) AD1CSSL AD1CON4 Reserved Legend: Note Addr 0300 0320 0322 0324 0326 0328 032A 032C 032E 0330 0332
ADC1 REGISTER
Resets xxxx SSRC<2:0> BUFS CH0NA PCFG24 PCFG8 CSS24 CSS8 PCFG23 PCFG7 CSS23 CSS7 PCFG9 CSS25 CSS9 PCFG22 PCFG6 CSS22 CSS6 PCFG21 PCFG5 CSS21 CSS5 PCFG20 PCFG4 CSS20 CSS4 PCFG3 CSS19 CSS3 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<4:0> PCFG19 PCFG18 PCFG17 PCFG2 CSS18 CSS2 PCFG1 CSS17 CSS1 DMABL<2:0> PCFG16 PCFG0 CSS16 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB
Data Buffer ADON ADRC CH0NB VCFG<2:0> PCFG29 PCFG13 CSS29 CSS13 PCFG28 PCFG12 CSS28 CSS12 ADSIDL ADDMABM AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> PCFG27 PCFG26 PCFG25 PCFG11 PCFG10 CSS27 CSS11 CSS26 CSS10 FORM<1:0> CHPS<1:0>
PCFG31 PCFG30 PCFG15 PCFG14 CSS31 CSS15 CSS30 CSS14
0334033E
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. inputs available devices. device diagrams available inputs.
TABLE 4-16:
File Name ADC2BUF0 AD2CON1 AD2CON2 AD2CON3 AD2CHS123 AD2CHS0 Reserved AD2PCFGL Reserved AD2CSSL AD2CON4 Reserved Legend: Addr 0340 0360 0362 0364 0366 0368 036A 036C 036E 0370 0372 0374037E
ADC2 REGISTER
Resets xxxx SSRC<2:0> BUFS CH0NA PCFG8 CSS8 PCFG7 CSS7 PCFG6 CSS6 PCFG5 CSS5 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<3:0> PCFG3 CSS3 PCFG2 CSS2 PCFG1 CSS1 DMABL<2:0> PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB PCFG4 CSS4
Data Buffer ADON ADRC CH0NB CSS15 VCFG<2:0> CSS14 PCFG13 CSS13 PCFG12 CSS12 CSS11 ADSIDL ADDMABM AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<3:0> CSS10 PCFG9 CSS9 PCFG11 PCFG10 FORM<1:0> CHPS<1:0>
PCFG15 PCFG14
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-17:
File Name Addr DMA0CON 0380 DMA0REQ 0382 DMA0STA DMA0STB DMA0PAD DMA0CNT 0384 0386 0388 038A
REGISTER
CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> IRQSEL<6:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
AMODE<1:0>
MODE<1:0>
DMA1CON 038C DMA1REQ 038E DMA1STA DMA1STB DMA1PAD DMA1CNT 0390 0392 0394 0396
PIC24HJXXXGPX06/X08/X10
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DMA2CON 0398 DMA2REQ 039A DMA2STA DMA2STB DMA2PAD DMA2CNT 039C 039E 03A0 03A2
DMA3CON 03A4 DMA3REQ 03A6 DMA3STA DMA3STB DMA3PAD 03A8 03AA 03AC
DMA3CNT 03AE DMA4CON 03B0 DMA4REQ 03B2 DMA4STA DMA4STB DMA4PAD 03B4 03B6 03B8
DMA4CNT 03BA DMA5CON 03BC DMA5REQ 03BE DMA5STA DMA5STB Legend: 03C0 03C2
unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-17:
File Name Addr DMA5PAD 03C4
REGISTER (CONTINUED)
PAD<15:0> CHEN SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> XWCOL7 PPST7 DSADR<15:0> LSTCH<3:0> PPST6 CNT<9:0> XWCOL6 XWCOL5 PPST5 XWCOL4 PPST4 XWCOL3 PPST3 XWCOL2 PPST2 XWCOL1 XWCOL0 PPST1 PPST0 CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
DMA5CNT 03C6 DMA6CON 03C8 DMA6STA DMA6STB DMA6PAD 03CC 03CE 03D0
DMA6REQ 03CA FORCE
DMA6CNT 03D2 DMA7CON 03D4 DMA7REQ 03D6 DMA7STA DMA7STB 03D8 03DA
DMA7PAD 03DC DMA7CNT 03DE DMACS0 DMACS1 DSADR Legend: 03E2 03E4
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-18:
File Name C1CTRL1 C1CTRL2 C1VEC C1FCTRL C1FIFO C1INTF C1INTE C1EC C1CFG1 C1CFG2 C1FEN1 Addr 0400 0402 0404 0406 0408 040A 040C 040E 0410 0412
ECAN1 REGISTER WHEN C1CTRL1.WIN PIC24HJXXXGP506/510/610 DEVICES ONLY
DMABS<2:0> WAKFIL TXBO TXBP CSIDL FBP<5:0> RXBP F5MSK<1:0> F13MSK<1:0> TXWAR RXWAR SEG2PH<2:0> FLTEN9 FLTEN8 F4MSK<1:0> F12MSK<1:0> EWARN ABAT FILHIT<4:0> REQOP<2:0> IVRIF IVRIE WAKIF WAKIE ERRIF ERRIE FIFOIF FIFOIE OPMODE<2:0> CANCAP ICODE<6:0> FSA<4:0> FNRB<5:0> RBOVIF RBOVIE RBIF RBIE TBIF TBIE Resets 0480 0000 0000 0000 0000 0000 0000 0000 0000 PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 F1MSK<1:0> F9MSK<1:0> F0MSK<1:0> F8MSK<1:0> 0000 FFFF
DNCNT<4:0>
TERRCNT<7:0> SJW<1:0> SEG2PHTS FLTEN7 FLTEN6
RERRCNT<7:0> BRP<5:0> SEG1PH<2:0> FLTEN5 FLTEN4 FLTEN3 F2MSK<1:0> F10MSK<1:0>
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 F7MSK<1:0> F15MSK<1:0> F6MSK<1:0> F14MSK<1:0>
C1FMSKSEL1 0418 C1FMSKSEL2 041A Legend:
F3MSK<1:0> F11MSK<1:0>
PIC24HJXXXGPX06/X08/X10
0000 0000
unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-19:
File Name Addr 0400041E C1RXFUL1 C1RXFUL2 C1RXOVF1 C1RXOVF2 C1TR01CO C1TR23CO C1TR45CO C1TR67CO C1RXD C1TXD Legend:
ECAN1 REGISTER WHEN C1CTRL1.WIN PIC24HJXXXGP506/510/610 DEVICES ONLY
Resets
definition when RXFUL8 RXOVF8 RXFUL7 RXOVF7 TXEN0 TXEN2 TXEN4 TXEN6 RXFUL6 RXOVF6 ABAT0 ABAT2 ABAT4 ABAT6 RXFUL5 RXOVF5 LARB0 LARB2 LARB4 LARB6 RXFUL4 RXOVF4 ERR0 ERR2 ERR4 ERR6 RXFUL3 RXOVF3 REQ0 REQ2 REQ4 REQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 0430 0432 0434 0436 0440 0442 TXEN1 TXEN3 TXEN5 TXEN7 ABT1 ABT3 ABT5 ABT7 LARB1 LARB3 LARB5 LARB7 ERR1 ERR3 ERR5 ERR7 REQ1 REQ3 REQ5 REQ7 RTREN1 RTREN3 RTREN5 RTREN7
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> TX7PRI<1:0> TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0>
Recieved Data Word Transmit Data Word
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-20:
File Name
ECAN1 REGISTER WHEN C1CTRL1.WIN PIC24HJXXXGP506/510/610 DEVICES ONLY
Resets
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Addr 0400041E
definition when F3BP<3:0> F7BP<3:0> F11BP<3:0> F15BP<3:0> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> F2BP<3:0> F6BP<3:0> F10BP<3:0> F14BP<3:0> F1BP<3:0> F5BP<3:0> F9BP<3:0> F13BP<3:0> SID<2:0> MIDE MIDE MIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EID<7:0> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> F0BP<3:0> F4BP<3:0> F8BP<3:0> F12BP<3:0> EID<17:16> 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
C1BUFPNT1 C1BUFPNT2 C1BUFPNT3 C1BUFPNT4 C1RXM0SID C1RXM0EID C1RXM1SID C1RXM1EID C1RXM2SID C1RXM2EID C1RXF0SID C1RXF0EID C1RXF1SID C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID C1RXF6SID C1RXF6EID C1RXF7SID C1RXF7EID C1RXF8SID C1RXF8EID C1RXF9SID C1RXF9EID C1RXF10SID C1RXF10EID C1RXF11SID Legend:
0420 0422 0424 0426 0430 0432 0434 0436 0438 043A 0440 0442 0444 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 046A 046C
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-20:
File Name C1RXF11EID C1RXF12SID C1RXF12EID C1RXF13SID C1RXF13EID C1RXF14SID C1RXF14EID C1RXF15SID C1RXF15EID Legend:
ECAN1 REGISTER WHEN C1CTRL1.WIN PIC24HJXXXGP506/510/610 DEVICES ONLY (CONTINUED)
Resets xxxx EID<17:16> EID<17:16> EID<17:16> EID<17:16> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
2009 Microchip Technology Inc. DS70175H-page
Addr 046E 0470 0472 0474 0476 0478 047A 047C 047E
EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<2:0> SID<2:0> SID<2:0> SID<2:0>
EID<7:0> EXIDE EXIDE EXIDE EXIDE EID<7:0> EID<7:0> EID<7:0> EID<7:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
PIC24HJXXXGPX06/X08/X10
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
TABLE 4-21:
File Name C2CTRL1 C2CTRL2 C2VEC C2FCTRL C2FIFO C2INTF C2INTE C2EC C2CFG1 C2CFG2 C2FEN1 C2FMSKSEL1 C2FMSKSEL2 Legend: Addr 0500 0502 0504 0506 0508 050A 050C 050E 0510 0512 0514 0518 051A
ECAN2 REGISTER WHEN C2CTRL1.WIN PIC24HJ256GP610 DEVICES ONLY
FLTEN15 DMABS<2:0> WAKFIL FLTEN14 TXBO FLTEN13 TXBP FLTEN12 CSIDL FBP<5:0> RXBP FLTEN11 F5MSK<1:0> F13MSK<1:0> TXWAR RXWAR EWARN SEG2PH<2:0> FLTEN10 FLTEN9 FLTEN8 F4MSK<1:0> F12MSK<1:0> ABAT FILHIT<4:0> REQOP<2:0> IVRIF IVRIE WAKIF WAKIE ERRIF ERRIE FIFOIF FIFOIE CANCAP ICODE<6:0> FSA<4:0> FNRB<5:0> RBOVIF RBOVIE RBIF RBIE TBIF TBIE Resets 0480 0000 0000 0000 0000 0000 0000 0000 0000 PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 F1MSK<1:0> F9MSK<1:0> F0MSK<1:0> F8MSK<1:0> 0000 FFFF 0000 0000
OPMODE<2:0>
DNCNT<4:0>
TERRCNT<7:0> SJW<1:0> SEG2PHTS FLTEN7
RERRCNT<7:0> BRP<5:0> SEG1PH<2:0> F2MSK<1:0> F10MSK<1:0>
FLTEN6 FLTEN5 FLTEN4 FLTEN3
F7MSK<1:0> F15MSK<1:0>
F6MSK<1:0> F14MSK<1:0>
F3MSK<1:0> F11MSK<1:0>
unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-22:
File Name Addr 0500051E C2RXFUL1 C2RXFUL2 C2RXOVF1 C2RXOVF2
ECAN2 REGISTER WHEN C2CTRL1.WIN PIC24HJ256GP610 DEVICES ONLY
Resets
definition when RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXOVF6 ABAT0 ABAT2 ABAT4 ABAT6 RXFUL5 RXOVF5 LARB0 LARB2 LARB4 LARB6 RXFUL4 RXOVF4 ERR0 ERR2 ERR4 ERR6 RXFUL3 RXOVF3 REQ0 REQ2 REQ4 REQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 TXEN1 TXEN3 TXEN5 TXEN7 ABAT1 ABAT3 ABAT5 ABAT7 LARB1 LARB3 LARB5 LARB7 ERR1 ERR3 ERR5 ERR7 REQ1 REQ3 REQ5 REQ7 RTREN1 RTREN3 RTREN5 RTREN7 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> TX7PRI<1:0> TXEN0 TXEN2 TXEN4 TXEN6 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0>
C2TR01CON 0530 C2TR23CON 0532 C2TR45CON 0534 C2TR67CON 0536 C2RXD C2TXD Legend: 0540 0542
Recieved Data Word Transmit Data Word
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-23:
File Name
ECAN2 REGISTER WHEN C2CTRL1.WIN PIC24HJ256GP610 DEVICES ONLY
Addr 0500051E Resets
definition when F3BP<3:0> F7BP<3:0> F12BP<3:0> F15BP<3:0> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> F2BP<3:0> F6BP<3:0> F10BP<3:0> F14BP<3:0> F1BP<3:0> F5BP<3:0> F9BP<3:0> F13BP<3:0> SID<2:0> MIDE MIDE MIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EID<7:0> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> F0BP<3:0> F4BP<3:0> F8BP<3:0> F12BP<3:0> EID<17:16> 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
C2BUFPNT1 C2BUFPNT2 C2BUFPNT3 C2BUFPNT4 C2RXM0SID C2RXM0EID C2RXM1SID C2RXM1EID C2RXM2SID C2RXM2EID C2RXF0SID C2RXF0EID C2RXF1SID C2RXF1EID C2RXF2SID C2RXF2EID C2RXF3SID C2RXF3EID C2RXF4SID C2RXF4EID C2RXF5SID C2RXF5EID C2RXF6SID C2RXF6EID C2RXF7SID C2RXF7EID C2RXF8SID C2RXF8EID C2RXF9SID C2RXF9EID C2RXF10SID C2RXF10EID C2RXF11SID Legend:
0520 0522 0524 0526 0530 0532 0534 0536 0538 053A 0540 0542 0544 0546 0548 054A 054C 054E 0550 0552 0554 0556 0558 055A 055C 055E 0560 0562 0564 0566 0568 056A 056C
PIC24HJXXXGPX06/X08/X10
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-23:
File Name C2RXF11EID C2RXF12SID C2RXF12EID C2RXF13SID C2RXF13EID C2RXF14SID C2RXF14EID C2RXF15SID C2RXF15EID Legend:
ECAN2 REGISTER WHEN C2CTRL1.WIN PIC24HJ256GP610 DEVICES ONLY (CONTINUED)
Addr 056E 0570 0572 0574 0576 0578 057A 057C 057E Resets xxxx EID<17:16> EID<17:16> EID<17:16> EID<17:16> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<2:0> SID<2:0> SID<2:0> SID<2:0>
EID<7:0> EXIDE EXIDE EXIDE EXIDE EID<7:0> EID<7:0> EID<7:0> EID<7:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 4-24:
File Name TRISA PORTA LATA ODCA Legend: Note Addr 02C0 02C2 02C4 06C0
PORTA REGISTER MAP(1)
TRISA15 RA15 LATA15 ODCA15 TRISA14 RA14 LATA14 ODCA14 TRISA13 RA13 LATA13 TRISA12 RA12 LATA12 TRISA10 RA10 LATA10 TRISA9 LATA9 TRISA7 LATA7 TRISA6 LATA6 TRISA5 LATA5 ODCA5 TRISA4 LATA4 ODCA4 TRISA3 LATA3 ODCA3 TRISA2 LATA2 ODCA2 TRISA1 LATA1 ODCA1 TRISA0 LATA0 ODCA0 Resets F6FF xxxx xxxx 0000
2009 Microchip Technology Inc. DS70175H-page
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-25:
File Name TRISB PORTB LATB Legend: Note Addr 02C6 02C8 02CA
PORTB REGISTER MAP(1)
TRISB15 RB15 LATB15 TRISB14 RB14 LATB14 TRISB13 RB13 LATB13 TRISB12 RB12 LATB12 TRISB11 RB11 LATB11 TRISB10 RB10 LATB10 TRISB9 LATB9 TRISB8 LATB8 TRISB7 LATB7 TRISB6 LATB6 TRISB5 LATB5 TRISB4 LATB4 TRISB3 LATB3 TRISB2 LATB2 TRISB1 LATB1 TRISB0 LATB0 Resets FFFF
PIC24HJXXXGPX06/X08/X10
xxxx xxxx
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-26:
File Name TRISC PORTC LATC Legend: Note Addr 02CC 02CE 02D0
PORTC REGISTER MAP(1)
TRISC4 LATC4 TRISC3 LATC3 TRISC2 LATC2 TRISC1 LATC1 Resets F01E xxxx xxxx
TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 RC14 LATC14 RC13 LATC13 RC12 LATC12
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-27:
File Name TRISD PORTD LATD ODCD Legend: Note Addr 02D2 02D4 02D6 06D2
PORTD REGISTER MAP(1)
TRISD15 RD15 LATD15 ODCD15 TRISD14 RD14 LATD14 ODCD14 TRISD13 RD13 LATD13 ODCD13 TRISD12 RD12 LATD12 ODCD12 TRISD11 RD11 LATD11 ODCD11 TRISD10 RD10 LATD10 ODCD10 TRISD9 LATD9 ODCD9 TRISD8 LATD8 ODCD8 TRISD7 LATD7 ODCD7 TRISD6 LATD6 ODCD6 TRISD5 LATD5 ODCD5 TRISD4 LATD4 ODCD4 TRISD3 LATD3 ODCD3 TRISD2 LATD2 ODCD2 TRISD1 LATD1 ODCD1 TRISD0 LATD0 ODCD0 Resets FFFF xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-28:
File Name TRISE PORTE LATE Legend: Note Addr 02D8 02DA 02DC
PORTE REGISTER MAP(1)
TRISE7 LATE7 TRISE6 LATE6 TRISE5 LATE5 TRISE4 LATE4 TRISE3 LATE3 TRISE2 LATE2 TRISE1 LATE1 TRISE0 LATE0 Resets 00FF xxxx xxxx
DS70175H-page 2009 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-29:
File Name TRISF PORTF LATF ODCF(2) Legend: Note Addr 02DE 02E0 02E2 06DE
PORTF REGISTER MAP(1)
TRISF13 RF13 LATF13 ODCF13 TRISF12 RF12 LATF12 ODCF12 TRISF8 LATF8 ODCF8 TRISF7 LATF7 ODCF7 TRISF6 LATF6 ODCF6 TRISF5 LATF5 ODCF5 TRISF4 LATF4 ODCF4 TRISF3 LATF3 ODCF3 TRISF2 LATF2 ODCF2 TRISF1 LATF1 ODCF1 TRISF0 LATF0 ODCF0 Resets 31FF xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
TABLE 4-30:
File Name TRISG PORTG LATG ODCG(2) Legend: Note Addr 02E4 02E6 02E8 06E4
PORTG REGISTER MAP(1)
TRISG15 RG15 LATG15 ODCG15 TRISG14 RG14 LATG14 ODCG14 TRISG13 RG13 LATG13 ODCG13 TRISG12 RG12 LATG12 ODCG12 TRISG9 LATG9 ODCG9 TRISG8 LATG8 ODCG8 TRISG7 LATG7 ODCG7 TRISG6 LATG6 ODCG6 TRISG3 LATG3 ODCG3 TRISG2 LATG2 ODCG2 TRISG1 LATG1 ODCG1 TRISG0 LATG0 ODCG0 Resets F3CF xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. actual port pins varies from device another. Please refer corresponding pinout diagrams.
2009 Microchip Technology Inc. DS70175H-page
TABLE 4-31:
File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note Addr 0740 0742 0744 0746 0748
SYSTEM CONTROL REGISTER
TRAPR IOPUWR COSC<2:0> DOZE<2:0> DOZEN NOSC<2:0> FRCDIV<2:0> VREGS EXTR CLKLOCK SWDTEN LOCK PLLDIV<8:0> TUN<5:0> WDTO SLEEP IDLE PLLPRE<4:0> LPOSCEN OSWEN Resets xxxx(1) 0300(2) 3040 0030 0000
PLLPOST<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. RCON register Reset values dependent type Reset. OSCCON register Reset values dependent FOSC Configuration bits type Reset.
TABLE 4-32:
File Name NVMCON NVMKEY Legend: Note Addr 0760 0766
REGISTER
WREN WRERR ERASE NVMKEY<7:0> Resets 0000(1) 0000
PIC24HJXXXGPX06/X08/X10
NVMOP<3:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 4-33:
File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774
REGISTER
T5MD IC8MD T9MD T4MD IC7MD T8MD T3MD IC6MD T7MD T2MD IC5MD T6MD T1MD IC4MD IC3MD IC2MD IC1MD I2C1MD OC8MD U2MD OC7MD U1MD OC6MD SPI2MD OC5MD SPI1MD OC4MD C2MD OC3MD C1MD OC2MD I2C2MD AD1MD OC1MD AD2MD Resets 0000 0000 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
PIC24HJXXXGPX06/X08/X10
4.2.6 SOFTWARE STACK 4.2.7 DATA PROTECTION FEATURE
addition working register, register PIC24HJXXXGPX06/X08/X10 devices also used software Stack Pointer. Stack Pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 4-5. push during CALL instruction, zeroextended before push, ensuring that always clear. Note: push during exception processing concatenates register prior push. PIC24H product family supports Data protection features that enable segments protected when used conjunction with Boot Secure Code Segment Security. BSRAM (Secure segment accessible only from Boot Segment Flash code, when enabled. SSRAM (Secure segment RAM) accessible only from Secure Segment Flash code, when enabled. Table overview BSRAM SSRAM SFRs.
Instruction Addressing Modes
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 0x2000 RAM, initialize SPLIM with value 0x1FFE. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0x0800. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
addressing modes Table 4-34 form basis addressing modes optimized support specific features individual instructions. addressing modes provided class instructions somewhat different from those other instruction types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions 13-bit address field directly address data present first 8192 bytes data memory (Near Data Space). Most file register instructions employ working register, which denoted WREG these instructions. destination typically either same file register WREG (with exception instruction), which writes result register register pair. instruction allows additional flexibility access entire data space.
4.3.2
INSTRUCTIONS
3-operand instructions form: Operand Operand <function> Operand where Operand always working register (i.e., addressing mode only Register Direct) which referred Operand register, fetched from data memory, 5-bit literal. result location either register data memory location. following addressing modes supported instructions: Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit 10-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
FIGURE 4-5:
0x0000
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
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TABLE 4-34: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description address file register specified explicitly. contents register accessed directly. contents forms contents forms post-modified (incremented decremented) constant value. pre-modified (incremented decremented) signed constant value form literal forms Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified
Register Indirect with Register Offset forms Register Indirect with Literal Offset
4.3.3
MOVE INSTRUCTIONS
Move instructions provide greater degree addressing flexibility than other instructions. addition Addressing modes supported most instructions, move instructions also support Register Indirect with Register Offset Addressing mode, also referred Register Indexed mode. Note: instructions, Addressing mode specified instruction differ source destination However, 4-bit (Register Offset) field shared between both source destination (but typically only used one).
Interfacing Program Data Memory Spaces
PIC24HJXXXGPX06/X08/X10 architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24HJXXXGPX06/X08/X10 architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This capability makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. only access least significant word program word.
summary, following Addressing modes supported move instructions: Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: instructions support Addressing modes given above. Individual instructions support different subsets these Addressing modes.
4.4.1
ADDRESSING PROGRAM SPACE
4.3.4
OTHER INSTRUCTIONS
Besides various addressing modes outlined above, some instructions literal constants various sizes. example, (branch) instructions 16-bit signed literals specify branch destination directly, whereas DISI instruction uses 14-bit unsigned literal field. some instructions, source operand result implied opcode itself. Certain operations, such NOP, have operands.
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7>
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PIC24HJXXXGPX06/X08/X10
remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 4-35 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
TABLE 4-35:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Address <23> 0xxx xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1>
Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Program Space Visibility (Block Remap/Read) Note
User
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
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FIGURE 4-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2)
TBLPAG bits bits bits
Select Program Space Visibility(1) (Remapping) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
2009 Microchip Technology Inc.
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PIC24HJXXXGPX06/X08/X10
4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom byte', will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper `phantom' byte selected (Byte Select similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space.
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit, word wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when Byte Select `1'; lower byte selected when `0'.
FIGURE 4-7:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
0x000000
00000000
00000000 00000000 00000000
0x020000 0x030000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
0x800000
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4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space location used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This option provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 4-8), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions require instruction cycle addition specified execution time. other instructions require instruction cycles addition specified execution time. operations that PSV, which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 4-8:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 0x000000 0x010000 0x018000 data page designated PSVPAG mapped into upper half data memory space.
Data Space
0x0000 Data EA<14:0>
0x8000
Area .while lower bits specify exact address within 0xFFFF area. This corresponds exactly same lower bits actual program space address.
0x800000
2009 Microchip Technology Inc.
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FLASH PROGRAM MEMORY
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Flash Programming" (DS70228), which available from Microchip website (www.microchip.com).
signal controller just before shipping product. This also allows most recent firmware custom firmware programmed. RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data either blocks `rows' instructions (192 bytes) time, single instructions erase program memory blocks `pages' instructions (1536 bytes) time.
PIC24HJXXXGPX06/X08/X10 devices contain internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed ways: In-Circuit Serial Programming(ICSPTM) programming capability Run-Time Self-Programming (RTSP)
Table Instructions Flash Programming
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using bits<7:0> TBLPAG register Effective Address (EA) from register specified table instruction, shown Figure 5-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
ICSP programming capability allows PIC24HJXXXGPX06/X08/X10 device serially programmed while application circuit. This simply done with lines programming clock programming data (one alternate programming pairs: PGECx/PGEDx, three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program digital
FIGURE 5-1:
ADDRESSING TABLE REGISTERS
bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG bits bits
User/Configuration Space Select
24-bit
Byte Select
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RTSP Operation Programming Operations
PIC24HJXXXGPX06/X08/X10 Flash program memory array organized into rows instructions bytes. RTSP allows user erase page memory, which consists eight rows (512 instructions) time, program word time. Table 24-12 displays typical erase programming times. 8-row erase pages single write rows edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. program memory implements holding buffers that contain instructions programming data. Prior actual programming operation, write data must loaded into buffers sequential order. instruction words loaded must always from group boundary. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. total TBLWTL TBLWTH instructions required load instructions. table write operations single-word writes (two instruction cycles) because only buffers written. programming cycle required programming each row. complete programming sequence necessary programming erasing internal Flash RTSP mode. processor stalls (waits) until programming operation finished. programming time depends accuracy (see Table 24-19) value Oscillator Tuning register (see Register 9-4). following formula calculate minimum maximum values Write Time, Page Erase Time Word Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1:
PROGRAMMING TIME
-7.37 Accuracy Tuning example, device operating +85°C, accuracy will ±2%. TUN<5:0> bits (see Register 9-4) `b111111, Minimum Write Time 11064 Cycles 1.48ms 7.37 0.02 0.00375 and, Maximum Write Time 11064 Cycles 1.54ms 7.37 0.02 0.00375 Setting (NVMCON<15>) starts operation, automatically cleared when operation finished.
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 5-1) controls which blocks erased, which memory type programmed start programming cycle. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write 0x55 0xAA NVMKEY register. Refer Section "Programming Operations" further details.
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REGISTER 5-1:
R/SO-0(1) Legend: Readable Value Settable only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) R/W-0(1) R/W-0(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WREN R/W-0(1) WRERR R/W-0(1)
NVMOP<3:0>
Write Control Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(2) 1111 Memory bulk erase operation (ERASE operation (ERASE 1110 Reserved 1101 Erase General Segment Configuration Register (ERASE operation (ERASE 1100 Erase Secure Segment Configuration Register (ERASE operation (ERASE 1011-0100 Reserved 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE 0000 Program erase single Configuration register byte
12-7
Note These bits only reset POR. other combinations NVMOP<3:0> unimplemented.
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5.4.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program program Flash memory time. this, necessary erase 8-row erase page that contains desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase page (see Example 5-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address page erased into TBLPAG registers. Perform dummy table write operation (TBLWTL) address within page that needs erased. Write 0x55 NVMKEY. Write 0xAA NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 5-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write 0x55 NVMKEY. Write 0xAA NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 5-3.
EXAMPLE 5-1:
ERASING PROGRAM MEMORY PAGE
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA<15:0> pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
Note:
program memory page erase operation performing dummy table write (TBLWTL) operation address within page. This methodology different from page erase operation dsPIC30F/33F devices which erase page selected using dedicated pair registers (NVMADRU NVMADR).
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EXAMPLE 5-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch
EXAMPLE 5-3:
DISI BSET
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
#0x55, NVMKEY #0xAA, NVMKEY NVMCON,
2009 Microchip Technology Inc.
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RESET
This data sheet summarizes features PIC24HJXXXGPX06/X08/X10 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Reset" (DS70229), which available from Microchip website (www.microchip.com).
active source Reset will make SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets. Note: Refer specific peripheral section this manual register Reset states.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Reset SWR: RESET Instruction WDT: Watchdog Timer Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Uninitialized Register Reset
types device Reset will corresponding status RCON register indicate type Reset (see Register 6-1). will clear bits, except (RCON<0>), that set. user clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software does cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
simplified block diagram Reset module shown Figure 6-1.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter MCLR Module Sleep Idle SYSRST
Internal Regulator Rise Detect
Trap Conflict Illegal Opcode Uninitialized Register
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REGISTER 6-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 VREGS R/W-1
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read VREGS: Voltage Regulator Standby During Sleep Voltage regulator active during Sleep Voltage regulator goes into Standby mode during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake-up from Sleep Flag Device been Sleep mode Device been Sle
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