CMOS SyncBiFIFO256 IDT72605 IDT72615 Integrated Device Techn
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IDT72605/IDT72615 CMOS SyncBiFIFO
CMOS SyncBiFIFO256
IDT72605 IDT72615
Integrated Device Technology, Inc.
FEATURES:
independent FIFO memories fully bidirectional data transfers organization (IDT 72605) organization (IDT 72615) Synchronous interface fast (20ns) read write cycle times Each data port independent clock read/write control Output enable provided each port three-state control data Built-in bypass path direct data transfer between ports fixed flags, Empty Full, both A-to-B B-to-A FIFO Programmable flag offset depth FIFO synchronous BiFIFO packaged 64-pin TQFP (Thin Quad Flatpack), 68-pin 68-pin PLCC
DESCRIPTION:
IDT72605 IDT72615 very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with synchronous interface fast read write cycle times. SyncBiFIFOis data buffer that store retrieve information from sources simultaneously. Dual-Port FIFO memory arrays contained SyncBiFIFO; data buffer each direction. SyncBiFIFO registers inputs outputs. Data only transferred into registers clock edges, hence interfaces synchronous. Each Port independent clock. Data transfers registers gated enable signals. transfer direction each port controlled independently read/write signal. Individual output enable signals control whether SyncBiFIFO driving data lines port whether those data lines high-impedance state. Bypass control allows data directly transferred from input output register either direction. SyncBiFIFO eight flags. flag pins full, empty, almost-full, almost-empty both FIFO memories. offset depths almost-full almost-empty flags programmed location. SyncBiFIFO fabricated using IDT's high-speed, submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
R/WA
HIGH CONTROL CLKA INPUT REGISTER OUTPUT REGISTER MEMORY ARRAY MEMORY ARRAY RESET LOGIC
INTERFACE FLAG LOGIC
EFBA PAEBA PAFBA FFBA
EFAB PAEAB PAFAB FFAB
FLAG LOGIC
POWER SUPPLY INPUT REGISTER
CLKB
OUTPUT REGISTER HIGH CONTROL
R/WB
BYPB
COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
DB0-DB17
2704
SyncBiFIFO trademark logo registered trademark Integrated Device Technology, Inc.
AUGUST 1993
DSC-2045/3
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CONFIGURATIONS
DB11 DB13 DB12 DB14 DB15 DB16 DB17
DB10
R/WB CLKB
PAEAB PAFAB EFAB FFAB
G68-1
Designator
BYPB
PAEBA PAFBA EFBA FFBA
DA10
View
CLKA R/WA DA12 DA14 DA16 DA13 DA15
2704
DA17
DA11
DA16 DA17 EFAB FFAB PAFAB
J68-1
DB15 DB14 DB13 DB12 DB11 DB10
DA15 DA14 DA13 DA12 DA11 DA10
EFBA PAEBA BYPB R/WB CLKB
2704
PLCC View
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CONFIGURATIONS
EFBA FFBA PAEBA PAFBA
BYBB R/WB
CLKB
DA10 DA11 DA12 DA13 DA14 DA15 PN64-1 DB10 DB11 DB12 DB13 DB14 DB15 DB16
EFAB FFAB PAEAB PAFAB
CLKA
DA16
DA17
DB17
2704
TQFP View
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
DESCRIPTION
Symbol DA0-DA17 Name Data Chip Select Read/Write Description Data inputs outputs 18-bit Port bus. This controls read write direction Port R/WA LOW, Data input data written into Port R/WA HIGH, Data output data read from Port bypass mode, when R/WA LOW, message written into output register. R/WA HIGH, message read from output register. CLKA typically free running clock. Data read written into Port rising edge CLKA. When LOW, data read written Port When HIGH, data transfers occur. When R/WA HIGH Port output controls high-impedance state DA0-DA17. HIGH, Port high-impedance state. while R/WA HIGH, Port active (low-impedance) state. Data inputs outputs 18-bit Port bus. This controls read write direction Port R/WB LOW, Data input data written into Port R/WB HIGH, Data output data read from Port bypass mode, when R/WB LOW, message written into output register. R/WB HIGH, message read from output register. Clock typically free running clock. Data read written into Port rising edge CLKB. When LOW, data read written Port When HIGH, data transfers occur. When R/WB HIGH Port output controls high-impedance state DB0-DB17. HIGH, Port high-impedance state. while R/WB HIGH, Port active (low-impedance) state. When EFAB LOW, FIFO empty further data reads from Port inhibited. When EFAB HIGH, FIFO empty. EFAB synchronized CLKB. bypass mode, EFAB HIGH indicates that data DA0-DA17 available passing through. After data DB0-DB17 been read, EFAB goes LOW. Port accessed when LOW. Port inactive HIGH.
R/WA
CLKA
Clock Enable Output Enable
Addresses DB0-DB17 R/WB Data Read/Write
When asserted, R/WA used select internal resources.
CLKB
Clock Enable Output Enable
EFAB
Empty Flag
PAEAB
Programmable Almost-Empty Flag Programmable Almost-Full Flag Full Flag
PAFAB
When PAEAB LOW, FIFO almost empty. almost empty FIFO contains less than equal offset programmed into PAEAB Register. When PAEAB HIGH, FIFO contains more than offset PAEAB Register. default offset value PAEAB Register PAEAB synchronized CLKB.
FFAB
When PAFAB LOW, FIFO almost full. almost full FIFO contains greater than FIFO depth minus offset programmed into PAFAB Register. When PAFAB HIGH, FIFO contains less than equal depth minus offset PAFAB Register. default offset value PAFAB Register PAFAB synchronized CLKA.
When FFAB LOW, FIFO full further data writes into Port inhibited. When FFAB HIGH, FIFO full. FFAB synchronized CLKA. bypass mode, FFAB tells Port that message waiting Port output register. FFAB LOW, bypass message register. FFAB HIGH, Port read message another message written into Port
EFBA
Empty Flag
PAEBA
Programmable Almost-Empty Flag Programmable Almost-Full Flag
PAFBA
When PAEBA LOW, FIFO almost empty. almost empty FIFO contains less than equal offset programmed into PAEBA Register. When PAEBA HIGH, FIFO contains more than offset PAEBA Register. default offset value PAEBA Register PAEBA synchronized CLKA.
When EFBA LOW, FIFO empty further data reads from Port inhibited. When EFBA HIGH, FIFO empty. EFBA synchronized CLKA. bypass mode, EFBA HIGH indicates that data DB0-DB17 available passing through. After data DA0-DA17 been read, EFBA goes following cycle.
When PAFBA LOW, FIFO almost full. almost full FIFO contains greater than FIFO depth minus offset programmed into PAFBA Register. When PAFBA HIGH, FIFO contains less than equal depth minus offset PAFBA Register. default offset value PAFBA Register PAFBA synchronized CLKB.
2704
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
DESCRIPTION (Continued)
Symbol Name Full Flag Description When FFBA LOW, FIFO full further data writes into Port inhibited. When FFBA HIGH, FIFO full. FFBA synchronized CLKB. bypass mode, FFBA tells Port that message waiting Port output register. FFBA LOW, bypass message register. FFBA HIGH, Port read message another message written into Port This flag informs Port that Synchronous BiFIFO bypass mode. When BYPB LOW, Port placed FIFO into bypass mode. BYPB HIGH, Synchronous BiFIFO passes data into memory. BYPB synchronized CLKB. this will perform reset Synchronous BiFIFO functions. There three power pins PLCC packages TQFP. There seven ground pins PLCC packages four TQFP.
2704
FFBA
BYPB
Port Bypass Flag Reset Power Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect Ground Operating Temperature Temperature Under Bias Storage Temperature Output Current Com'l. -0.5 +7.0 Mil. -0.5 +7.0 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol VIL(1) Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Min. Typ. Max. Unit
2704
TBIAS TSTG IOUT
+125 +125
+125 +135 +150
NOTE: 1.5V undershoots allowed 10ns once cycle.
CAPACITANCE +25°C, 1.0MHz)
Symbol CIN(2) COUT(1,2) Parameter Input Capacitance Output Capacitance Conditions VOUT Max. Unit
2704
NOTE: 2704 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
NOTES: With output deselected. Characterized values, currently tested.
ELECTRICAL CHARACTERISTICS
(Commercial: 10%, +70°C)
IDT72615L IDT72605L Commercial tCLK 50ns Typ.
Symbol IIL(1) IOL(2) ICC(3)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic Voltage IOUT -2mA Output Logic Voltage IOUT Average Power Supply Current
Min.
Max.
Unit
2704
NOTES: Measurements with 0.4V VCC. OEA, VIH; VOUT VCC. Tested with outputs open. Testing frequency f=20MHz
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
TEST CONDITIONS
Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V 1.5V 1.5V Figure
2704
1.1K
D.U.T. 30pF*
2704
ELECTRICAL CHARACTERISTICS
(Commercial: 5V±10%, +70°C)
72615L20 72605L20 Min. Max.
equivalent circuit Figure Output Load Includes scope capacitances.
Symbol fCLK tCLK tCLKH tCLKL tRSS tRSR tRSF tOLZ tOHZ tPAE tPAF tSKEW1 tSKEW2
Parameter Clock frequency Clock cycle time Clock HIGH time Clock time Reset pulse width Reset set-up time Reset recovery time Reset flags intial state Data access time Control signal set-up time(1) Control signal hold time(1) Data set-up time Data hold time Output Enable output data valid(2) Output Enable data Low-Z(2) Output Enable HIGH data High-Z(2) Clock Full Flag time Clock Empty Flag time Clock Programmable Almost Empty Flag time Clock Programmable Almost Full Flag time Skew between CLKA CLKB Empty/Full Flags(2) Skew between CLKA CLKB Programmable Flags(2)
Commercial 72615L25 72615L35 72615L50 72605L25 72605L35 72605L50 Min. Max. Min. Max. Min. Max. Unit
Timing Figures 4,5,6,7 4,5,6,7,12,13,14,15 4,5,6,7,12,13,14,15 5,7,8,9,10,11 4,5,6,7,8,9,10,11, 13,14,15 4,5,6,7,10,11,12, 14,15 4,6,8,9,10,11 5,7,8,9,10,11 5,7,8,9,10,11 5,7,10,11 4,6,10,11 5,7,8,9,10,11 12,14 13,15 4,5,6,7,8,9,10,11 7,12,13,14,15
NOTES: Control signals refer CSA, R/WA, ENA, R/WB, ENB. Minimum values guaranteed design.
2704
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
FUNCTIONAL DESCRIPTION
IDTs SyncBiFIFO versatile both multiprocessor peripheral applications. Data stored retrieved from sources simultaneously. SyncBiFIFO registers inputs outputs. Data only transferred into registers clock edges, hence interfaces synchronous. Dual-Port FIFO memory arrays contained SyncBiFIFO; data buffer each direction. Each port independent clock. Data transfers registers gated enable signals. transfer direction each port controlled independently read/write signal. Individual output enable signals control whether SyncBiFIFO driving data lines port whether those data lines highimpedance state. processor connected Port BiFIFO send receive messages directly Port device using 18-bit bypass path. SyncBiFIFO used multiples 18-bits. 36to 36-bit configuration, SyncBiFIFOs operate parallel. Both devices programmed simultaneously, data bits each device. This configuration extended wider widths (54- 54-bits, 72-bits, etc.) adding more SyncBiFIFOs configuration. Figure shows multiple SyncBiFIFOs configured multiprocessor communication. microprocessor microcontroller connected Port controls operations SyncBiFIFO. Thus, Port interface pins inputs driven controlling processor. Port interfaces with second processor. Port control pins inputs driven second processor.
Reset accomplished whenever Reset (RS) input taken state with CSA, HIGH. During reset, both internal read write pointers first location. reset required after power before write operation take place. FIFO Empty Flags (EFAB, EFBA) Programmable Almost Empty Flags (PAEAB, PAEBA) will after tRSF. FIFO Full Flags (FFAB, FFBA) Programmable Almost Full Flags (PAFAB, PAFBA) will HIGH after tRSF. After reset, offsets Almost-Empty Flags AlmostFull Flags FIFO offset default
RESET
PORT INTERFACE
SyncBiFIFO straightforward micro-processor-based systems because each port standard microprocessor control set. Port interfaces with microprocessor through three address pins (A2-A0) Chip Select pins. When asserted, A2,A1,A0 R/WA used select internal resources (Table With A2=0 A1=0, determines whether data read output register written into FIFO (A0=0), data pass through FIFO through bypass path (A0=1). With A2=1, four programmable flags (two FIFO programmable flags FIFO programmable flags) selected: FIFO Almost-Empty Flag Offset (A1=0, A0=0), FIFO Almost-Full Flag Offset (A1=0, A0=1), FIFO Almost-Empty Flag Offset (A1=1, A0=0), FIFO Almost-Full Flag Offset (A1=1, A0=1). Port disabled when deasserted data high-impedance state.
SYNCBIFIFO MICROPROCESSOR DATA ADDR, CONTROL LOGIC SYNCBIFIFO DATA DATA CONTROL CONTROL SYSTEM CLOCK SYSTEM CLOCK CONTROL LOGIC DATA DATA CONTROL CONTROL MICROPROCESSOR DATA ADDR,
2704
NOTES: Upper SyncBiFIFO only used 18-bit configuration. Control Consists R/WA, ENA, OEA, CSA, Control consists R/WB, ENB, OEB. Figure 36-bit Processor Interface Configuration.
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
R/WA
Data
Port Operation Data written CLKA This write cycle immediately following low-impedance cycle prohibited. Note that even though logic level R/WA, once qualified rising edge CLKA, will Data into high-impedance state. Data written CLKA Data ignored Data read(1) from array output register CLKA Data low-impedance Data read(1) from array output register CLKA Data high-impedance Output register does change(2), Data low-impedance Output register does change(2), Data high-impedance Data ignored(3) Data high-impedance(3)
2704 NOTES: When A2A1A0 000, next FIFO value read output register read pointer advances. A2A1A0 001, bypass path selected bypass data from Port input register read from Port output register. A2A1A00 1XX, flag offset register selected offset read through Port output register. Regardless condition A2A1A0, data Port output register does change read pointer does advance. CSA# HIGH, then BYPB HIGH. bypass occur under this condition.
Table Port Operation Control Signals
BYPASS PATH
bypass paths provide direct communication between Port Port There full 18-bit bypass paths, each direction. During bypass operation, data passed directly between input output registers, FIFO memory undisturbed. Port initiates terminates bypass operations. bypass flag, BYPB, asserted inform Port that bypass operation beginning. bypass flag state controlled Port controls, although BYPB signal synchronized CLKB. BYPB asserted next rising edge CLKB when A2A1A0=001and LOW. When Port returns normal FIFO mode (A2A1A0=000 HIGH), BYPB deasserted next CLKB rising edge. Once SyncBiFIFO bypass mode, data transfers controlled standard Port (R/WA, CLKA, ENA, OEA) Port (R/WB, CLKB, ENB, OEB) interface pins. Each bypass path considered word deep FIFO. Data held each input register until read. Since controls each port operate independently, Port reading bypass data same time Port reading bypass data. When R/WA LOW, data pins DA0-DA17 written into Port input register. Following rising edge CLKA this write, Full Flag (FFAB) goes LOW. Subsequent writes into Port blocked internal logic until FFAB goes HIGH again. next CLKB rising edge, Empty Flag (EFAB) goes HIGH indicating Port that data available. Once R/WB HIGH LOW,
data read into Port output register. still controls whether Port high-impedance state. WhenOEB LOW, output register data appears DB0-DB17. EFAB goes following CLKB rising edge this read. FFAB goes HIGH next CLKA rising edge, letting Port know that another word written through bypass path. Bypass data transfers from Port Port work similar manner with EFBA FFBA indicating Port output register state. When Port address changes from bypass mode (A2A1A0=001) FIFO mode (A2A1A0=000) rising edge CLKA, data held Port output register overwritten. Unless Port monitors BYPB waits Port clock last bypass word, data from FIFO will overwrite data Port output register. BYPB will HIGH rising edge CLKB signifying that Port finished last bypass operation. Port must read bypass data output register this last CLKB clock lost SyncBiFIFO returns FIFO operations. especially important monitor BYPB when CLKB much slower than CLKA avoid this condition. BYPB will also HIGH after brought HIGH; this manner Port bypass data also lost. Since Port processor controls bypass mode, this scenario handled bypass data. Port processor must read last bypass word before leaving bypass mode.
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
Read Write FIFO FIFO 18-bit Bypass Path FIFO Almost-Empty Flag Offset FIFO Almost-Full Flag Offset FIFO Almost-Empty Flag Offset FIFO Almost-Full Flag Offset Port Disabled
2704
PROGRAMMABLE FLAGS
SyncBiFIFO eight flags: four flags FIFO (EFAB, PAEAB, PAFAB, FFAB), four flags FIFO (EFBA, PAEBA, PAFBA, FFBA). Empty Full flags fixed, while Almost Empty Almost Full offsets depth through Flag Offset Registers (see Table flags asserted depths shown Flag Truth Table (Table After reset, programmable flag offsets This means Almost Empty flags asserted Empty words deep, Almost Full flags asserted Full words deep. PAEAB synchronized CLKB, while PAEAB synchronized CLKA; PAEBA synchronized CLKA, while PAEBA synchronized CLKB. minimum time (tSKEW2) between rising CLKB rising CLKA met, flag will change state current clock; otherwise, flag change state until next clock rising edge. specific flag timings, refer Figures 12-15.
Table Accessing Port Resources Using CSA,
PORT CONTROL SIGNALS
Port control signals pins dictate various operations shown Table Port accessed when LOW, inactive HIGH. R/WA lines determine when Data written read. R/WA LOW, data written into input register LOW-to-HIGH transition CLKA. R/WA HIGH LOW, data comes read from output register into three-state buffer. Refer descriptions more information.
PORT CONTROL SIGNALS
Port control signal pins dictate various operations shown Table Port independent CSA. R/WB lines determine when Data written read Port R/WB LOW, data written into input register, LOW-to-HIGH transition CLKB data written into
PAEAB PAFAB PAEBA PAFBA
Register
FIFO Almost-Empty Flag Offset FIFO Almost-Full Flag Offset
Register
Register
FIFO Almost-Empty Flag Offset FIFO Almost-Full Flag Offset
Register
NOTE: must IDT72605 (256 Synchronous BiFIFO. Table Flag Offset Register Format.
2704
Number Words FIFO From D-(m+1)
HIGH HIGH HIGH HIGH
HIGH HIGH HIGH
HIGH HIGH HIGH
HIGH HIGH HIGH HIGH
2704
NOTES: Programmable Empty Offset (PAEAB Register PAEBA Register) Programmable Full Offset (PAFAB Register PAFBA Register) FIFO Depth (IDT72605 words, IDT72615= words) Table Internal Flag Truth Table.
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
input register FIFO memory. R/WB HIGH LOW, data comes read from output register into three-state buffer. bypass mode, R/WB LOW, bypass messages transferred into output register. R/WA HIGH, bypass messages transferred into output register. Refer descriptions more information.
R/WB
Data
Port Operation Data written CLKB This write cycle immediately following output lowimpedance cycle prohibited. Note that even though logic level R/WB, once qualified rising edge CLKB, will Data into high-impedance state. Data written CLKB Data ignored Data read(1) from array output register CLKB Data impedance Data read(1) from array output register CLKB Data HIGH impedance Output register does change(2), Data low-impedance Output register does change(2), Data high-impedance
NOTES: 2704 When A2A1A0 1XX, next FIFO value read output register read pointer advances. A2A1A0 001, bypass path selected bypass data read from Port output register. Regardless condition A2A1A0, data Port output register does change read pointer does advance.
Table Port Operation Control Signals.
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
tRSF
CSA,
tRSF
tRSS
tRSR
Figure Reset Timing
2704
tCLK tCLKH CLKA tCLKL
R/WA
FFAB -DA17 tSKEW1 CLKB READ DATA VALID READ OPERATION
2704
OPERATION
Figure Port (AB) Write Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
tCLK tCLKH CLKA tCLKL
R/WA
EFBA -DA17 tOLZ tSKEW1 CLKB WRITE WRITE
2704
OPERATION
VALID DATA tOHZ
Figure Port (BA) Read Timing
tCLK tCLKH CLKB tCLKL
R/WB FFBA -DB17 tSKEW1 CLKA READ DATA VALID READ OPERATION OPERATION
2704
Figure Port (BA) Write Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
tCLK tCLKH CLKB tCLKL
R/WB EFAB -DB17 tOLZ tSKEW1 CLKA WRITE OPERATION
Figure Port (AB) Read Timing
OPERATION
VALID DATA tOHZ
WRITE
2704
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKA
R/WA tSKEW1 CLKB (First valid write) tFRL
R/WB EFAB
2704
NOTE: When tSKEW1 minimum specification, tFRL(Max.) tCLK tSKEW1 tSKEW1 minimum specification, tFRL(Max.) 2tCLK tSKEW1 tCLK tSKEW1 Latency Timing applies only Empty Boundary LOW). Figure First Data Word Latency after Reset Simultaneous Read Write
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKB
R/WB tSKEW1 CLKA (First valid write) tFRL
R/WA EFBA
2704
NOTE: When tSKEW1 minimum specification, tFRL(Max.) tCLK tSKEW1 tSKEW1 minimum specification, tFRL(Max.) 2tCLK tSKEW1 Latency Timing apply only Empty Boundary LOW). Figure First Data Word Latency after Reset Simultaneous Read Write
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKA
R/WA FFAB tSKEW1 CLKB DATA INPUT tSKEW1 tSKEW1 BYPASS FLAG FIFO FLAG
R/WB EFAB FIFO FLAG BYPASS FLAG FIFO FLAG
BYPB
2704
DATA OUTPUT
NOTES: When brought HIGH, Bypass mode will switch FIFO mode following CLKA LOW-to-HIGH transition. After bypass operation completed, BYPB goes from LOW-to-HIGH; this will reset bypass flags. bypass path becomes available next bypass operation. When A-side changed from bypass mode into FIFO mode, B-side only cycle read bypass data. next cycle, B-side will forced back FIFO mode. Figure Bypass Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKB
R/WB FFBA BYPASS FLAG FIFO FLAG
BYPB -DB17 tSKEW1 CLKA tSKEW1 tSKEW1 tSKEW1 DATA INPUT
R/WA EFBA FIFO FLAG BYPASS FLAG -DA17 tOLZ
2704
FIFO FLAG
DATA OUTPUT
NOTES: When brought HIGH, Bypass mode will switch FIFO mode following CLKA going LOW-to-HIGH. After bypass operation completed, BYPB goes from LOW-to-HIGH; this will reset bypass flags. bypass path becomes available next bypass operation. When A-side changed from bypass mode into FIFO mode, B-side only cycle read bypass data. next cycle, B-side will forced back FIFO mode. Figure Bypass Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKH CLKA
tCLKL
(R/W
WRITE words FIFO tSKEW2
words FIFO
tPAE
(R/W
READ
2704
NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge PAEAB change during that clock cycle. time between rising edge CLKA rising edge CLKB less than tSKEW, then PAEAB HIGH until next CLKB rising edge. read performed this rising edge read clock, there will Empty words FIFO when goes LOW. Figure Programmable Almost-Empty Flag Timing
CLKH CLKA
tCLKL
(R/W PAFAB
WRITE Full (m+1) words FIFO tPAF Full words FIFO tPAF
(R/W
READ
2704
NOTES: tSKEW2 minimum time between rising CLKB edge rising CLKA edge PAFAB change during that clock cycle. time between rising edge CLKB rising edge CLKA less than tSKEW2, then PAFAB HIGH until next CLKA rising edge. write performed this rising edge write clock, there will Full words FIFO when goes LOW. Figure Programmable Almost-Full Flag Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
CLKH CLKB
tCLKL
(R/W PAEBA
WRITE words FIFO tSKEW2
words FIFO tPAE
(R/W
2704
READ
NOTES: tSKEW2 minimum time between rising CLKB edge rising CLKA edge PAEBA change during that clock cycle. time between rising edge CLKB rising edge CLKA less than tSKEW2, then PAEBA HIGH until next CLKA rising edge. read performed this rising edge read clock, there will Empty words FIFO when goes LOW. Figure Programmable Almost-Empty Flag Timing
CLKH CLKB
tCLKL
(R/W PAFBA
WRITE Full (m+1) words FIFO tPAF Full words FIFO tSKEW2 tPAF
(R/W
READ
2704
NOTES: tSKEW2 minimum time between rising CLKB edge rising CLKA edge PAFBA change during that clock cycle. time between rising edge CLKB rising edge CLKA less than tSKEW2, then PAFBA HIGH until next CLKA rising edge. write performed this rising edge write clock, there will Full words FIFO when goes LOW. Figure Programmable Almost-Full Flag Timing
5.13
IDT72605/IDT72615 CMOS SyncBiFIFO
ORDERING INFORMATION
XXXXX Device Type Power Speed Package Process/ Temperature Range Commercial (0°C +70°C)
BLANK
72605 72615
68-pin 68-pin PLCC 64-pin TQFP
Clock Cycle Time
Power Parallel Synchronous Bidirectional FIFO Parallel Synchronous Bidirectional FIFO
2704
5.13
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