TECHNICAL NOTE TN-03 Integrated Device Technology, Inc. Michael M

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TECHNICAL NOTE TN-03 Integrated Device Technology, Inc. Michael M

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USING IDT49C402A
TECHNICAL NOTE TN-03
Integrated Device Technology, Inc. Michael Miller
MICROSLICEfamily consists high-performance VLSI building blocks that provide such functions ALUs, sequencers building complex finite state machines, register files support devices. IDT49C402A member this MICROSLICE family first series 16-bit
ALUs from IDT. This high-speed (shown Figure capable supporting 20MHz operations. This phenomenal speed result CEMOS, single-poly double-metal structure using micron gate lengths designed highperformance high-reliability.
DATAIN
SHIFT SHIFT
DATA
READ ADDR READ/ WRITE ADDR
ADDRESS
DATA
ADDRESS
REGISTER
LOGIC
Instruction Decode
SOURCE SELECTOR
G/F15 P/OVR
DATA SELECTOR
DATAOUT
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Figure Block Diagram IDT49C402A
CEMOS MICROSLICE trademarks Integrated Device Technology, Inc. ©1990 Integrated Device Technology, Inc.
1/90
USING IDT49C402A
TECHNICAL NOTE TN-03
APPLICATIONS
IDT49C402A thought VLSI building block. This building block register file, accumulator. Since IDT49C402A designed static random logic, this device used many different places. used data path element general purpose computer address generator generate complex addresses accessing data structures linked lists. might also used complex accumulator with input achieve sophisticated counter-type operations where constants register file order CORDIC-type algorithms. simply, IDT49C402A thought used very high-performance 16-bit version widely used 4-bit 7400 family (74181, 251, 381) ALUs.
destination control functions. This input, conjunction with through allows many functions take place like shifting register down independently, well loading registers directly from inputs without going through ALU. tying instruction input high, through instruction lines exhibit destination codes found 2901. With line low, additional functions IDT49C402A accessed.
EXTRA DATA PATHS
IDT49C402A, while using same basic 2901-type architecture, incorporates data path aimed increasing system parallelism. This data path goes directly from inputs into register file register. Normally, loading register file register 2901 requires that work pass function order route direct data input path through then store results register file register. With data path, data directly into register file parallel with other operations. example, cycle destination instruction allows output port register file register combined together with results being stored into register, while data brought into register file stored address selected address port. more sophisticated destination functions available IDT49C402A DFA. This allows loaded directly from inputs, register receive results output output data directly from RAM. This extra data path allows full, complete utilization three major buses inside IDT49C402A.
FUNCTIONAL DESCRIPTION
IDT49C402A high-speed, fully cascadable 16-bit CMOS slice with 64-by-16-bit register file. combines standard functions four 2901s (4-bit ALU) 2902 (carry lookahead) with additional control features aimed enhancing performance bit-slice microprocessor designs. Based normal control functions associated with standard 2901 bit-slice operation, IDT49C402A includes twice destination codes. standard functions (Figures include 3-bit instruction field which controls source operand select (I0, I2), 3-bit instruction field used control possible functions (I3, I5), 3-bit instruction field (I6, selecting standard destination control functions supported 2901. tenth microinstruction input, offers additional
FUNCTION CONTROL
Microcode Mnemonic SUBR SUBS NOTRS EXOR EXNOR Octal Code Function Plus Minus Minus
SOURCE CONTROL
Microcode Mnemonic Octal Code Source Operands
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EX-OR EX-NOR
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Figure Function Source Codes
USING IDT49C402A
TECHNICAL NOTE TN-03
DESTINATION CONTROL
Microcode Mnemonic OREG RAMA RAMF RAMQD RAMD RAMQU RAMU XQDF XQUF Code Data Stored Address Data Stored Register Output
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Original 2901 Functions
Added IDT49C402 Functions
Figure Destination Codes
REGISTER FILE
register file IDT49C402A addressable locations, each bits wide. Being four times larger than most other 16-bit slices, this increased data space provides larger cache data which minimizes traffic bring data from outside world into register file. From another perspective, register file also viewed banks location register files. using address lines, register file bank-selected, thus allowing programmer have virtual 2901s operating inside IDT49C402A. This enables user perform multi-tasking microcode. each clock cycle task selected, thus having minimal overhead context switches.
6.5ns (utilizing IDT74FCT374A) set-up time data status (37ns) from IDT49C402A into status register with set-up time 2.5ns.
32-BIT APPLICATIONS
High-speed operation most 32-bit applications easily obtainable when using IDT49C402A. order build 32-bit ALU, IDT49C402As cascaded connecting carryout device into carry-in next device (see Figure this 32-bit design critical path through carryout 16), which 34ns, then through carryin (Cn) most significant device set-up clock, which 32ns. Using IDT's FCT/A logic family, cycle time 75ns constructed.
INCREASED PERFORMANCE
critical path through IDT49C402A address instruction lines output status flags (ABI Y/Flags). version IDT49C402 this 37ns, time required address input lines select operands register file output data. This allows user construct data path well under 50ns. This would include pipeline register instruction time with clock-to-Q
CONCLUSION
IDT49C402A used multitude applications which previously incorporated discrete 2901s. Upgrading this high-performance device allows user operate 20MHz level while reducing board space overall power. exemplifies overall flexibility VLSI building block wherever function with register files used.
USING IDT49C402A
TECHNICAL NOTE TN-03
32-Bits DataIN
System Clock
32-Bits DataOUT
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Figure 32-Bit configuration showing critical delay path
IDT74FCT374A

TECHNICAL NOTE TN-03 Integrated Device Technology, Inc. Michael M

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