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Pentium® XeonProcessor Specification Update
Order Number: 244460-002
Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update.
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CONTENTS
REVISION HISTORY. PREFACE Specification Update Pentium® XeonProcessor. GENERAL INFORMATION. ERRATA. DOCUMENTATION CHANGES SPECIFICATION CLARIFICATIONS SPECIFICATION CHANGES
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date Revision March 1999 April 1999 Version -001 -002 Description This document first Specification Update Pentium® Xeonprocessor. Removed Erratum G15. Renumbered remaining errata. Added Errata G46. Corrected Errata table "Plans" column G42. Updated Pentium Xeon Processor Identification Package Information table. Moved revised Mixed Steppings statement General Information section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
PREFACE
This document update specifications contained Pentium® XeonProcessor datasheet (Order Number 245094) Intel Architecture Software Developer's Manual, Volumes (Order Numbers 243190, 243191, 243192, respectively). intended hardware system manufacturers software developers applications, operating systems, tools. contains Specification Changes, Errata, Specification Clarifications, Documentation Changes.
Nomenclature
S-Spec Number five digit code used identify products. Products differentiated their unique characteristics, e.g., core speed, cache size, package type, etc., described processor identification information table. Care should taken read notes associated with each S-Spec number. Specification Changes modifications current published specifications Pentium® Xeonprocessor. These changes will incorporated next release specifications. Errata design defects errors. Errata cause Pentium Xeon processor's behavior deviate from published specifications. Hardware software designed used with given processor must assume that errata documented that processor present devices unless otherwise noted. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications.
Identification Information
Pentium Xeon processor identified following values: Family1 0110 Pentium® XeonProcessor2 0111
NOTES: Family corresponds bits [11:8] register after Reset, bits [11:8] register after CPUID instruction executed with register, generation field Device register accessible through Boundary Scan. Model corresponds bits [7:4] register after Reset, bits [7:4] register after CPUID instruction executed with register, model field Device register accessible through Boundary Scan.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
Pentium Xeon processor's second level (L2) cache size determined following register contents: 512-Kbyte Unified Cache 1-Mbyte Unified Cache 2-Mbyte Unified Cache
NOTE:
Pentium® Xeonprocessor, unified cache size corresponds token register after CPUID instruction executed with register. Other Intel microprocessor models families move this information other positions otherwise reformat result returned this instruction; generic code should parse resulting token stream according definition CPUID instruction.
Specification Update Pentium® XeonProcessor
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
GENERAL INFORMATION
Pentium® Xeonand Boxed Pentium® XeonProcessor Markings
Production Dynamic Mark Example:
500/512/100/2.0V FFFFFFFF-NNNN {country} ©'98 SSSSS
Matrix Contents Example: Intel 80525PY500512 FFFFFFFF-NNNN
Dynamic Mark Area
Speed Cache Voltage Identifier
Matrix Mark
Serial Country Assy
500/512/100/2.0V FFFFFFFF-NNNN XXXXX ©'98 SYYYY
S-Spec
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE Pentium® XeonProcessor Identification Package Information S-Spec Number SL2XU SL2XV SL2XW SL3C9 SL3CA SL3CB SL3FK SL3FR Core Stepping Speed (MHz) Size (Kbytes) 1024 2048 1024 2048 Cache Stepping Processor Substrate Revision 512K-6A 1M-6A 2M-kA 512K-6A 1M-6A 2M-kA 512K-kA 512K-kA Cartridge Revision
CPUID 672h 672h 672h 672h 672h 672h 673h 673h
Notes
NOTES: These processors affected Erratum G44. performance-monitoring event counter inaccurate when counting events Data Cache Unit External Logic these processors. counter count these events. This boxed processor with attached passive heatsink. These processors validated systems only. These processors affected Erratum G46.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
Summary Table Changes
following table indicates Errata which apply Pentium Xeon processors. Intel intends some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations: CODES USED SUMMARY TABLE Doc: Fix: Fixed: NoFix: mark) (blank box): SUB: Shaded: Specification Change, Erratum, Specification Clarification, Documentation Change applies given processor stepping. Intel intends update appropriate documentation future revision. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum. This item fixed does apply given stepping. APIC related erratum. This column refers errata Pentium® Xeonprocessor's substrate components other than processor core. This item either modified from previous version document.
Some Intel's Specification Updates will undergoing numbering methodology change reduce confusion when referring errata which affect specific product. Each Specification Update item will prefixed with capital letter distinguish product refers below details letters which will used current Intel microprocessor Specification Updates: Pentium® processor Mobile Pentium® processor Intel® Celeronprocessor Pentium® Xeonprocessor Pentium® processor Pentium® Xeonprocessor Intel® Mobile Celeronprocessor Specification Updates Pentium® processor, Pentium® processor, other Intel products will implementing such convention this time.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
Plans NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix
ERRATA Data Operand Pointer incorrectly calculated after access which wraps 64-Kbyte boundary 16-bit code Differences exist debug exception reporting FLUSH# servicing delayed while waiting STARTUP_IPI systems Code fetch matching disabled debug register cause debug exception Double error read result BINIT# inexact-result exception flag Bfor will contain incorrect FROM restart fail after simultaneous Branch traps function BTMs also enabled Checker BIST failure mode signaled BINIT# assertion causes FRCERR assertion mode Machine check exception handler always execute successfully LBER corrupted after some events BTMs corrupted during simultaneous cache line replacement Near CALL creates unexpected address Mixed cacheability lock variables problematic systems parity error gives MCACOD.LL Memory Type field undefined nonmemory operations Infinite snoop stall during initialization systems Data Operand Pointer zero after power Reset Premature execution load operation prior exception handler invocation EFLAGS discrepancy page fault after multiprocessor shootdown Read portion instruction execute twice MC2_STATUS model-specific error code Machine Check Architecture error code reversed MOVD following zeroing instruction cause incorrect result entries usable with Mode Mode paging with debug register causes debug exception Data Breakpoint Exception displacement relative near call corrupt System functional with ratio RDMSR WRMSR invalid address cause fault SYSENTER/SYSEXIT instructions implicitly load "null segment selector" registers
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
G1AP G2AP G3AP
Plans NoFix NoFix NoFix
ERRATA PRELOAD followed EXTEST does load boundary scan data jump with D-bit cleared cause system hang Illegal opcode during cache initialization Incorrect cache line invalidation Transmission error cache read COMISS/UCOMISS update EFLAGS under certain conditions System hang occur with core ratio Misaligned locked access APIC space results hang Potential loss data coherency during data ownership transfer instruction handler execution could generate debug exception Memory ordering based synchronization cause livelock condition systems Floating point exception signal deferred System address parity checking report false AERR# Processor assert DRDY# write with data Thermal sensor leakage current exceed specification APIC access cacheable memory causes shutdown systems hang catastrophic errors during determination Write mask (programmed EXTINT) will deassert outstanding interrupt
NoFix NoFix NoFix NoFix NoFix NoFix
NoFix NoFix NoFix NoFix
NOTE: erratum titled A20M# inverted after returning from Reset numbered been removed. erroneously included previous versions this Specification Update. remaining errata have been renumbered. Plans SPECIFICATION CHANGES Locks across cache line boundary disable added
Mixed Steppings Systems
Intel Corporation fully supports mixed steppings Pentium Xeon processors. following list processor matrix describes requirements support mixed steppings: Mixed steppings only supported with processors that have identical family model number indicated CPUID instruction. While Intel done nothing specifically prevent processors operating differing frequencies from functioning within multiprocessor system, there uncharacterized errata that exist such configurations. Intel does support such configurations. mixed stepping systems, processors must operate identical frequencies (i.e., highest frequency rating commonly supported processors).
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
While there known issues associated with mixing processors with differing cache sizes multiprocessor system, Intel done nothing specifically prevent such system configurations from operating, Intel does support such configurations since there uncharacterized errata that exist. mixed stepping systems, processors must same cache size. While Intel believes that certain customers wish perform validation system configurations with mixed frequency cache sizes, that those efforts acceptable option customers, customers would fully responsible validation such configurations. workarounds identified this following specification updates must properly applied each processor system. Certain errata specific multiprocessor environment identified Mixed Stepping Processor Matrix found this section. Errata processor steppings will affect system performance properly worked around. Also "Pentium® XeonProcessor Identification Package Information" section additional details which processors affected specific errata. mixed stepping systems, processor with lowest feature-set, determined CPUID Feature Bytes, must Bootstrap Processor (BSP). event feature-set, should resolved selecting processor with lowest stepping determined CPUID instruction.
Functional Redundancy Checking Mode (FRC mode) supported using master checker pair processors with different stepping, model number, cache size, frequency.
following processor matrix, "NI" indicates that there currently known issues associated with mixing these steppings. number indicates that known issue been identified listed table following matrix. multiprocessor system using mixed processor steppings must assure that errata addressed appropriately each processor. Mixed Stepping Processor Matrix Stepping NOTES:
Some these processors affected errata which affect features system able support. "Pentium® XeonProcessor Identification Package Information" details which processors affected these errata. stepping processors have differing cache components which require differing voltages. When mixing theses steppings proper cache voltage identified pins must supplied each cartridge.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
ERRATA
Data Operand Pointer Incorrectly Calculated After Access Which Wraps 64-Kbyte Boundary 16-Bit Code
PROBLEM: Data Operand Pointer effective address operand associated with last
noncontrol floating-point instruction executed machine. 80-bit floating-point access (load store) occurs 16-bit mode other than protected mode which case access will produce segment limit violation), memory access wraps 64-Kbyte boundary, floating-point environment subsequently saved, value contained Data Operand Pointer incorrect.
IMPLICATION: 32-bit operating system running 16-bit floating-point code encounter this erratum, under
following conditions: operating system using segment greater than Kbytes size. application running 16-bit mode other than protected mode. 80-bit floating-point load store which wraps 64-Kbyte boundary executed. operating system performs floating-point environment store (FSAVE/FNSAVE/FSTENV/FNSTENV) after above memory access. operating system uses value contained Data Operand Pointer.
Wrapping 80-bit floating-point load around segment boundary this normal programming practice. Intel currently identified software which exhibits this behavior.
WORKAROUND: Data Operand Pointer used which 16-bit floating-point code, care must taken ensure that 80-bit floating-point accesses wrapped around 64-Kbyte boundary. STATUS: steppings affected Summary Table Changes beginning this section.
Differences Exist Debug Exception Reporting
PROBLEM: There exist some differences reporting code data breakpoint matches between that
specified previous Intel processors' specifications behavior Pentium Xeon processor, described below: CASE first case breakpoint MOVSS POPSS instruction, when instruction following causes debug register protection fault (DR7.gd already set, enabling fault). Pentium processor reports delayed data breakpoint matches from MOVSS POPSS instructions setting matching DR6.bi bits, along with debug register protection fault (DR6.bd). additional breakpoint faults matched during call debug fault handler, Pentium processor sets breakpoint match bits (DR6.bi) reflect breakpoints matched both MOVSS POPSS breakpoint debug fault handler call. Pentium Xeon processor only sets DR6.bd either situation, does DR6.bi bits. CASE second breakpoint reporting failure case, MOVSS POPSS instruction with data breakpoint followed store memory which crosses 4-Kbyte page boundary, breakpoint information MOVSS POPSS will lost. Previous processors retain this information across such page split.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
CASE they occur after MOVSS POPSS instruction, INTO, INT3 instructions zero DR6.Bi bits (bits through B3), clearing pending breakpoint information, unlike previous processors. CASE data breakpoint (System Management Interrupt) occur simultaneously, will serviced call handler, pending breakpoint will lost. CASE When instruction which accesses debug register executed, breakpoint encountered instruction, breakpoint reported twice.
IMPLICATION: When debugging when developing debuggers Pentium Xeon processor-based system,
this behavior should noted. Normal usage MOVSS POPSS instructions (i.e., following them with ESP) will exhibit behavior cases 1-3. Debugging conjunction with will limited case
WORKAROUND: Following MOVSS POPSS instructions with instruction when using breakpoints will avoid first three cases this erratum. workaround been identified cases STATUS: steppings affected Summary Table Changes beginning this section.
FLUSH# Servicing Delayed While Waiting STARTUP_IPI Systems
PROBLEM: system, application processor waiting startup inter-processor interrupt (STARTUP_IPI), then will service FLUSH# assertion until received STARTUP_IPI. IMPLICATION: After initialization protocol, only processor becomes bootstrap processor (BSP).
other processor becomes slave application processor (AP). After losing arbitration, goes into wait loop, waiting STARTUP_IPI. wake perform some tasks with STARTUP_IPI, then back sleep with initialization inter-processor interrupt (INIT_IPI, which same effect asserting INIT#), which returns wait loop. result possible loss cache coherency off-line processor intended service FLUSH# assertion this point. FLUSH# will serviced soon processor awakened STARTUP_IPI, before other instructions executed. Intel encountered operating systems that affected this erratum.
WORKAROUND: Operating system developers should take care execute WBINVD instruction before taken off-line using INIT_IPI. STATUS: steppings affected Summary Table Changes beginning this section.
Code Fetch Matching Disabled Debug Register Cause Debug Exception
PROBLEM: bits L0-3 G0-3 enable breakpoints local task global tasks, respectively. these bits set, breakpoint enabled, corresponding addresses debug registers DR0-DR3. least these breakpoints enabled, these registers disabled (i.e., disabled register (indicating breakpoint instruction execution), normally instruction fetch will cause instruction-breakpoint fault based match with address disabled register(s). However,
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
address disabled register matches address code fetch which also results page fault, instruction-breakpoint fault will occur.
IMPLICATION: While debugging software, extraneous instruction-breakpoint faults encountered breakpoint registers cleared when they disabled. Debug software which does implement code breakpoint handler will fail, this occurs. handler present, fault will serviced. Mixing data code exacerbate this problem allowing disabled data breakpoint registers break instruction fetch. WORKAROUND: debug handler should clear breakpoint registers before they become disabled. STATUS: steppings affected Summary Table Changes beginning this section.
Double Error Read Result BINIT#
PROBLEM: this erratum occur, following conditions must met:
Machine Check Exceptions (MCEs) must enabled. dataless transaction (such write invalidate) must occurring simultaneously with transaction which returns data normal read). read data must contain double-bit uncorrectable error.
these conditions met, Pentium Xeon processor will able determine which transaction erroneous, instead generating MCE, will generate BINIT#.
IMPLICATION: will reinitialized this case. However, since double-bit uncorrectable error occurred read, handler (which normally reached double-bit uncorrectable error read) would most likely cause same BINIT# event. WORKAROUND: Though ability drive BINIT# disabled Pentium Xeon processor, which
would prevent effects this erratum, overall system behavior would improve, since error which would normally cause BINIT# would instead cause machine shut down. other workaround been identified.
STATUS: steppings affected Summary Table Changes beginning this section.
Inexact-Result Exception Flag
PROBLEM: When result floating-point operation exactly representable destination format (1/3 binary form, example), inexact-result (precision) exception occurs. When this occurs, (bit status word) normally processor. Under certain rare conditions, this when this rounding occurs. However, other actions taken processor (invoking software exception handler exception unmasked) affected. This erratum only occur floating-point operation which causes precision exception immediately followed following instructions:
m32real m64real FSTP m32real FSTP m64real FSTP m80real FIST m16int FIST m32int FISTP m16int
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
FISTP m32int FISTP m64int
Note that even this combination instructions encountered, there also dependency internal pipelining execution state both instructions processor.
IMPLICATION: Inexact-result exceptions commonly masked ignored applications, happens frequently, produces rounded result acceptable most applications. status word always upon receiving inexact-result exception. Thus, these exceptions unmasked, floating-point error exception handler recognize that precision exception occurred. Note that this "sticky" bit, i.e., once inexact-result condition, remains until cleared software. WORKAROUND: This condition avoided inserting instructions between floating-point
instructions.
STATUS: steppings affected Summary Table Changes beginning this section.
Bfor Will Contain Incorrect FROM
PROBLEM: system management interrupt (SMI) will produce Branch Trace Message (BTM), BTMs enabled. However, FROM field B(used determine address instruction which being executed when serviced) will have been updated SMI, field will report same FROM previous BTM. IMPLICATION: Bwhich issued will contain correct FROM EIP, limiting usefulness BTMs debugging software conjunction with System Management Mode (SMM). WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
Restart Fail After Simultaneous
PROBLEM: instruction (IN, INS, INS, OUT, OUTS, OUTS) being executed, data this instruction becomes corrupted, Pentium Xeon processor will signal machine check exception (MCE). instruction directed device which powered down, processor also receive assertion SMI#. Since MCEs have higher priority, processor will call handler, SMI# assertion will remain pending. However, upon attempting execute first instruction handler, SMI# will recognized processor will attempt execute handler. handler completed successfully, will attempt restart instruction, will have correct machine state, call handler. IMPLICATION: simultaneous SMI# assertion occur instructions above. handler attempt restart such instruction, will have corrupted state handler call, leading failure restart shutdown processor. WORKAROUND: system implementation must support both MCEs, first thing handler
code (when restart performed) should check pending MCE. there pending, handler should immediately exit instruction allow machine check exception handler execute. there not, handler proceed with normal operation.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
Branch Traps Function BTMs Also Enabled
PROBLEM: branch traps branch trace messages (BTMs) enabled alone, both function expected. However, both enabled, only BTMs will function, branch traps will ignored. IMPLICATION: branch traps branch trace message debugging features cannot used together. WORKAROUND: branch trap functionality desired, BTMs must disabled. STATUS: steppings affected Summary Table Changes beginning this section.
G10.
Checker BIST Failure Mode Signaled
PROBLEM: system running functional redundancy checking (FRC) mode, checker master-checker pair encounters hard failure while running built-in self test (BIST), checker will tri-state outputs without signaling IERR#. IMPLICATION: Assuming master passes BIST successfully, will continue execution unchecked, operating without functional redundancy. However, necessary pull-up FRCERR will cause FRCERR signaled. operation master depends implementation FRCERR. WORKAROUND: successful detection BIST failure checker pair, FRCERR
signal, instead IERR#.
STATUS: steppings affected Summary Table Changes beginning this section.
G11.
BINIT# Assertion Causes FRCERR Assertion Mode
PROBLEM: pair Pentium Xeon processors running functional redundancy checking (FRC) mode, catastrophic error condition causes BINIT# asserted, checker master-checker pair will enter shutdown. next transaction from master will then result assertion FRCERR. IMPLICATION: initialization assertion BINIT# occurs result catastrophic error condition which precludes continuing reliable execution system. Under normal circumstances, masterchecker pair would remain synchronized execution BINIT# handler. However, this erratum, FRCERR will signaled. System behavior then depends system specific error recovery mechanisms. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
G12.
Machine Check Exception Handler Always Execute Successfully
PROBLEM: asynchronous machine check exception (MCE), such BINIT# event, which occurs during
access that splits 4-Kbyte page boundary leave some internal registers indeterminate state. Thus, handler code always successfully asynchronous occurred previously.
IMPLICATION: always result successful execution handler. However, asynchronous MCEs usually occur upon detection catastrophic system condition that would also hang processor. Leaving MCEs disabled will result condition which caused asynchronous instead causing processor enter shutdown. Therefore, leaving MCEs disabled improve overall system behavior.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
WORKAROUND: workaround which would guarantee successful handler execution under this condition been identified. STATUS: steppings affected Summary Table Changes beginning this section.
G13.
LBER Corrupted After Some Events
PROBLEM: last branch record (LBR) last branch before exception record (LBER) used determine source destination information previous branches exceptions. contains source destination addresses last branch exception, LBER contains similar information last branch taken before last exception. This information typically used determine location branch which leads execution code which causes exception. However, after catastrophic condition which results assertion BINIT# re-initialization buses, value LBER corrupted. Also, after either CALL which results fault software interrupt, LBER will updated same value, when LBER should have been updated. IMPLICATION: LBER registers used only debugging purposes. When this erratum occurs, LBER will contain reliable address information. value LBER should used with caution when debugging branching code; values LBER same, then LBER value incorrect. Also, value LBER should relied upon after BINIT# event. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
G14.
BTMs Corrupted During Simultaneous Cache Line Replacement
PROBLEM: When Branch Trace Messages (BTMs) enabled such message generated, Bcorrupted when issued cache line data brought into data cache simultaneously. Though line being stored cache stored correctly, corruption occurs data, information Bmay incorrect internal collision data line BTM.
IMPLICATION: Although BTMs entirely reliable this erratum, conditions necessary this boundary condition occur have only been exhibited during focused simulation testing. Intel currently observed this erratum system level validation environment. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
G15.
Near CALL Creates Unexpected Address
PROBLEM: documented, CALL instruction saves procedure linking information procedure stack jumps called procedure specified with destination (target) operand. target operand specifies address first instruction called procedure. This operand immediate value, general purpose register, memory location. When accessing absolute address indirectly using stack pointer (ESP) base register, base value used value register before instruction executes. However, when accessing absolute address directly using base register, base value used value after return value pushed stack, value register before instruction executed. IMPLICATION: this erratum, processor transfer control unintended address. Results unpredictable, depending particular application, range from effect unexpected
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
termination application exception. Intel observed this erratum only focused testing environment. Intel observed commercially available operating system, application, compiler that makes generates this instruction.
WORKAROUND: other seven general purpose registers unavailable use, necessary
CALL register, first push onto stack, then perform indirect call using (e.g., CALL [ESP]). saved version should then popped stack after call returns.
STATUS: steppings affected Summary Table Changes beginning this section.
G16.
Mixed Cacheability Lock Variables Problematic Systems
PROBLEM: This errata only affects multiprocessor systems where lock variable address marked cacheable
processor uncacheable others. processors which have marked uncacheable stall indefinitely when accessing lock variable. stall only encountered processor lock variable cached, attempting execute cache lock. processor which that address cached cached only. Other processors, meanwhile, issue back back accesses that same address bus.
IMPLICATION: systems where processors either cache locks consistent locks uncacheable
space will encounter this problem. however, lock variable's cacheability varies different processors, several processors attempting perform lock simultaneously, indefinite stall experienced processors which have marked uncacheable locking variable conditions above satisfied). Intel only encountered this problem focus testing with artificially generated external events. Intel currently identified commercial software which exhibits this problem.
WORKAROUND: Follow homogenous model memory type range registers (MTRRs), ensuring that
processors have same cacheability attributes each region memory; locks whose memory type cacheable processor, uncacheable others. Avoid page table aliasing, which produce nonhomogenous memory model.
STATUS: steppings affected Summary Table Changes beginning this section.
G17.
Parity Error Gives MCACOD.LL
PROBLEM: Cache Reply Parity (CRP) error, Cache Address Parity (CAP) error, Cache Synchronous Error (CSER) occurs access Pentium Xeon processor's cache, resulting Machine Check Architectural Error Code (MCACOD) will logged with `01' field. This value indicates cache error; value should `10', indicating cache error. Note that errors have correct value `10' logged. IMPLICATION: cache access error, other than error, will improperly logged cache error MCACOD.LL. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
G18.
Memory Type Field Undefined Nonmemory Operations
PROBLEM: Memory Type field nonmemory transactions such Special Cycles undefined.
Although Memory Type attribute nonmemory operations logically should (and usually does) manifest itself this feature designed into implementation therefore inconsistent.
IMPLICATION: agents decode non-UC memory type nonmemory transactions. WORKAROUND: agents must consider transaction type determine validity Memory Type field
transaction.
STATUS: steppings affected Summary Table Changes beginning this section.
G19.
Infinite Snoop Stall During Initialization Systems
PROBLEM: possible snoop traffic generated system while processor executing cache initialization routine cause initializing processor hang. IMPLICATION: system which does suppress snoop traffic while caches being initialized hang during this initialization sequence. WORKAROUND: System BIOS create execution environment which allows processors initialize their caches without system generating snoop traffic bus.
Below pseudo-code fragment, designed explicitly processor system, that uses serial algorithm initialize each processor's cache: Suppress_all_I/O_traffic() while Obtain current value This forces both Temp into cache. Note that Temp could also maintained general purpose register. Temp logical_proc_APIC_id wait_10_usecs_delay_loop(); this time delay, required worst case, allows barrier semaphore settle shared state. Initialize cache else while (Temp This algorithm prevents snoop traffic from other processors, which would otherwise cause initializing processor hang. algorithm assumes that cache enabled (the Temp variables must cached each processor). Also, Memory Type Range Register (MTRR) data segment must (writeback) memory type.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
G20.
Data Operand Pointer Zero After Power Reset
PROBLEM: Data Operand Pointer, specified, should reset zero upon power Reset
processor. this erratum, Data Operand Pointer nonzero after power Reset.
IMPLICATION: Software which uses Data Operand Pointer count value being zero after power Reset without first executing FINIT/FNINIT instruction will incorrect value, resulting incorrect behavior software. WORKAROUND: Software should follow recommendation Section Intel Architecture Software
Developer's Manual, Volume System Programming Guide (Order Number 243192). This recommendation states that will used, software-initialization code should execute FINIT/FNINIT instruction following hardware reset. This will correctly clear Data Operand Pointer zero.
STATUS: steppings affected Summary Table Changes beginning this section.
G21.
Premature Execution Load Operation Prior Exception Handler Invocation
PROBLEM: This erratum occur following situations:
instruction that performs memory load causes code segment limit violation, waiting floating-point instruction MMXinstruction that performs memory load floating-point exception pending, instruction that performs memory load either CR0.EM (Emulation set), floatingpoint Top-of-Stack TOS) equal exception pending. above circumstances occur, possible that load portion instruction will have executed before exception handler entered.
IMPLICATION: normal code execution where target load operation write back memory there
impact from load being prematurely executed, from restart subsequent re-execution that instruction exception handler. target load uncached memory that system sideeffect, restarting instruction cause unexpected system behavior repetition side-effect.
WORKAROUND: Code which performs loads from memory that side-effects effectively work around this
behavior using simple integer-based load instructions when accessing side-effect memory, ensuring that code written such that code segment limit violation cannot occur part reading from side-effect memory.
STATUS: steppings affected Summary Table Changes beginning this section.
G22.
EFLAGS Discrepancy Page Fault After Multiprocessor Shootdown
PROBLEM: This erratum occur when Pentium Xeon processor executes following readmodify-write arithmetic instructions page fault occurs during store memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, XADD. this case, EFLAGS value pushed onto stack page fault handler reflect status register after instruction would have completed execution rather than before following conditions required store generate page fault call operating system page fault handler:
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
store address entry must evicted from DTLB speculative loads from other instructions that same DTLB before store completed. DTLB eviction requires least three load operations that have linear address bits 15:12 equal each other address bits 31:16 different from each other close physical proximity arithmetic operation. page table entry store address must have permissions tightened during very small window time between DTLB eviction execution store. Examples page permission tightening include from Present Present from Read/Write Read Only, etc. Another processor, without corresponding synchronization flush, must cause permission change.
IMPLICATION: This scenario only occur multiprocessor platform running operating system that performs "lazy" shootdowns. memory image EFLAGS register page fault handler's stack prematurely contains final arithmetic flag values although instruction completed. Intel identified operating systems that inspect arithmetic portion EFLAGS register during page fault observed this erratum laboratory testing software applications. WORKAROUND: workaround needed upon normal restart instruction, since this erratum
transparent faulting code results correct instruction behavior. Operating systems ensure that processor currently accessing page that scheduled have page permissions tightened have page fault handler that ignores incorrect state.
STATUS: steppings affected Summary Table Changes beginning this section.
G23.
Read Portion Instruction Execute Twice
PROBLEM: When Pentium Xeon processor executes read-modify-write (RMW) arithmetic instruction, with memory destination, possible page fault occur during execution store memory operand after read operation completed before write operation completes. memory targeted instruction (uncached), memory will observe occurrence initial load before page fault handler again instruction restarted. IMPLICATION: memory targeted instruction side effects, then memory location will simply read twice with additional implications. however, load targets memory region that side effects, multiple occurrences initial load lead unpredictable system behavior. WORKAROUND: Hardware software developers write device drivers custom hardware that
have side effect style design should simple loads simple stores transfer data from device.
STATUS: steppings affected Summary Table Changes beginning this section.
G24.
MC2_STATUS Model-Specific Error Code Machine Check Architecture Error Code Reversed
PROBLEM: Intel Architecture Software Developer's Manual, Volume System Programming Guide,
documents that MCi_STATUS MSR, bits 15:0 contain (machine-check architecture) error code field, bits 31:16 contain model-specific error code field. However, MC2_STATUS MSR, these bits have been reversed. MC2_STATUS MSR, bits 15:0 contain model-specific error code field bits 31:16 contain error code field.
IMPLICATION: machine check error decoded incorrectly this erratum MC2_STATUS
taken into account.
WORKAROUND: When decoding MC2_STATUS MSR, reverse error fields.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
G25.
MOVD Following Zeroing Instruction Cause Incorrect Result
PROBLEM: incorrect result calculated after following circumstances occur:
register been zeroed with either reg, instruction reg, instruction, value moved with sign extension into same register's lower bits; signed integer multiply performed same register's lower bits, This register then copied MMXtechnology register using MOVD instruction prior other operations sign-extended value. Specifically, sign incorrectly extended into bits 16-31 MMXtechnology register. Only technology register affected this erratum. erratum only occurs when following steps occur order shown. erratum occur with intervening instructions that modify sign-extended value between steps EAX, EAX, MOVSX MOVSX byte <memory address> MOVSX MOVSX word <memory address> IMUL implicit, opcode IMUL byte <memory address> implicit, opcode IMUL (opcode IMUL word <memory address> (opcode IMUL (opcode IMUL word <memory address>, (opcode IMUL (opcode IMUL 1024 (opcode IMUL word <memory address>, 1024 (opcode IMUL 1024 (opcode MOVD MM0, Note that values immediate byte/words merely representative (i.e., 1024) that value range size affected. Also, note that this erratum occur with "EAX" replaced with 32-bit general purpose register, "AX" with corresponding 16-bit version that replacement. "BL" "BX" replaced with 8-bit 16-bit general purpose register. IMUL (opcode instructions specific register only. example, forced contain instructions. Since four types MOVSX IMUL instructions instruction modify only bits 15:8 sign extending lower eight bits EAX, bits 31:16 should always contain This implies that when MOVD copies MM0, bits 31:16 should also Under certain scenarios, bits 31:16 replicas (the 16th bit) This noticeable when value after MOVSX, IMUL instruction negative, i.e., When positive (bit MOVD will always produce correct answer. negative (bit MOVD produce right answer wrong answer depending point time when MOVD instruction executed relation MOVSX, IMUL instruction.
IMPLICATION: effect incorrect execution will vary from unnoticeable, code sequence discarding incorrect bits, application failure. technology-enabled application which MOVD used manipulate pixels, possible more pixels exhibit wrong color position momentarily. also possible computational application that uses MOVD instruction manner described above produce incorrect data. Note that this data cause unexpected page fault general protection fault. WORKAROUND: There possible workarounds this erratum:
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
Rather than using MOVSX-MOVD, IMUL-MOVD CBW-MOVD pairing handle variable time, sign extension capabilities (PSRAW, etc.) within MMXtechnology operating multiple variables. This would result higher performance well. Insert another operation that modifies copies sign-extended value between MOVSX/IMUL/CBW instruction MOVD instruction example below: EAX, EAX, EAX) MOVSX other MOVSX, other IMUL instruction) *MOV EAX, MOVD MM0, *Note: EAX, used here fairly generic. Again, 32-bit register.
STATUS: steppings affected Summary Table Changes beginning this section.
G26.
Entries Usable With Mode Mode Paging
PROBLEM: Page Attribute Table (PAT) contains eight entries, which must initialized considered when setting memory types Pentium Xeon processor. However, Mode Mode paging, four entries function correctly 4-Kbyte pages. Specifically, page table entries which translate addresses 4-Kbyte pages should used upper three-bit index determine entry that specifies memory type page. When Mode (CR4.PSE and/or Mode (CR4.PAE enabled, processor forces this zero when determining memory type, regardless value page table entry. upper four entries function correctly 2-Mbyte 4-Mbyte large pages (specified page directory entry those translations). IMPLICATION: Only lower four entries useful 4-Kbyte translations when Mode paging used. Mode paging (4-Kbyte pages only), eight entries used. eight entries also used large pages Mode paging. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
G27.
with Debug Register Causes Debug Exception
PROBLEM: When mode, instruction executed debug registers, general-protection exception (#GP) should generated, documented Intel Architecture Software Developer's Manual, Volume System Programming Guide, Section 14.2. However, case when general detect enable flag (GD) set, observed behavior that debug exception (#DB) generated instead. IMPLICATION: With debug-register protection enabled (i.e., set), when attempting execute
debug registers mode, debug exception will generated instead expected general-protection fault.
WORKAROUND: general, operating systems when they mode.
generally used debuggers. debug exception handler should check that exception occur mode before continuing. exception occur mode, exception directed general-protection exception handler.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
G28.
Data Breakpoint Exception Displacement Relative Near Call Corrupt
PROBLEM: data breakpoint programmed memory location where stack push near call performed, processor will update stack appropriately, skip code destination call. Hence, program execution will continue with next instruction immediately following call, instead target call. IMPLICATION: failure mechanism this erratum that call would taken; therefore, instructions
called subroutine would executed. result, code relying execution subroutine will behave unpredictably.
WORKAROUND: program data breakpoint exception stack where push near call
performed.
STATUS: steppings affected Summary Table Changes beginning this section.
G29.
System Functional With Ratio
PROBLEM: processor underclocked core frequency system frequency ratio system enabled, system detection correction will negatively affect internal timing dependencies. IMPLICATION: system enabled, processor underclocked ratio, system behave unpredictably these timing dependencies. WORKAROUND: agents that support system must disable when ratio used. STATUS: steppings affected Summary Table Changes beginning this section.
G30.
RDMSR WRMSR Invalid Address Cause Fault
PROBLEM: RDMSR WRMSR instructions allow reading writing MSRs (Model Specific Registers) based index number placed ECX. processor should reject access reserved unimplemented MSRs generating #GP(0). However, there some invalid addresses which processor will generate #GP(0). IMPLICATION: RDMSR, undefined values will read into EDX:EAX. WRMSR, undefined processor
behavior result.
WORKAROUND: invalid addresses with RDMSR WRMSR. STATUS: steppings affected Summary Table Changes beginning this section.
G31.
SYSENTER/SYSEXIT Instructions Implicitly Load "Null Segment Selector" Registers
PROBLEM: According processor specification, attempting load null segment selector into segment registers should generate General Protection Fault (#GP). Although loading null segment selector other segment registers allowed, processor will generate exception when segment register holding null selector used access memory.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
However, SYSENTER instruction implicitly load null value segment selector. This occur value SYSENTER_CS_MSR between FFF8h FFFBh when SYSENTER instruction executed. This behavior part SYSENTER/SYSEXIT instruction definition; content SYSTEM_CS_MSR always incremented before loaded into This operation will null segment selector null result generated, does generate SYSENTER instruction itself. exception will generated expected when register used access memory, however. SYSEXIT instruction will also exhibit this behavior both when executed with value SYSENTER_CS_MSR between FFF0h FFF3h, between FFE8h FFEBh, inclusive.
IMPLICATION: These instructions intended operating system use. this erratum occurs (and does ensure that processor never null segment selector segment registers), processor's behavior become unpredictable, possibly resulting system failure. WORKAROUND: initialize SYSTEM_CS_MSR with values between FFF8h FFFBh, FFF0h FFF3h, FFE8h FFEBh before executing SYSENTER SYSEXIT. STATUS: steppings affected Summary Table Changes beginning this section.
G32.
PRELOAD Followed EXTEST Does Load Boundary Scan Data
PROBLEM: According IEEE 1149.1 Standard, EXTEST instruction would data "typically loaded onto latched parallel outputs boundary-scan shift-register stages using SAMPLE/PRELOAD instruction prior selection EXTEST instruction." result this erratum, this method cannot used load data onto outputs. IMPLICATION: Using PRELOAD instruction prior EXTEST instruction will produce expected data
after completion EXTEST.
WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
G33.
Jump With D-bit Cleared Cause System Hang
PROBLEM: task switch performed executing jump through task gate Task State Segment (TSS) directly. Normally, when such jump occurs, D-bit (which indicates that page referenced Page Table Entry (PTE) been modified) which maps location previous will already processor will operate expected. However, D-bit clear time jump TSS, processor will hang. IMPLICATION: used which clear D-bit system pages, which jumps
task switch, then condition occur which results system hang. Intel identified commercial software which encounter this condition; this erratum discovered focused testing environment.
WORKAROUND: Ensure that code does clear D-bit system pages (including pages that contain task gate TSS). task gates rather than jumping when performing task switch. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
G34.
Illegal Opcode During Cache Initialization
PROBLEM: possible cache components 1-Mbyte 2-Mbyte Pentium Xeon processor
power state such that they synchronized. During read under these circumstances, data cache correct processor does read data correctly.
IMPLICATION: processor read invalid data after cache enabled during Power-On Self Test (POST) phase boot-up, most likely resulting invalid opcode being received processor, which would generate invalid opcode exception. WORKAROUND: Intel recommends that following BIOS instructions equivalent) added Intel Cache initialization module, just prior enabling cache BBL_CR_CTL3 [8]:
RDMSR PUSH PUSH WRMSR WRMSR ECX, 11Eh 0E1h 00Ah (11Eh) BBL_CR_CTL3 read contents save lower bits save upper bits isolate latency bits desktop latency value write value restore original value determined BIOS latency write back
IMPORTANT NOTE above example code contains stack operations. BIOS cache initialization code executed pre-stack environment, BIOS developer must ensure that push/pop instruction pairs replaced with another register save method. Also, BIOS developer must ensure that actual BIOS code does corrupt existing code's register usage.
STATUS: steppings affected Summary Table Changes beginning this section.
G35.
Incorrect Cache Line Invalidation
PROBLEM: event complex internal conditions processor invalidate cache line incorrectly. this line previously modified state, cache coherency maintained. Since timing critical these conditions occur, following sequence events MUST occur order encounter this erratum:
external snoop occurs. cache read miss occurs which generates cache read. This cache read miss, causing modified cache line scheduled eviction. cache write-back (resulting from separate transaction that happened before event different cache line occurs, which causes second cache miss. address same address first external snoop. Another external snoop occurs. Another cache read occurs; this read result either miss. modified cache line event written back main memory, invalidated. delay between event event causes processor invalidate wrong cache line.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
IMPLICATION: Stale data exist main memory because newer, modified data written back.
Depending significance this modified cache line, results unpredictable.
WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
G36.
Transmission Error Cache Read
PROBLEM: During reads cache, processor cache optimizations which result data
transmission error.
IMPLICATION: Data corruption caused this erratum will result unpredictable system behavior. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
G37.
COMISS/UCOMISS Update EFLAGS Under Certain Conditions
PROBLEM: COMISS/UCOMISS instructions compare least significant pairs packed single-precision
floating-point numbers bits EFLAGS register accordingly (the bits cleared). EFLAGS register contain appropriate value specified COMISS/UCOMISS operands under following conditions: source operand COMISS/UCOMISS instruction from memory that encounters some latency before available processor instruction subsequent COMISS/UCOMISS string instruction (e.g., MOVS) which completes before UCOMISS/COMISS instruction completes.
IMPLICATION: COMISS/UCOMISS instructions with register source operand unaffected this erratum. result incorrect status EFLAGS register range from effect unexpected application operating system behavior. WORKAROUND: possible BIOS code contain workaround this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
G38.
System Hang Occur With Core Ratio
PROBLEM: following conditions must occur this erratum observed:
Core frequency frequency ratio must 2:1. Chipset must most aggressive TRDY assertion allowed protocol. following instructions: movntq, movntps, maskmovq. large number back back stores memory.
IMPLICATION: occurrence this erratum cause system hang.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
WORKAROUND: core ratio. STATUS: steppings affected Summary Table Changes beginning this section.
G39.
Misaligned Locked Access APIC Space Results Hang
PROBLEM: When processor's APIC space accessed with misaligned locked access machine check
exception expected. However, processor's machine check architecture unable handle misaligned locked access.
IMPLICATION: this erratum occurs processor will hang. Typical usage models APIC address space locked accesses. Systems using such model will affected this erratum. WORKAROUND: Ensure that accesses APIC space aligned and/or locked. STATUS: steppings affected Summary Table Changes beginning this section.
G40.
Potential Loss Data Coherency During Data Ownership Transfer
PROBLEM: systems, processors sharing data different cache lines, referenced line line discussion below. When this erratum occurs (with following example given 2-way system with processors noted `P0' `P1'), contains shared copy line shared copy Line Each processor must manage necessary invalidation snoop cycles before that processor modify source results internal writes other processor.
There exists narrow timing window when, requests copy line supplied Exclusive state which allows modify contents line with further external invalidation cycles. this narrow window also retire instructions that original data present before performed modification.
IMPLICATION: Multiprocessor threaded application synchronization, required level data sharing, that
implemented operating system provided synchronization constructs affected this erratum. Applications which rely upon usage locked semaphores rather than memory ordering also unaffected. Uniprocessor systems affected this erratum. existence this erratum discovered during ongoing design reviews been reproduced environment. Intel identified, date, commercially available application operating system software which affected this erratum. erratum does occur processor execute software with stale data that present from previous shared state rather than data written more recently another processor.
WORKAROUND: Deterministic barriers beyond which program variables will modified achieved
usage locked semaphore operations. These should effectively prevent occurrence this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
G41.
Instruction Handler Execution Could Generate Debug Exception
PROBLEM: processor's general detect enable flag explicit call made interrupt
procedure instruction, general detect enable flag should cleared prior entering handler. result this erratum, flag cleared prior entering handler. access made debug registers while inside handler, state general detect enable flag will cause second debug
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
exception taken. second debug exception clears general detect enable flag returns control handler which able access debug registers.
IMPLICATION: This erratum will generate unexpected debug exception upon accessing debug registers while inside handler. WORKAROUND: Ignore second debug exception that taken result this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
G42.
Memory Ordering Based Synchronization Cause Livelock Condition Systems
PROBLEM: environment, following sequence code similar code) processors cause them each enter infinite loop (livelock condition):
[xyz], [abc], val1 wait0: EBX, [abc] EBX, val2 wait0(9) NOTE general-purpose register. Addresses [abc] [xyz] location memory must same bank cache. Variables "val1" "val2" integer. algorithm above involves processors each which loops keep them synchronized with each other. looping until instruction globally observed. Likewise, will loop until instruction globally observed. architecture allows instructions dispatched cache simultaneously. instructions accessing same memory bank cache, load will given higher priority will complete, blocking instruction (1). Instructions then execute retire, placing instruction pointer back instruction (7). This condition "wait0" loop being false. livelock scenario occur timing wait0 loop execution such that instruction ready completion every time that instruction tries complete. Instruction will again have higher priority, preventing data ([xyz]) instruction from being written cache. This causes instruction complete sequence "wait0" loop infinitely livelock condition also occurs because instruction does complete (blocked instruction completing). problem with this scenario that should eventually allow instruction write [abc], val2 wait1: EBX, [abc] EBX, val1 wait1
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
data cache. this occurs, data instruction will written memory, allowing conditions both loops true.
IMPLICATION: Both processors will stuck infinite loop, leading hang condition. Note that
receives interrupt, loop timing will disrupted such that livelock will broken. system timer, keystroke, mouse movement provide interrupt that will break livelock.
WORKAROUND: LOCK instruction force execute instruction before instruction (7). STATUS: steppings affected Summary Table Changes beginning this section.
G43.
Floating Point Exception Signal Deferred
PROBLEM: clock window exists where pending exception that should signaled
execution CVTPS2PI, CVTPI2PS, CVTTPS2PI instruction deferred next waiting floating point instruction instruction that would change register state.
IMPLICATION: this erratum occurs floating point exception will handled expected. WORKAROUND: Applications that follow Intel programming guidelines (empty registers before executing technology instructions) will affected this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
G44.
System Address Parity Checking Report False AERR#
PROBLEM: processor's address parity error detection circuit fail meet frequency timing
specification under certain environmental conditions. high temperature specification and/or voltage range, processor report false address parity errors.
IMPLICATION: system AERR# drive enabled (bit EBL_CR_POWERON resister `1')
spurious address detection reporting occur. some system configurations BINIT# asserted system bus. This cause some systems generate machine check exception others cause reboot.
WORKAROUND: Disable AERR# drive from processor. AERR# drive disabled clearing
EBL_CR_POWERON register. addition, chipset allows, AERR# drive should enabled from chipset AERR# observation enabled processor. AERR# observation processor enabled asserting active-to-inactive transition RESET#.
STATUS: processor part numbers affected "Pentium® XeonProcessor Identification
Packaging Information" table General Information section.
G45.
Processor Assert DRDY# Write with Data
PROBLEM: When MASKMOVQ instruction misaligned across chunk boundary that chunk
mask 0's, processor will initiate partial write transactions with having byte enables deasserted. Under these conditions, expected behavior processor would perform both write transactions, deassert DRDY# during transaction which byte enables asserted. result this erratum, DRDY# asserted even though data being transferred.
IMPLICATION: implications this erratum depend agents ability handle this erroneous DRDY#
assertion. agent cannot handle DRDY# assertion this situation, attempts invalid data during this transaction, unpredictable system behavior could result.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
WORKAROUND: system which accept DRDY# assertion during write with data will affected this erratum. addition, this erratum will occur MASKMOVQ aligned. STATUS: steppings affected Summary Table Changes beginning this section.
G46.
Thermal Sensor Leakage Current Exceed Specification
PROBLEM: thermal sensor Pentium Xeon processor cartridge violates maximum input leakage
current specification Table Pentium® XeonProcessor datasheet (10µA).
IMPLICATION: thermal sensor incorporates input protection diodes SMBCLK SMBDAT signals protection. protection diodes potentially clamp these lines ~0.6 when VCCSMBus voltage supply cartridge powered off. Hence, when VCCSMBus powered down, Pentium Xeon processor thermal sensor prevent SMBus transactions originating from SMBus devices powered different voltage source, same SMBus, from occurring. SMBus devices that powered from different voltage power planes typically located same SMBus. Designs using this isolation technique will affected this erratum. WORKAROUND: desired have SMBus devices powered source other than VCCSMBus, these devices must isolated from Pentium Xeon processor SMBus ensure that this erratum does occur. STATUS: processor part numbers affected "Pentium® XeonProcessor Identification
Packaging Information" table General Information section.
G1AP. APIC Access Cacheable Memory Causes Shutdown
PROBLEM: APIC operations which access memory with type other than uncacheable (UC) illegal. APIC operation memory type other than occurs Machine Check Exceptions (MCEs) disabled, processor will enter shutdown after such access. MCEs enabled, will occur. However, this circumstance, second will signaled. second signal will cause Pentium Xeon processor enter shutdown. IMPLICATION: Recovery from access cacheable memory will successful. Software that
accesses only type memory during APIC operations will encounter this erratum.
WORKAROUND: Ensure that memory space which accesses made marked type
(uncacheable) memory type range registers (MTRRs) avoid this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
G2AP. Systems Hang Catastrophic Errors During Determination
PROBLEM: systems, catastrophic error during bootstrap processor (BSP) determination process should cause assertion IERR#. catastrophic error APIC data being stuck electrical zero, then system hangs without asserting IERR#. IMPLICATION: systems hang during boot catastrophic error. This erratum been observed date typical commercial system, found during focused system testing using grounded APIC data bus. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
G3AP. Write Mask (Programmed EXTINT) Will Deassert Outstanding Interrupt
PROBLEM: APIC subsystem configured Virtual Wire Mode implemented through local APIC, (i.e., 8259 INTR signal connected LINT0 LVT1's interrupt delivery mode field programmed EXTINT), write LVT1 intended mask interrupts will deassert internal interrupt source external LINT0 signal already asserted. interrupt will erroneously posted Pentium Xeon processor despite attempt mask LVT. IMPLICATION: Because masking attempt, interrupts generated when system software expects
interrupts posted.
WORKAROUND: Software issue write 8259A interrupt mask register deassert LINT0 interrupt
level, followed read controller ensure that LINT0 signal been deasserted. Once this ensured, software then issue write mask entry
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
DOCUMENTATION CHANGES
Documentation Changes listed this section apply Pentium® XeonProcessor datasheet Intel Architecture Software Developer's Manual, Volumes NOTE Documentation Changes previously listed this section have been incorporated into updated version Intel Architecture Software Developer's Manual, Volumes (Order Numbers 243190-002, 243191-002, 243192-002, respectively). updated versions ordered contacting Intel Literature Center.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
SPECIFICATION CLARIFICATIONS
Specification Clarifications listed this section apply Pentium® XeonProcessor datasheet Intel Architecture Software Developer's Manual, Volumes NOTE Specification Clarifications previously listed this section have been incorporated into updated version Intel Architecture Software Developer's Manual, Volumes (Order Numbers 243190-002, 243191-002, 243192-002, respectively). updated versions ordered contacting Intel Literature Center.
PENTIUM® XEONPROCESSOR SPECIFICATION UPDATE
SPECIFICATION CHANGES
Specification Changes listed this section apply Pentium® XeonProcessor datasheet Intel Architecture Software Developer's Manual, Volumes
Locks Across Cache Line Boundary Disable Added
Pentium Xeon processor, setting Model Specific Register (MSR) address will prevent LOCK# from being asserted when locked transactions which split across cache line boundary issued from processor. This disabled default. default state (`0'), unaligned data issued locked sequence processor will have atomicity with LOCK# signal asserted. When set, transactions issued which split cache line boundary will have LOCK# signal asserted, atomicity guaranteed between reads writes sequence. Locked sequences which split cache line boundary will still follow normal LOCK# protocol with this set. Pentium® XeonProcessor Stepping 500-MHz 550-MHz 500-MHz 550-MHz
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