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Pentium® Processor Mobile Module: Embedded Module Connector (EMC-2) Design Guide
Order Number: 273212-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Mobile Pentium® Processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com.
Copyright Intel Corporation, 1998 *Third-party brands names property their respective owners.
Pentium® Processor Mobile Module Design Guide
Contents
Introduction
Terms Overview Related Documents.11 Mobile Pentium® Processor Intel® 440BX AGPset 2.2.1 System Interface 2.2.2 DRAM Interface.13 2.2.3 Accelerated Graphics Port Interface 2.2.4 Interface 2.2.5 System Clocking.13 Xcelerator (PIIX4E).14 DRAM Interface Overview.14 3.1.1 Groups 3.1.2 Single DRAM Interface 3.1.2.1 DRAM 3.1.2.2 SDRAM DRAM Layout Guidelines 3.2.1 SODIMM Connection DRAMs 3.2.2 SODIMM Connection SDRAM 3.2.3 Memory Trace Lengths Module Design SODIMM DRAM Organization.23 3.3.1 64-Mbit SDRAM System Examples.23 Clocking System Overview.25 Clock Synthesizer Pinout Specifications Timing Guidelines.27 Clock Layout Guidelines.28 Optional Clock Layout Clock Vendors Layout Routing Guidelines 5.1.1 On-board Compliant Device Layout Guidelines.31 5.1.1.1 Data Strobe Signal Routing Recommendations 5.1.1.2 Control Signal Routing Recommendations ACPI Compliance Requirements.33 IDSEL Routing Resistor Values EMC-2 Design Checklist
Design Features
Memory Guidelines
Clocking Guidelines
82443BX Interface EMC-2 Design
Design Guideline Checklists
Pentium® Processor Mobile Module Design Guide
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7
EMC-2 Errata Power Ground Pins Decoupling Requirements Clock Test Signals SDRAM Signals. Module Strapping Options. Signals 6.2.7.1 Design Considerations 6.2.8 Processor/PIIX4E Bridge Sideband Signals. 6.2.9 Power Management Signals 6.2.10 Signals 82371EB (PIIX4E) Design Checklist. 6.3.1 82371EB (PIIX4E) Errata 6.3.2 Power Ground Pins 6.3.3 Clock Test Signals 6.3.4 Signals 6.3.5 ISA/EIO Signals 6.3.6 Power Management Signals 6.3.7 Interface. 6.3.8 Interface 6.3.9 BIOS Flash Memory Interface PIIX4E Power Sequencing. 7.1.1 Power Sequencing Requirements. 7.1.2 Suspend/Resume Power Plane Control. 7.1.2.1 Power Suspend (POS) System Model 7.1.2.2 Suspend (STR). 7.1.2.3 Suspend Disk (STD) Soft (SOff). 7.1.2.4 Mechanical (MOff) 7.1.3 System Resume 7.1.3.1 System Resume Events 7.1.3.2 Global Standby Timer Resume 7.1.4 System Suspend Resume Control Signaling 7.1.4.1 Power Well Reset Signal Timings 7.1.4.2 PIIX4E Power Well Timings 7.1.4.3 RSMRST# PWROK Timing. 7.1.4.4 Suspend Well Power RSMRST# Activated Signals 7.1.4.5 Clock Control Timings 7.1.4.6 Core Well Power PWROK Activated Signals (RSMRST# Inactive Before Core Well Power Applied) 7.1.4.7 Core Well Power PWROK Activated Signals (Core Well Power Applied Before RSMRST# Inactive). 7.1.5 Power Management State Transition Timings 7.1.5.1 Mechanical 7.1.5.2 7.1.5.3 (with Processor Reset). 7.1.5.4 (with Processor Reset). 7.1.5.5 Reset). 7.1.5.6 7.1.5.7 7.1.5.8 STD/SOff
Power Sequencing.
Pentium® Processor Mobile Module Design Guide
7.1.5.9 STD/SOff 82443BX Host Bridge Controller Power Sequencing 7.2.1 Power Sequencing Requirements.69 7.2.2 440BX AGPset Power Management 7.2.2.1 System Power Modes 7.2.2.2 System Power-up Sequencing 7.2.2.3 Suspend Resume Protocols 7.2.2.4 82443BX Suspend/Resume Sequences Timing 7.2.2.5 Suspend/Resume with PCIRST# Active 7.2.2.6 Suspend/Resume with inactive PCIRST#, CPURST# 7.2.2.7 Suspend/Resume with CPURST Active, PCIRST# Inactive 7.2.2.8 Suspend/Resume from EMC-2 Power Sequencing 7.3.1 Voltage Regulator Control 7.3.2 Voltage Signal Definition Sequencing
Figures
EMC-2/440BX AGPset System Block Diagram.10 DRAM On-board Bank, SODIMMs DRAM SODIMMs DRAM Three SODIMMs.19 SDRAM On-board Bank, SODIMMs.20 SDRAM SODIMMs.21 SDRAM Three SODIMMs Clock Connections EMC-2 Module Pinout CK100-M Compatible Clock Synthesizer.26 Pinout CKBF-M Compatible Clock Buffer Timing Specifications Layout.27 EMC-2 Clocking Layout.29 General Clock Layout.30 On-board Compliant Device Layout Guidelines.31 Signal Layout Recommendations.32 Pull-up Resistor Example Clock Design Block Diagram.44 VREF Supply Schematic PIIX4E Power Well Timings RSMRST# PWROK Timings Suspend Well Power RSMRST# Activated Signals Clock Stop Timing Clock Start Timing Core Well Power PWROK Activated Signals (RSMRST# Inactive before Core Well Power Applied) Core Well Power PWROK Activated Signals (Core Well Power Applied before RSMRST# Inactive) Mechanical On.57 (with Processor Reset).59 (with Processor Reset).60
Pentium® Processor Mobile Module Design Guide
Reset) STD/SOff STD/SOff REFVCC5 Supply Circuit Schematic System Power-up Sequencing. Suspend/Resume with PCIRST# Active Suspend/Resume with CPURST, PCIRST# Inactive. Suspend/Resume with Inactive PCIRST Active CPURST# Suspend/Resume from Power Sequence
Tables
Related Intel Documents. Related Specifications. Trace Lengths DRAM Interface SODIMM DRAM Organization System Examples Supporting 64-Mbit SDRAM. Timing Specifications Maximum Minimum Clock Skews EMC-2 Clocking Trace Layout Specifications Clock Vendors. Data Associated Strobe Motherboard Recommendations Control Signal Line Length Recommendations. Module Capacitive Decoupling Requirements Clock Test Signal Resistor Values SDRAM Signal Resistor Values EMC-2 Strapping Options Signals Resistor Values Sideband Signal Resistor Values. Power Management Signals Resistor Values Signals Resistor Values. PIIX4E Power Signal Assignments Clock Test Signal Resistor Values Signal Resistor Values. ISA/EIO Signal Resistor Values Power Management Signal Resistor Values. Interface Signal Resistor Values Power State Decode Resume Events Supported Different Power States Resume Event Programming Model Power Plane Control Power Plane Control Using SUS[C:A]# Signals. PIIX4E Power Well Timings RSMRST# PWROK Timing. Suspend Well Power RSMRST# Timing.
Pentium® Processor Mobile Module Design Guide
Core Well Power PWROK Timing Core Well Power PWROK Timing Mechanical Timing.57 Timing Timing (with Processor Reset) Timing.60 Reset) Timing.61 Timing.63 Timing.64 STD/SOff Timing STD/SOff Timing System-wide Low-power Modes System Power-up Sequencing Timing Suspend Resume Events Activities 443BX Signal States During Modes Suspend/Resume Timing Voltage Signal Definitions Sequences
Revision History
Revision Date October 1998 Notes First release this document.
Pentium® Processor Mobile Module Design Guide
Introduction
This document provides design guidelines developing systems based Pentium® Processor Mobile Module: Embedded Module Connector MHz. System board memory subsystem design guidelines included. Special design recommendations concerns presented. Likely design errors have been listed here checklist format. These recommendations only. recommended that perform your simulations meet designspecific requirements.
Terms
EMC-2 refers Embedded Module Connector-2. This module identical Intel® Pentium® Processor Mobile Module Connector (MMC-2). complete description this module located Intel® Pentium® Processor Mobile Module: Mobile Module Connector (MMC-2) datasheet Intel 440BX AGPset refers both 82443 Host Bridge Controller 82371EB Xcelerator. 82443BX refers Intel 82443BX Host Bridge Controller. PIIX4E refers Intel 82371EB Xcelerator. Design Features items that allow designer fully capabilities mobile Pentium® processor Intel 440BX AGPset. Design Checklists items which provide recommendations designing EMC-2-based platform. Design Considerations items that should considered applicable your design.
Overview
EMC-2 module features summarized below. Figure block diagram typical EMC-2 system design.
Full support mobile Pentium® processors with system frequencies Intel 440BX AGPset
82443BX Host Bridge Controller (443BX) 82371EB Accelerator (PIIX4E)
memory interface: wide range DRAM support including:
64-bit memory data interface plus bits hardware scrubbing DRAM SDRAM support Mbit Mbit DRAM technologies
masters
Specification Compliant
Pentium® Processor Mobile Module Design Guide
Accelerated Graphics Port (AGP) Slot:
Interface Specification Revision compliant 66/133 MHz, 3.3-V device support
Integrated controller with Ultra DMA/33 support
Mode transfers master support
Integrated Universal Serial (USB) controller with ports Integrated System Power Management support
Figure EMC-2/440BX AGPset System Block Diagram
EMC-2
Mobile Pentium® Processor @266
PROCESSOR
Processor Interface
DRAM SDRAM
Enabled Interface
Mobile
443BX
mBGA
Slots
Device
PCI-0
MHz)
Master
PIIX4E
mBGA
GPIO (30+) SMBus
(5-V Tolerant)
Ultra DMA/33
Audio MicroController
Serial Port Parallel Port Floppy Disc Infrared
Keyboard
BIOS
A6058-02
Pentium® Processor Mobile Module Design Guide
Table
Related Documents
Related Intel Documents
Document Order Number 243668 243887 290633 243867 290635 290562 243190 243191 243192 243006 241618 243330 243331 243332 243334
Intel® Pentium® Processor Mobile Module (MMC-2) datasheet Mobile Pentium® Processor Specification Update Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet
PIIX4 Universal Serial Design Guide CK97 Clock Synthesizer Design Guidelines application note Intel® 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4E) Specification Update Intel® Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet Architecture Software Developer's Manual, Volume Basic Architecture
Intel® Architecture Software Developer's Manual, Volume Instruction Reference Intel® Intel® Architecture Software Developer's Manual, Volume System Programming Guide Architecture MMXTechnology Developer's Guide
AP-485 Intel Processor Identification CPUID Instruction application note AP-585 Pentium® Processor Guidelines application note AP-586 Pentium® Processor Thermal Design Guidelines application note AP-587 Slot Processor Power Distribution Guidelines application note AP-589 Slot Processor Overview application note documents only available through Intel Field Sales Representative.
Table
Related Specifications
Document Local Specification, Revision Universal Serial Specification, Revision Interface Specification, Revision Platform Design Guide, Revision 1.1A Information Technology Attachment with Packet Interface Extension (ATA/ATAPI-4) System Management Specification 66MHz Unbuffered SDRAM 64-bit (Non-ECC/Parity) 144pin SO-DIMM Specification, Revision URL/Contact http://www.sbs-forum.org/ Contact Intel Field Sales Representative
Pentium® Processor Mobile Module Design Guide
Design Features
Mobile Pentium® Processor
mobile Pentium processor first Pentium processor family offered embedded platform. offered with speed MHz. consists mobile Pentium processor core with integrated second-level cache controller 64-bit highperformance host bus. mobile Pentium processor private second-level cache that allows high-performance 64-bit wide cache subsystem gluelessly implemented using BSRAM devices. mobile Pentium processor cache Mbytes memory using Kbytes BSRAM. private second level cache complements host providing critical data faster, improving performance, reducing total system power consumption. mobile Pentium processor's 64-bit wide Power GTL+ host compatible with 440BX AGPset provides glueless, point-to-point interface bridge memory controller.
Intel® 440BX AGPset
Intel® 440BX AGPset based Pentium processor architecture. interfaces with mobile Pentium processor's system MHz. Along with Host-to-PCI bridge interface, 82443BX host bridge controller been optimized with SDRAM memory controller data path unit. 82443BX also features Accelerated Graphics Port (AGP) interface. 82443BX component includes following functions capabilities:
64-bit Power GTL+ based system data interface 32-bit system address support 64/72-bit main memory interface with optimized support SDRAM 32-bit interface with integrated arbiter interface with data transfer capability Extensive data buffering between interfaces high throughput concurrent operations
Figure shows block diagram typical platform based 440BX AGPset. 82443BX system interface supports mobile Pentium processor frequency MHz. physical interface design based Power GTL+ specification compatible with Intel 440BX AGPset. 440BX provides optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3-V DRAM technologies. 82443BX designed support PIIX4E bridge. PIIX4E highly-integrated multifunctional component that supports following functions capabilities:
Revision compliant PCI-to-ISA bridge with support operations ACPI Power Management support Enhanced controller, interrupt controller timer functions Integrated controller with Ultra DMA/33 support host interface with support ports System Management (SMB) with support DIMM Serial Presence Detect
Pentium® Processor Mobile Module Design Guide
2.2.1
System Interface
82443BX supports maximum Gbytes memory address space from processor perspective. largest address size bits. 82443BX provides control signals address paths transfers between processor bus, bus, Accelerated Graphics Port main memory. 82443BX supports 4-deep-in-order queue, which provides support pipelining four outstanding transaction requests system bus. mobile Pentium® processor supports second-level cache size Kbytes with ECC. cache-control logic provided processor. system bus-to-PCI transfers, addresses either translated directly forwarded bus, depending address space being accessed. When access configuration space, processor cycle mapped configuration space cycle. When access memory space, processor address passed without modification bus. Certain memory address ranges dedicated graphics memory address space. When this space portion mapped main DRAM, address translated address remapping mechanism request forwarded DRAM subsystem. portion graphics aperture mapped AGP, corresponding system cycles accessing that range forwarded without translation. address defines other system cycles that forwarded AGP.
2.2.2
DRAM Interface
82443BX integrates main memory controller that supports 64/72-bit DRAM interface which operates MHz. integrated DRAM controller features include:
3.3-V interface Support three double-sided SODIMMs
Mbytes Mbytes using 16-Mbit technology Mbytes using 64-Mbit technology
Support with hardware scrubbing 2.2.3 Accelerated Graphics Port Interface
82443BX supports interface. interface maximum theoretical transfer rate ~532 Mbytes/s.
2.2.4
Interface
82443BX interface operates MHz, Revision compliant, supports five external masters addition PIIX4E bridge. interface only 3.3-V. developer requires interface, level shifter implementation recommended.
2.2.5
System Clocking
82443BX operates system interface MHz, transfer rate 66/133 MHz. 82443BX clocking scheme uses external clock synthesizer that produces reference clocks system interfaces. 82443BX generates DRAM clock signals. Please refer CK97 Clock Synthesizer/Driver Specification (order number 243867).
Pentium® Processor Mobile Module Design Guide
Xcelerator (PIIX4E)
Xcelerator (PIIX4E) multi-function device that implements PCI-toISA bridge function, function, Universal Serial host/hub function, Enhanced Power Management function. Because PCI-to-ISA bridge, PIIX4E integrates many common functions found ISA-based systems; seven channel Controller, 82C59 Interrupt Controllers, 8254 Timer/Counter, Real Time Clock. addition Compatible transfers, each channel also supports Type transfers. PIIX4E contains full support PC/PCI Distributed protocols that implement PCIbased DMA. Interrupt Controller edge level sensitive programmable inputs. Chip select decoding provided BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, Programmable Chip Selects. PIIX4E provides full Plug-and-Play compatibility. PIIX4E configured subtractive decode bridge positive decode bridge. PIIX4E supports connectors. This provides interface IDE/EIDE hard disks CD-ROMs. four devices supported Master mode. PIIX4E contains support Ultra DMA/33 compatible synchronous devices. PIIX4E contains Universal Serial (USB) host controller that Universal Host Controller Interface (UHCI) compatible. host controller's root programmable ports. PIIX4E supports Enhanced Power Management, including full clock control, device management devices, suspend resume logic with Power Suspend, Suspend RAM, Suspend Disk. PIIX4E fully supports operating-system-directed power management according Advanced Configuration Power Interface (ACPI) specification. PIIX4E integrates both System Management (SMBus) host slave interface serial communication with other devices. more information PIIX4E, please refer 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet (order number 290562) 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4E) Specification Update (order number 290635).
Memory Guidelines
This section lists guidelines followed when routing signal traces board design. order which signals routed first last will vary from designer designer. Some designers prefer routing clock signals first, while others prefer routing high-speed signals first. Either order used, long guidelines listed here followed. When guidelines listed here followed, very important simulate design. Even when guidelines followed, recommended that simulate these signals proper signal integrity, flight time cross talk.
DRAM Interface Overview
82443BX integrates main memory DRAM controller that supports 64-bit DRAM array embedded environments. DRAM types supported Synchronous (SDRAM) Extended Data (EDO). 82443BX does support mixture SDRAM memory.
Pentium® Processor Mobile Module Design Guide
82443BX DRAM interface runs MHz. DRAM controller interface fully configurable through control registers. Complete descriptions these registers given Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet. 443BX supports industry standard 64-bit wide 144-pin SODIMM modules with SDRAM DRAM devices. Both symmetric asymmetric addressing supported. write operations less than Qword size, 443BX will either perform byte-wide write cycle (non-ECC protected configuration) read-modify-write cycle merging write data byte basis with previously read data (ECC error correction configurations). 82443BX requires DRAMs SDRAM with latency (CL2), supports 1-and 2-row SODIMMs. 82443BX provides refresh functionality with programmable rates (normal DRAM rate refresh/15.6 µs). When using SDRAM 82443BX configured paging policy register keep multiple pages open within memory array. Pages kept open rows memory. When using bank SDRAM devices particular row, pages kept open within that row. DRAM interface 82443BX configured DRAM control registers, DRAM timing register, SDRAM control register, bits NBXCFG register eight DRAM boundary (DRB) registers. DRAM configuration registers control DRAM interface select SDRAM, timing, rates. eight registers define size each memory array, enabling 82443BX assert proper CSA[7:0]#, CSB[7:0]# pair accesses array.
3.1.1
Groups
82443BX multiple copies many signals interfacing memory. However, EMC-2/440BX AGPset only supports single copy memory signals. "Single DRAM Interface" page more information. interface consists following pins: Multiple copies: MAA[13:0], MAB[12:11,9:0]# MAB[13, CSA[7:0]#, CSB[7:0]# SRASA#, SRASB# SCASA#, SCASB# WEA#, WEB# DQMA[7:0], DQMB[5:1] Single copies: CKE[5:0] (for three SODIMM configuration) MD[63:0] MECC[7:0] GCKE (for four DIMM configuration) FENA (FET switch control four DIMM configuration) CSA[7:0]#, CSB[7:0]# pins function RAS# pins case DRAMs. pins function CAS# pins case DRAMs. lines provided row. These functionally equivalent. extra copy provided loading reasons. SRAS#, SCAS# pins also functionally equivalent each copy drives rows DRAM. Most pins programmable strength output buffers. When contains 16-Mbit SDRAMs, MAA11 MAB11# function Bank Select lines. When contains 64-Mbit SDRAMs, MAA[12:0], MAB[12:11] function Bank Addresses (BA[1:0], Bank Selects). design
Pentium® Processor Mobile Module Design Guide
does support ECC, leave MECC[7:0] unconnected. When design supports ECC, perform simulations determine which buffer strength needed loading requirements. This require BIOS change.
3.1.2
Single DRAM Interface
following sections explain which signals used embedded platforms. Note that MAB[13,10] active because these address bits used define various SDRAM commands.
3.1.2.1
DRAM
Single copies used: MAB[12:11,9:0]# MAB[13,10] MD[63:0] MECC[7:0] RASA[5:0]# CASA[7:0]# WEA#
3.1.2.2
SDRAM
Single copies used: MAB[12:11,9:0]# MAB[13,10] MD[63:0] MECC[7:0] CSA[5:0]# DQMA[7:0] CKE[5:0] SRASA# SCASA# WEA#
Note:
DRAM Layout Guidelines
following DRAM layout guidelines intended with EMC-2 platforms that will only Host/SDRAM clock frequencies.
DRAM expansion socket embedded applications 144-pin SODIMM. MAB[11]# should connected SODIMM connector. MAB[12]# should connected SODIMM connector. MAB[13] should connected SODIMM connector. onboard 64-Mbit SDRAM devices motherboard, MAB[11]# should connected A13/BA0 SDRAM device, MAB[13] should connected SDRAM device.
Pentium® Processor Mobile Module Design Guide
memory data traces byte-swapped simplify board routing minimize
trace lengths. This should also done data bits within byte channel.
Board impedance should 15%. resistors should within tolerance. Trace widths memory signals should mil. Populate furthest SODIMM first avoid stub reflections. onboard memory should further away from EMC-2 module than SODIMM connectors. each other possible.
Place board DRAM connector, SODIMM connector, EMC-2 connector near 3.2.1 SODIMM Connection DRAMs
Figures show route EMC-2/440BX DRAM interface DRAM. Figure DRAM On-board Bank, SODIMMs
RASA[0]# RASA[2:1]# RASA[4:3]# RASA[5]#
MAB[12:11, 9:0]#, MAB[13,10]
443BX
CASA[7:0]# WEA#
MD[63:0] MECC[7:0] SRAS[B:A]# SCAS[B:A]# CKE0/FENA CKE[5:1] Note Note Note Note
WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals connected configuration. These signals used should left un-connected.
Note Note Note Note
SODIMM1 SODIMM0
On-Board
Pentium® Processor Mobile Module Design Guide
Figure DRAM SODIMMs
RASA[1:0]# RASA[3:2]# RASA[5:4]#
MAB[12:11, 9:0]#, MAB[13,
443BX
CASA[7:0]# WEA#
MD[63:0] MECC[7:0] SRAS[B:A]# SCAS[B:A]# CKE0/FENA CKE[5:1] Note Note Note Note
WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals connected configuration. These signals used should left un-connected.
Note Note Note Note
SODIMM1 SODIMM0
Pentium® Processor Mobile Module Design Guide
Figure DRAM Three SODIMMs
RASA[1:0]# RASA[3:2]# RASA[5:4]# MAB[12:11, 9:0]#, MAB[13,
443BX
CASA[7:0]# WEA#
MD[63:0] MECC[7:0] SRAS[B:A]# SCAS[B:A]# CKE0/FENA CKE[5:1] Note Note Note Note
WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals connected configuration. These signals used should left un-connected.
Note Note Note Note
SODIMM2 SODIMM1 SODIMM0
Pentium® Processor Mobile Module Design Guide
3.2.2
SODIMM Connection SDRAM
Figures show route EMC-2/440BX DRAM interface SDRAM.
Figure SDRAM On-board Bank, SODIMMs
CSA[0]# CSA[2:1]# CSA[4:3]# CSA[5]#
SRASA# SCASA#
DQMA[7:0]
443BX
WEA#
MAB[12:11, 9:0]#, MAB[13, MD[63:0] MECC[7:0] CKE[5] CKE[4:3] CKE[2:1] CKE[0] SRASB# SCASB# WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals used should left un-connected.
Note Note Note Note Note Note
SODIMM1
SODIMM0
On-Board
Pentium® Processor Mobile Module Design Guide
Figure SDRAM SODIMMs
CSA[1:0]# CSA[3:2]# CSA[5:4]#
SRASA# SCASA#
DQMA[7:0]
443BX
WEA#
MAB[12:11, 9:0]#, MAB[13, MD[63:0] MECC[7:0] CKE[5:4] CKE[3:2] CKE[1:0] SRASB# SCASB# WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals used should left un-connected.
Note Note Note Note Note Note
SODIMM1
SODIMM0
Pentium® Processor Mobile Module Design Guide
Figure SDRAM Three SODIMMs
CSA[1:0]# CSA[3:2]# CSA[5:4]#
SRASA# SCASA#
DQMA[7:0]
443BX
WEA#
MAB[12:11, 9:0]#, MAB[13, MD[63:0] MECC[7:0] CKE[5:4] CKE[3:2] CKE[1:0] SRASB# SCASB# WEB# CASB[5:1]#/DQMB[5:1] MAA[13:0] RASB[5:0]#/CSB[5:0]# Notes: These signals used should un-connected. Note Note Note Note Note Note
SODIMM2
SODIMM1
SODIMM0
3.2.3
Note:
Memory Trace Lengths Module Design
following DRAM layout guidelines intended with EMC-2 platforms that only Host/SDRAM clock frequencies. Table provides minimum maximum trace lengths SODIMM connector each signal group (excluding clock) each design. trace lengths clocks, "Clocking Guidelines" page memory configurations with on-board memory devices, signal traces should routed there were "phantom" connector board. designer should follow routing guidelines from 66MHz Unbuffered SDRAM 64-bit (Non-ECC/Parity) 144-pin SO-DIMM Specification, Revision 1.0, memory signals from "phantom" connector on-board memory devices (refer Table page 11). other words, route memory channel from 82443BX position that SODIMM0 would occupy your design following given constraints, route from that point onward according 66MHz Unbuffered SDRAM 64-bit (Non-ECC/ Parity) 144-pin SO-DIMM Specification.
Pentium® Processor Mobile Module Design Guide
Table
Trace Lengths DRAM Interface
Signal MAB[13:0]x, WEA#, SRASA#, SCASA# CKE[5:0] CSA/RASA[5:0]# CASA[7:0]#/DQMA[7:0]# MD[63:0], MECC[7:0] Min. Length inch inch inch inch inch Max. Length inch inch inch inch inch 203.2 228.6 228.6 228.6 203.2 Resistor System Electronics Board) NONE NONE NONE NONE
SODIMM DRAM Organization
144-pin SODIMM height) maximum capacity eight devices provides following configuration possibilities (see Table SDRAM EDO.
Table
SODIMM DRAM Organization
Technology Mbit SODIMM Organization Mbit Component Organization 2Mx8 8Mx8 Devices Mbyte SODIMM Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte Mbyte
NOTE: denotes single-sided SODIMMs. denotes double-sided SODIMMs.
3.3.1
64-Mbit SDRAM System Examples
Table lists five system examples. Each example based using three SODIMM sockets on-board DRAM SODIMM sockets. terms used Table defined below: SODIMM: Row: Technology: Density/Width: Devices/Row: Number SODIMM sockets plus on-board DRAM RAS[5:0]# CS[5:0]# connection. DRAM technology Mbit, Mbit DRAM configuration Mbit: Mbit: x16, Number DRAM components row.
Pentium® Processor Mobile Module Design Guide
Table
System Examples Supporting 64-Mbit SDRAM
SODIMM Technology Density Width Devices/Row Mbytes SODIMM
Example on-board Total Example on-board Total Example on-board Total Example on-board Total Mbit Mbit Mbit 8Mx8 8Mx8 8Mx8 Mbytes Mbytes Mbytes Mbytes Mbit Mbit Mbit 2Mx8 8Mx8 Mbytes Mbytes Mbytes Mbytes Mbit Mbit Mbit 2Mx8 2Mx8 2Mx8 Mbytes Mbytes Mbytes Mbytes Mbit Mbit Mbit Mbit 2Mx8 2Mx8 Mbytes Mbytes Mbytes Mbytes Mbytes
Pentium® Processor Mobile Module Design Guide
Clocking Guidelines
This section lists guidelines followed when routing signal traces board design. order which signals routed will vary from designer designer. Some designers prefer routing clock signals first, while others prefer routing high-speed signals first. Either order used, long guidelines listed here followed. When guidelines listed here followed, very important simulate design. Even when guidelines followed, recommended that simulate signals proper signal integrity, flight time cross talk.
Clocking System Overview
This section provides guidelines application information clock layout EMC-2/440BX AGPset system. These guidelines based HCLK, PCICLK SDRAMCLK requirements should implemented along with application instructions supplied your clock chip vendor. Figure shows clock synthesizer connection processor, 443BX, SDRAM when using EMC-2 module.
Figure Clock Connections EMC-2 Module
Mobile Pentium® Processor
HCLK 2.5V 66MHz HCLK DCLK DCLKRD DCLKWR SDRAM CLOCK BUFFER
Clock Synthesizer
HCLK
443BX
PCLK
SDRAM
PCLK 3.3V 33MHz Free running clock
PCLK
PIIX4E
Pentium® Processor Mobile Module Design Guide
Clock Synthesizer Pinout Specifications
clock synthesizer that meets CK97 Clock Synthesizer Design Guidelines (order number 243867) will meet requirement EMC-2/440BX AGPset-based system. Table page lists clock vendors that provide clock synthesizers which meet CK97 Clock Synthesizer Design Guidelines. Note: CK100-M compatible clock synthesizer operates multi-voltage mode. processor clocks operate clocks operate CKBF-M compatible clock buffer provides clocks SDRAM operating
Figure Pinout CK100-M Compatible Clock Synthesizer
XTAL_IN XTAL_OUT Vsspci0 PCICLK_F PCICLK1 Vddpci0 PCICLK2 PCICLK3 Vddpci1 PCICLK4 PCICLK5 Vsspci1 Vddcore0 Vsscore0
CK100-M
Vssref Vddref Vddcpu CPUCLK0 CPUCLK1 Vsscpu Vddcore1 Vsscore1 PCISTOP# CPUSTOP# PWRDWN# SEL100/66#
Figure Pinout CKBF-M Compatible Clock Buffer
Vdd0 Sdram0 Sdram1 Vss0 Vdd1 Sdram2 Sdram3 Vss1 buf_in Vdd4 Sdram16 Vss4 Vddiic Sdata
CKBF-M
Vdd9 Sdram15 Sdram14 Vss9 Vdd8 Sdram13 Sdram12 Vss8 Vdd5 Sdram17 Vss5 Vssiic Sclock
Pentium® Processor Mobile Module Design Guide
Timing Guidelines
Trace lengths should matched within clock signal groups minimize skew between copies clocks. This applies HCLK-to-HCLK PCICLK-to-PCICLK clock trace lengths.
Figure Timing Specifications Layout
Mobile Pentium® Processor 443BX GCLKIN GCLKO HCLKIN DCLKRD DCLKWR DCLKO
Device
SODIMM
SDRAM Component
PCLKIN
Clock Buffer Clock Synthesizer Device
Device
A6057-01
Figure shows simplified clocking layout timing specifications. recommended trace lengths given Note page Table clock skews.
Pentium® Processor Mobile Module Design Guide
Table
Timing Specifications Maximum Minimum Clock Skews
Symbol Description device (GCLK) 440BX AGPset (GCLKIN) skew 440BX AGPset (HCLK) (PCLK) skew (PCLK) (PCLK) skew DCLKWR SDRAM (SCLK) skew CK100-M Pin-to-Pin (max.) (min.) (max) (min) (max) -250 (min) Boards (max) (min) (max.) (min.) (max) -1.5 (min) (max) (min) Total (max) (min) (max.) (min.) (max) (min) (max) (min)
NOTES: 82443BX PCICLK input should HCLK input minimum maximum pins CK100-M device. integrated buffer offers best control over these output-to-output drive skews. This skew allowance includes ±280 capacitance SODIMM routing variation. Motherboards should allow more than ±100 contribution total skew.
Note:
Clock period, jitter, offset skew measured rising edge clock signals 1.25-V 2.5-V clocks 1.5-V 3.3-V clocks.
Clock Layout Guidelines
Series matching resistors required.
Resistor Value: Table Placement: near possible driver (less than
PCLK that used socket should point-to-point connection should
shared with another load.
When designing with expansion connector, remember account PCICLK trace
length docking station.
Route clocks internal layers provide better trace delay consistency
containment.
Board impedance should 15%. discrete resistors HCLK signals coming from CK100-M. Minimize vias clock signals. clocks should have width-to-spacing ratio. CKBF-M should rail CK100-M should V_3S rail (see "Power Ground Pins" page description these rails).
Pentium® Processor Mobile Module Design Guide
Figure EMC-2 Clocking Layout
Mobile Pentium Processor 443BX
GCLKO GCLKIN
Device
DCLKWR
DCLKRD
DCLKO
HCLK0
PCLK
HCLK1
CK100-M
2.5V 66MHz
Sdram
buf_in
SODIMM SODIMM SODIMM
CKBF-M
3.3V 33MHz
PCICLK_F
OTHER DEVICES
PIIX4E
Note: signals shown clarity
Table
EMC-2 Clocking Trace Layout Specifications
Variable (Notes (Notes Trace Width Minimum Trace Length inch inch B1+2.4 inch (B1+60.9 inch inch inch Maximum Trace Length inch (101.6 inch (101.6 B1+2.6 inch (B1+66 inch (A+101.6 inch (101.6 inch (25.4 inch (215.9 Tolerance (Note inch 2.54 inch 2.54 Resistor Value inch 114.3mm) None
NOTES: "Tolerance" refers allowed difference length between multiple traces sharing same variable name. platforms with on-board memory devices, clock traces should routed there were "phantom" connector board. designer should follow routing guidelines Unbuffered SDRAM 64-bit Non-ECC/Parity 144-pin SODIMM Specification clock signals from "phantom" connector on-board memory devices. other words, route clock trace position that SODIMM0 would occupy following constraints given above, route from that point onward according Unbuffered SDRAM 64-bit Non-ECC/Parity 144-pin SODIMM Specification. These layout guidelines intended only platforms which Host/SDRAM clocks MHz.
Pentium® Processor Mobile Module Design Guide
Optional Clock Layout
Figure General Clock Layout
Clock Driver Load
Note: signals shown clarity.
This optional layout implementation suggested accommodate clock tuning, HCLK PCICLK from CK100-M SCLK from CKBF-M. This will allow designer tune individual clock signals minimize allow variations impedance, skew loading. variables considered include:
Variation actual device load Line load impedance variation Driver output impedance Vendor variation
stub capacitor must minimized. maximum stub length clock trace inch. capacitor should placed close possible load. Refer specific clock vendors layout termination guidelines.
Table
Clock Vendors
Clock Vendors
Vendor Name Works, Inc. Address 3725 North First Street Jose, 95134 (408) 922-0202 Coches Street Milpitas, 95035 (408) 263-6300 1271 Parkmoor Avenue Jose, 95126-3448 (408) 925-9493 12020 113th Ave. Northeast Kirkland, 98034 (425) 398-3400
International Microcircuits, Inc.
Integrated Circuit Systems, Inc.
Cypress Semiconductor
Pentium® Processor Mobile Module Design Guide
82443BX Interface EMC-2 Design
This section lists guidelines followed when routing signal traces board design. Even when guidelines followed, recommended that simulate many signals possible proper signal integrity cross talk. Section 6.2.10, "AGP Signals" page pull-up requirements. Section 4.0, "Clocking Guidelines" page clocking information.
Layout Routing Guidelines
definition interface functionality (protocols, rules signaling mechanisms, platform level aspects functionality), refer latest Interface Specification Platform Design Guide. This document focuses only specific 440BX platform recommendations interface. Throughout this section term "data" refers G_AD[31:0], G_C/BE[3:0]# SBA[7:0]. term "strobe" refers AD_STB[B:A] SB_STB. When term "data" used, referring three groups data seen Table When term "strobe" used referring three strobes relates data associated group.
Table
Data Associated Strobe
Data G_AD[15:0] G_C/BE[1:0]# G_AD[31:16] G_C/BE[3:2]# SBA[7:0] Associated Strobe AD_STBA AD_STBB SB_STB
5.1.1
On-board Compliant Device Layout Guidelines
Longer trace lengths require greater amount spacing between traces order reduce crosstalk. When using spacing, maximum trace length data lines inches. line length mismatch inches. strobe longest trace group. This restricts maximum trace length data lines less than inches trace spacing. strobe requires trace spacing. Trace length guidelines given this section reflect signal integrity EMI. recommended that simulate routes ensure that signal quality requirements met.
Figure On-board Compliant Device Layout Guidelines
1.0" ting
EMC-2
lian
443BX I/AG
1.0" ting
Pentium® Processor Mobile Module Design Guide
Figure Signal Layout Recommendations
5.1.1.1
Data Strobe Signal Routing Recommendations
Table Motherboard Recommendations
Width:Space 1:1(Data)/1:2(Strobe) Trace Data /Strobe Data/Strobe Line Length line length line length Line Length Matching strobe longest trace strobe longest trace
line length mismatch must less than 0.5" strobe must longest signal group. example, strobe inches, data line from inches length. best reduce line length mismatch wherever possible insure added margin. strobe always required have trace spacing. also best separate traces much possible order reduce amount trace-to-trace coupling. Note: Under certain layouts, crosstalk ground bounce observed AD_STB signals interface. Although Intel observed system failures this issue, noise margin been improved enhancing buffers 82443BX. designs, additional margin obtained following layout guidelines.
5.1.1.2
Control Signal Routing Recommendations
Some control signals require pull-up resistors installed motherboard. Pull-up resistors should discrete resistors, since resistor packs will need longer stub lengths violate timing requirements. stub length these pull-up resistors must controlled. maximum stub length strobe trace inch. maximum stub trace length other traces inch. Pull-up recommendations, "AGP Signals" page Table Control Signal Line Length Recommendations
Width:Space Board Motherboard Motherboard Trace Control Signals Control Signals Line Length line length line length 10.0 Pull-up Stub Length (Strobes 0.1in) (Strobes 0.1in)
Pentium® Processor Mobile Module Design Guide
ACPI Compliance Requirements
Based Advanced Configuration Power Interface (ACPI) specification, graphics device must ACPI compliant must implement self power management circuitry, such self clock-gating idle detection mechanism reduce power. However, embedded Pentium® processor-based platform device clock derivative host clock. When host clock stops state Deep Sleep), clock also stops. AGP_BUSY# protocol solves this instantaneous stop clock problem. graphics device must signal operating system south bridge that currently busy clock should stopped. device internally protects core logic ensure that illegal clock will corrupt device state. This protection gates internal clock nets used device's logic from time STP_AGP# asserted until deasserted. STP_AGP# signal indication that clock will valid much longer should gated protection. STP_AGP# should connected PIIX4E's SUS_STAT1# signal. AGP_BUSY# signal indicates that graphics controller requires GCLK running. This signal should connected PIIX4E's PCIREQ# pins. When PCIREQ# must shared, logically ORed with PIIX4E's PCIREQ# inputs. AGP_BUSY# open-drain signal from graphics device requires Pull-up resistor. AGP_SUSPEND# devices that support Suspend mode. AGP_SUSPEND# signal connected PIIX4E's SUSB# signal.
IDSEL Routing
compliant master composed compliant target interface compliant master interface. (Optionally device also include compliant master interface when required.) When used mode operation, device must provide external IDSEL that connected AD16. When device designed exclusive operation interface device does have external IDSEL pin, therefore IDSEL does need routed.
Design Guideline Checklists
Design checklists provided this section intended used schematic reviews EMC-2 based platform designs. checklists represent only design system, provide recommendations. system designer should examine checklist items correctness. Additional design considerations also provided.
Resistor Values
Pull-up pull-down register values system dependent. appropriate value your system determined from AC/DC analysis pull-up voltage used, current drive capability output driver, input leakage currents devices signal net, pull-up voltage tolerance, pull-up/pull-down resistor tolerance, input high/low voltage specifications, input timing specifications rise time), etc. Analysis should done determine minimum
Pentium® Processor Mobile Module Design Guide
maximum values that used individual signal. Engineering judgment should used determine optimal value. This determination include cost concerns, commonality considerations, manufacturing issues, specifications other considerations. simplistic calculation pull-up value RMAX (VccPU MIN) ILeakage RMIN (VccPU MAX) Figure Pull-up Resistor Example
VccPU
RMAX ILeakage
VccPU
RMIN IOLMAX
EMC-2 Design Checklist ]Pass, ]Fail
PIIX4E recommendations system electronics board, please "82371EB (PIIX4E) Design Checklist ]Pass, ]Fail" page
6.2.1
EMC-2 Errata
Please Mobile Pentium® Processor Specification Update (order number 243887) workarounds errata that present stepping used.
6.2.2
Power Ground Pins V_DC voltage driven from power supply required between
21-V module cannot inserted removed while V_DC powered
V_3S SUSB#-controlled 3.3-V voltage supply which output voltage regulator
system electronics. This rail should during Suspend-to-RAM (STR), Suspend-toDisk (STD), Soft-Off (SOff) modes.
SUSC# controlled voltage supply which output voltage regulator
system electronics. This rail should during Suspend-to-Disk (STD), Soft-Off (SOff) modes.
SUSC# controlled voltage supply which output voltage regulator
system electronics. This rail should during Suspend-to-Disk (STD), Soft-Off (SOff) modes.
Pentium® Processor Mobile Module Design Guide
V_CPUPU driven EMC-2 power processor interface signals such PIIX4E
open-drain pull-ups processor/PIIX4E sideband signals.
V_CLK driven EMC-2 power HCLK drivers from CK100-M clock source. VCCAGP VDDQ voltage, should connected V_3. output DC-DC regulator EMC-2, driven core voltage
(VCC_CORE) processor. used implementations.
unused active 3.3-V tolerant inputs should connected V_3S with 10-K
resistor unless otherwise stated.
unused active high inputs should connected ground (VSS) through 10-K resistor
unless otherwise stated.
6.2.3
Decoupling Requirements
order provide adequate filtering in-rush current protection system design, bulk capacitance required. small amount bulk capacitance supplied EMC-2. achieve proper filtering, additional capacitance should placed system electronics. Table details bulk capacitance requirements system electronics when using EMC-2.
Table Module Capacitive Decoupling Requirements
Voltage Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Capacitance 0.01 0.01 Ripple Current Rating tolerance 35-V tolerance 10-V tolerance tolerance tolerance tolerance tolerance
0.01 0.01 0.01 8200
8200
NOTES: This capacitance should located near processor module connector. V_CPUPU V_CLK filtering should located next system clock synthesizer. Ripple current specification depends V_DC input. V_DC, device required. V_DC 18-V higher, sufficient.
6.2.4
Clock Test Signals "Clocking Guidelines" page clocking guidelines. discrete resistors HCLK signals from CK100-M. HCLK,
PCLK signals coming from CK100-M resistor packs.
should connected CK100-M provide host clock frequency.
CKBF-M should rail CK100-M should V_3S rail.
clock signal from CKBF-M SODIMM should have series termination
resistors.
CONFIG[1] should pulled V_3ALWAYS with 100-K resistor system I/O. CONFIG[2] should pulled 440BX AGPset based designs. weak 100-K
resistor used.
Pentium® Processor Mobile Module Design Guide
Table Clock Test Signal Resistor Values
Name HCLK PCLK DCLKO DCLKRD DCLKWR GCLKO GCLKIN SDRAM_CLK Termination Resistor (see above) (see above) None Pull-up (Pull-down) Resistor None None None None None None None None None
"Clock period, jitter, offset skew measured rising edge clock signals 1.25-V 2.5-V clocks 1.5-V 3.3-V clocks." page
6.2.5
SDRAM Signals "Memory Guidelines" page memory guidelines. MD[63:0] should have series termination resistors.
Table SDRAM Signal Resistor Values
Name MD[63:0] Termination Resistor Pull-up (Pull-down) Resistor None
6.2.6
Module Strapping Options MAB9# Disable strapping option EMC-2. This should pulled
with 10-K resistor when disabled.
Table EMC-2 Strapping Options
Name MAB9# Function Disable Enabled High Disabled Internal Resistor Pull-down Status Register PMCR[1]
6.2.7
Signals
"PCI Signals" page EMC-2 supports only 3.3-V PCI. pull-up V_3S should placed CLKRUN# signal. 82443BX does implement PERR# pin. Data parity errors still detected reported SERR# (when enabled SERRE PERRE).
Pentium® Processor Mobile Module Design Guide
6.2.7.1
Design Considerations
82443BX supports five masters with REQ[4:0]#/GNT[4:0]# pairs. supports loads. 82443BX PIIX4E each represent load; other components soldered motherboard load each; each connector adds approximately loads. design with four slots motherboard devices uses available loads. When five REQ[4:0]#/GNT[4:0]# pairs used, simulation required ensure that Specification Rev. timings met. recommended, specification, that design have series resistors (~100 each connector IDSEL lines. Table Signals Resistor Values
Name AD[31:0] C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# REQ[4:0]# GNT[4:0]# PHOLD# PHLDA# SERR# CLKRUN# PCIRST# PLOCK# Termination Resistor None None None None None None None None None None None None None None (see "PCI Signals" page None Pull-up (Pull-down) Resistor None None pull-up V_3S pull-up V_3S pull-up V_3S pull-up V_3S pull-up V_3S pull-up V_3S unused pull-up V_3S used pull-up V_3S pull-up V_3S None pull-up V_3S pull-up V_3S None pull-up
6.2.8
Processor/PIIX4E Bridge Sideband Signals Pull-ups V_CPUPU: INIT# STPCLK# LINT1#/NMI, LINT0#/INTR,
IGNNE#, A20M#, SMI# These open collector outputs from PIIX4E component.
CPURST left unconnected EMC-2 designs. Refer System Management Specification (see Table descriptions
specifications three SMBus signals: SMBALERT#, SMBCLK, SMBDATA. pullup resistor required. Values will vary depending actual capacitance bus.
Pentium® Processor Mobile Module Design Guide
Table Sideband Signal Resistor Values
Name FERR# CPURST IGNNE# INIT# INTR A20M# SMI# STPCLK# Termination Resistor None None None None None None None None None Pull-up (Pull-down) Resistor None None pull-up V_CPUPU pull-up V_CPUPU pull-up V_CPUPU pull-up V_CPUPU pull-up V_CPUPU pull-up V_CPUPU pull-up V_CPUPU
6.2.9
Power Management Signals MID[3:0] should have pull-up V_3S. BXPWROK must transition from inactive (low) active (high) minimum after
BX_VCC within specified Functional Operating Range. "82443BX Host Bridge Controller Power Sequencing" page more information.
Table Power Management Signals Resistor Values
Name SUS_STAT# VR_ON VR_PWRGD SM_CLK SM_DATA ATF_INT# MID[3:0] Termination Resistor None None None None None None None Pull-up (Pull-down) Resistor None None None Refer System Management Specification Refer System Management Specification Refer System Management Specification pull-up V_3S
6.2.10
Signals "82443BX Interface EMC-2 Design" page MAB9# strapping option 443BX system electronic board. This allows
designers enable disable AGP.
When disabled signals three-stated isolated. They need
external pull-up resistors.
Unconnected pins disabled interface: PIPE#, SBA[7:0], RBF#, ST[2:0], AD_STBA,
AD_STBB, SB_STB, G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_REQ#, G_GNT#, G_AD[31:0], G_C/BE[3:0]#, G_PAR.
graphic card must able signal operating system, south bridge, that
currently busy clock should stopped. "ACPI Compliance Requirements" page
Pentium® Processor Mobile Module Design Guide
LOCK# signal supported interface, even operations. signals that require pull-ups should discrete resistors resistor packs. When enabled following signals must have pull-up resistors
approximately VCCAGP ensure they contain stable values when agent actively driving bus: G_FRAME#, G_TRDY#, G_IRDY#, G_DEVSEL#, G_STOP#, SERR#, PERR#, RBF#, INTA#, INTB#, PIPE#, G_REQ#, G_GNT#, SB_STB, AD_STBA, AD_STBB.
GPAR requires pull-down resistor when design interfacing
connector, when compliant device uses PIPE# side band addressing. When compliant device uses GFRAME# only, pull-down resistor needed.
When side band addressing disabled, SBA[7:0] isolated external pull-ups
required.
When PIPE# used queue addresses master allowed queue addresses using
side band addressing bus.
external termination (for signal quality) required specification. Termination
added improve signal integrity, provided that performance (timing) constraints still satisfied.
interrupts shared with interrupts similar recommendations
Revision specification. example, system with three slots AGP, interrupts should connected such that each four INTA# lines connects unique input PIIX4E. recommended that interrupts staggered. also recommended that each PIRQ programmed different IRQ, possible.
system electronics (S.E.) board designer must properly interface interrupts
bus.
order minimize impact impedance mismatch between S.E. board
add-in card, impedance strongly recommended.
strobe signals must grouped with their associated data signals. AD_STBA with
G_AD[15:0], AD_STBB with G_AD[31:16], SB_STB with SBA[7:0]. Section 5.1, "Layout Routing Guidelines" page
Some onboard devices require their VREF. This should generated locally
from interface VCCAGP rail. should separate voltage divider from AGP_REF 82443BX. connect two. VCCAGP rail controller ring voltage supply. Table Signals Resistor Values (Sheet
Name GAD[31:0] GC/BE[3:0]# GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GREQ# Termination Resistor None None None None None None None None Pull-up (Pull-down) Resistor None None pull-up VCCAGP pull-up VCCAGP pull-up VCCAGP pull-up VCCAGP pull-up VCCAGP pull-up VCCAGP
Pentium® Processor Mobile Module Design Guide
Table Signals Resistor Values (Sheet
Name GGNT# GPAR PIPE# SBA[7:0] RBF# ST[2:0] ADSTB[B:A] SBSTB Termination Resistor None None None None None None None None Pull-up (Pull-down) Resistor pull-up VCCAGP pull-down device does GFRAME# ONLY) pull-up VCCAGP None pull-up VCCAGP None pull-up VCCAGP pull-up VCCAGP
6.3.1
82371EB (PIIX4E) Design Checklist ]Pass, ]Fail
82371EB (PIIX4E) Errata Please 82371EB (PIIX4E) Xcelerator Specification Update
workarounds errata that applicable stepping used.
6.3.2
Power Ground Pins V_3ALWAYS 3.3-V rail that connected VCC(SUS) PIIX4E. V_3ALWAYS
should power only when system mechanically off. PIIX4E core.
VCC(USB) must tied V_3S. VCC(USB) should tied same voltage rail VCC(RTC) should tied 3.3-V supply voltage logic. VREF must tied tolerant system. This signal must power before
simultaneous V_3S, must power down after simultaneous V_3S. Note that most devices operate even when running 3.3-V bus, PIIX4E interface must tolerant. devices.
VREF tied V_3S non-5-V tolerant system. devices generally VSS(USB) ground. unused active 3.3-V tolerant inputs should connected V_3S with 10-K
resistor unless otherwise stated.
unused active high inputs should connected ground (VSS) through 10-K resistor
unless otherwise stated.
Pentium® Processor Mobile Module Design Guide
Table PIIX4E Power Signal Assignments
Power Pins VCC(RTC) VCC(SUS) VCC(USB) VSS(USB) Ball Number E11, E12, E16, F14, F15, P15, R15, N16,R16 D10, E13, J9-J12, K9-K12, L9-L12, M9-M12
6.3.3
Clock Test Signals Clock clock with duty cycle better than 40/60% should into
PIIX4E's clock input,
Place 10-K pull-up resistor TEST# V_3ALWAYS. Test signals reside Suspend/
Resume well.
Pentium processor-based system, CONFIG[1] should pulled V_3ALWAYS with
100-K resistor.
CONFIG[2] should pulled with 100-K resistor 440BX AGPset-based
designs. Table Clock Test Signal Resistor Values
Name TEST# CONFIG[1] CONFIG[2] Termination Resistor None None None Pull-up (Pull-down) Resistor Pull-up V_3ALWAYS Pull-up V_3ALWAYS Pull-down
6.3.4
Signals unused general purpose inputs (GPIs) should pulled valid logic level with 10-K
resistor. When pulled high, they should pulled V_3S except GPIs that VCC(SUS) well.
unused outputs left no-connects. IDSEL signals should have 100-W series resistor each device. environment, place pull-up resistors PIRQ[A:D]#, SDONE,
SBO#, FRAME#, TRDY#, STOP#, IRDY#, DEVSEL#, PLOCK#, PERR#, SERR#, REQ64# ACK64# bus.
Place 10-K pull-up resistors V_3S PCIREQ[D:A]# REQ[A:C]# when these
signals unused when using add-in slot insure that these signals float.
3.3-V environment, place 10-K pull-up resistors V_3S PIRQ[A:D]#, SDONE,
SBO#, FRAME#, TRDY#, STOP#, IRDY#, DEVSEL#, PLOCK#, PERR#, SERR#, REQ64# ACK64# bus.
Pentium® Processor Mobile Module Design Guide
designs, make sure that PIIX4E does connect IDSEL AD12, becoming
device 82443BX, known device whether disabled not. Connect IDSEL from PIIX4E AD18.
systems which PCIRST# signal lightly loaded (<50 pF), place 33-W series
termination resistor this signal. This resistor should placed close possible PIIX4E. Table Signal Resistor Values
Name Unused GPIs IDSEL signals PIRQ[A:D]# SDONE SBO# FRAME# TRDY# STOP# IRDY# DEVSEL# PLOCK# PERR# SERR# REQ64# ACK64# PCIREQ[D:A]# REQ[A:C]# Termination Resistor None None None None None None None None None None None None None None None None Pull-up (pull-down) Resistor valid level None Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S
6.3.5
ISA/EIO Signals When implementing Power Suspend (POS) mode, signals should pulled
V_3S. Otherwise V_5S.
pull-up resistors SD[15:0], MEMR#, MEMW#, IOR#, IOW#, IOCS16#. pull-up resistors IOCHRDY, MEMCS16#, REFRESH#, ZEROWS#. pull-up resistors IRQx. IRQ8# resides VCC(SUS) well, must pulled
V_3ALWAYS. When IRQ8# used, default GPI[6] requires external pull-up resistor.
pull-down resistor DRQx. When using bus, IOCHK# becomes general-purpose input ISA, IOCHK#
requires pull-up resistor.
Pentium® Processor Mobile Module Design Guide
Table ISA/EIO Signal Resistor Values
Name SD[15:0] MEMR# MEMW# IOR# IOW# IOCS16# IOCHRDY MEMCS16# REFRESH# ZEROWS# IRQx DRQx SIRQ IOCHK# Termination Resistor None None None None None None None None None None None None None None Pull-up (Pull-down) Resistor Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S Pull-up V_3S (see above) (Pull-down) Pull-up V_3S Pull-up using bus)
6.3.6
Power Management Signals Power management signals that reside VCC(SUS) well require pull-ups, pullups must connected V_3ALWAYS. These signals support input levels.
EXTSMI# input reset open drain output when activating SMI# within
Serial function. Designers need pull-up V_3ALWAYS when always being driven valid state.
When CLKRUN# connected between PIIX4E 82443BX, should tied
through resistor 82443BX. When CLKRUN# connected between PIIX4E 82443BX, pull-up V_3S should placed CLKRUN# signal.
SUS_STAT1# connected between 82443BX PIIX4E. SUS_STAT2# connected from PIIX4E devices that must informed
stopping clocks.
PCI_STP# connected clock synthesizer stop clocks. CPU_STP# connected clock synthesizer stop processor clock. SUSA# connected clock synthesizer's PWR_DWN# through Schottky diode
with pull-up resistor. Alternatively, SUSA# used control clock synthesizer's power plane.
Pentium® Processor Mobile Module Design Guide
Figure Clock Design Block Diagram
chottky iode
100-M
chottky iode
SUSB# SUSC# used control power planes. THRM# connected thermal protection logic. PCIREQ[D:A]# connected between PIIX4E bus. master requests
considered power management events.
Connect modem when this feature used. Connect BATLOW# battery monitoring logic when this feature implemented. Connect monitoring logic system. PWRBTN# connected logic that allows user switch from suspend. RSMRST# connected switch allow complete system reset. This signal resides VCC(RTC) well. potential must exceed that VCC(RTC).
Table Power Management Signal Resistor Values
Name EXTSMI# CLKRUN# Damping Resistor None None Pull-up (Pull-down) Resistor above K~10 Pull-up V_3S connected from PIIX4E 82443BX) (Pull-down) otherwise
6.3.7
Interface Refer PIIX4 Design Guide (see Table layout recommendations USB,
clock, over-current detection circuit general board layout recommendations.
6.3.8
Interface pull-down resistors PDDREQ SDDREQ. pull-up resistors PIORDY SIORDY. pull-down resistor connector (CSEL). Support Cable Select
(CSEL) PC97 requirement. state cable select determines master/slave configuration hard drive cable.
primary connector uses IRQ14, secondary connector uses IRQ15.
Pentium® Processor Mobile Module Design Guide
ATA-4 specification requires series terminating resistors P/SDIOR, P/SDIOW#,
P/SDCS[1,3]#, P/SDA[2:0], P/SDDACK# P/SDD[15:0]. These series termination resistors should placed close possible PIIX4E.
Ultra-DMA enabled systems, ATA-4 specification also requires series
terminating resistors P/SDDREQ, INTRQx P/SIORDY. These series terminating resistors should placed close possible PIIX4E.
When distance between PIIX4E connector greater than terminating
resistor should placed within PIIX4E.
When using reset signal RSTDRV from PIIX4E, should routed through
Schmitt trigger RESET# signals.
Ground pins both connectors Pins both connectors should left unconnected. According ATA-4 specification, pull-down resistor required allow
host recognize absence device power-up.
Exceptions: When PIIX4E's interface configured Primary 0/Primary
devices connected, should appear devices they same cable. Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet (order number 290562). Both devices should connect IRQ14. CSEL connected (pin28) together between connectors pulled down with resistor meet PC97 requirement. DIAG (pin connected together between connectors. Table Interface Signal Resistor Values
Name PDDREQ SDDREQ PIORDY SIORDY CSEL (Pin signals connectors Termination Resistor Ultra DMA) Ultra DMA) (Ultra only) (Ultra only) None Pull-up (pull-down) Resistor (pull-down) (pull-down) Pull-up Pull-up (pull-down) None (pull-down)
6.3.9
BIOS Flash Memory Interface
Mbits flash usually that required support 82443BX configurations. These recommendations Intel 28F200BV flash part.
0.01 capacitors power supply (VCC VPP) decoupling. Connect BYTE# when flash device used configure GPOx control signal. Connect 5-V. GPOx control signal.
Pentium® Processor Mobile Module Design Guide
Power Sequencing
This section provides summary power sequencing requirements options 440BX AGPset. provides detailed description PIIX4E Suspend/Resume sequence, signaling protocols, timings. recommended usage model power plane control 440BX platform using PIIX4E power management signals described. This section does represent only design system, does provide recommendations using 440BX AGPset.
7.1.1
PIIX4E Power Sequencing
Power Sequencing Requirements
systems requiring tolerance, VREF signal must tied 5-V. This signal must power before simultaneous VCC. must power down after simultaneous VCC. non-5-V tolerant system (3.3-V only), this signal tied directly VCC. There then sequencing requirements. Refer Figure example circuit schematic, which used ensure proper VREF sequencing. PIIX4E VCC(USB) supplies separated internally order reduce noise signals. They should powered down independently another. They should connected same power plane motherboard. There other power sequencing requirements various power supplies PIIX4E.
Figure VREF Supply Schematic
Supply (3.3V) Schottky Diode Supply
System
VREF
System
7.1.2
Suspend/Resume Power Plane Control
PIIX4E supports three different Suspend modes. common system usage model these modes described here includes Power Suspend (POS), Suspend (STR), Suspend Disk (STD). This mode definition allows other system usage models that PIIX4E suspend/resume control signals other ways. common system mode names used throughout this document.
Pentium® Processor Mobile Module Design Guide
PIIX4E power management architecture designed allow systems support multiple suspend modes, switch between those modes required. suspended system resumed number different events. system returns full operation, then continue processing placed into another suspend mode. mode lower power mode than from what resumed.
7.1.2.1
Power Suspend (POS) System Model
devices powered except clock synthesizer. Host clocks inactive, PIIX4E provides control signals Suspend Clock (SUSCLK) allow DRAM refresh turn clock synthesizer. only power consumed system while mode DRAM refresh leakage current powered devices. When system resumes from mode, PIIX4E resume without resetting system, reset processor only, reset entire system. When reset performed, PIIX4E only needs wait clock synthesizer processor PLLs lock before system resumed. This takes typically
7.1.2.2
Suspend (STR)
Power removed from most system components during STR, except DRAM. Power supplied host bridge (for DRAM Suspend Refresh) PIIX4E's Suspend Well logic. PIIX4E provides control signals Suspend Clock (SUSCLK) allow DRAM refresh turn clock synthesizer other power planes. PIIX4E resets system resume from STR.
7.1.2.3
Suspend Disk (STD) Soft (SOff)
Power removed from most system components during STD. Power maintained Suspend Well logic PIIX4E. PIIX4E resets system resume from STD. state also called Soft (SOff) state. difference depends whether system state restored software pre-suspend condition system rebooted.
7.1.2.4
Mechanical (MOff)
This suspend state. This condition where power except battery been removed from system. typically controlled mechanical switch that turns power power supply. could used condition which embedded system's main battery been removed. PIIX4E controls system entering various suspend states through suspend control signals listed Table Upon initiation suspend, PIIX4E asserts SUS_STAT[1-2]#, SUSA#, SUSB#, SUSC# signals well defined sequence switch system into desired power state. SUSA#, SUSB#, SUSC# signals used control various power planes system. SUS_STAT1# signal status signal that indicates host bridge when enter exit suspend state, when enter exit stop clock state (when system still running). This typically used place DRAM controller into Suspend Refresh mode operation. SUS_STAT2# signal status signal that used indicate other system devices when enter exit suspend state (like graphics Cardbus controllers).
Pentium® Processor Mobile Module Design Guide
"System Suspend Resume Control Signaling" page sequencing details. Note that these signals associated with particular type suspend mode power plane descriptive purposes here. system designer free these signals control type function desired. system placed into suspend mode programming Power Management Control register. Suspend Type first programmed then Suspend Enable set. This causes PIIX4E automatically sequence into programmed suspend mode. Table Power State Decode
Power State STD/SOFF Mechanical RSMRST# SUS_STAT1# SUS_STAT2# SUSA# SUSB# SUSC#
SUS_STAT1# also used when system running. indicates Host-to-PCI bridge when switch between normal suspend refresh mode DRAM Stop Clock support. Stop Clock condition, HCLK stopped Host-to-PCI bridge must DRAM refresh from internal oscillator.
7.1.3
System Resume
PIIX4E resumed from either Suspend Soft state. Depending suspend state that system different features enabled resume system. There classes resume events, those whose logic resides PIIX4E main power well those whose logic resides PIIX4E suspend well. Those suspend well resume system from Suspend Soft state. Those main power well only resume system from Power Suspend state. Table lists suspend states which particular resume event enabled. Upon detection enabled resume event, PIIX4E sets appropriate status signals automatically transitions suspend control signals bring system into "full condition. sequencing shown "System Suspend Resume Control Signaling" page
Table Resume Events Supported Different Power States (Sheet
Suspend States Resume Event Alarm (IRQ8) SMBus Resume Event (Slave Port Match) Serial Ring (RI) Power Button (PWRBTN#) EXTSMI (EXTSMI#) (LID) GSTBY Timer Expiration STD/SOff MOff
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Table Resume Events Supported Different Power States (Sheet
Suspend States Resume Event Interrupt (IRQ 1,3-15) STD/SOff MOff
Alarm only supports internal RTC. external implementations, IRQ8 must tied other resume input signals (GPI[1], LID, EXTSMI#,RI#) resume functionality.
7.1.3.1
System Resume Events
various resume events their programming model shown here. Table Resume Event Programming Model
System Resume Event PWRBTN# Asserted Asserted Polarity Select GPI[1] Asserted EXTSMI# Asserted Programming Model [PWRBTN_EN] [LID_EN] [LID_POL] [GPI_EN] [EXTSMI_EN] [ALERT_EN] [SLV_EN] [SHDW1_EN] [SHDW2_EN] [GSTBY_EN] [RI_EN] [RTC_EN] [USB_EN] [IRQ_RSM_EN]
SMBus Events:
Global Standby Timer Expiration: Ring Indicate Assertion (RI#) Alarm (IRQ8)
Resume Signaling: (POS Only) IRQ[1,3-7,9-15]: (POS Only)
Alarm only supports internal RTC. external implementations, IRQ8 must tied other resume input signals (GPI[1], LID, EXTSMI#,RI#) resume functionality.
7.1.3.2
Global Standby Timer Resume
Global Standby Timer used monitor system activity during normal operation reloaded system activity events. Upon expiration, generates SMI#. When system placed Suspend Mode, Global Standby Timer used generate resume event. Global Standby Timer enable different timer resolutions wake-up times from approximately seconds hours. This allow system transition into lower power suspend state. System Management Section 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet additional information about Global Standby Timer.
Pentium® Processor Mobile Module Design Guide
7.1.4
System Suspend Resume Control Signaling
PIIX4E automatically controls signals required transition system between various power states. provides control Host clocks, main memory video memory refresh, system power plane control, system reset. Table Table illustrate common usage model power plane control using SUS[C:A]# signals. PIIX4E Resume well should always powered trickle supply (main battery backup battery embedded system).
Table Power Plane Control
SUSA# (POS) Clock synthesizer Video display
SUSB# (STR) Processor (Low Power GTL+ supplies) PIIX4E Core Other system devices2
SUSC# (STD) 82443BX Host Bridge Controller DRAM Graphics Controller
NOTES: video display (flat panel CRT) optionally powered POS. This could accomplished using PIIX4E's SUSA# SUS_STAT2# signals assert video controller's STANDBY signal. Devices include mass storage, audio, other devices that will generate system resume events.
Table Power Plane Control Using SUS[C:A]# Signals
Suspend Mode (Suspend Mode Signals Asserted PIIX4E) Power Plane Full (None) Clock Synthesizer Video Display PIIX4E Core Other Devices 82443BX DRAM Graphics Controller PIIX4E Resume PIIX4E
(SUSA#, SUS_STAT[2:1]#) On/Off1
(SUS[B:A]# SUS_STAT[2:1]#)
(SUS[C:A]# SUS_STAT[2:1]#)
NOTES: video display (flat panel CRT) optionally powered POS. This could accomplished using PIIX4E's SUSA# SUS_STAT2# signals assert video controller's STANDBY signal. Devices include mass storage, audio, other devices that will generate system resume events.
7.1.4.1
Power Well Reset Signal Timings
Figure shows system timings changing power states system using POS/STR/ models.
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7.1.4.2
PIIX4E Power Well Timings
Figure describes relative transitions PIIX4E power supplies. Figure PIIX4E Power Well Timings
Power Suspend Power Core Power
Table PIIX4E Power Well Timings
Parameter Well Power Suspend Well Power Suspend Well Power Core Well Power Unit Notes
7.1.4.3
RSMRST# PWROK Timing
Figure describes required timings PIIX4E power level active status signals. Figure RSMRST# PWROK Timings
Suspend Power RSMRST# Core Power
Table RSMRST# PWROK Timing
Parameter Suspend Well Power RSMRST# Inactive Core Well Power PWROK Active RSMRST# Inactive PWROK Active Unit Notes
Pentium® Processor Mobile Module Design Guide
7.1.4.4
Suspend Well Power RSMRST# Activated Signals
This describes timing relationships PIIX4E power management signals that powered from Suspend Power well. These timings hold independent condition Core Well power PWROK signal. Figure Suspend Well Power RSMRST# Activated Signals
Suspend Well Power RSMRST# SUS_STAT[1-2]# SUS[A-C]# SUSCLK
Table Suspend Well Power RSMRST# Timing
Parameter Resume Well Power RSMRST# Active SUS_STAT[1:2]# Active Resume Well Power RSMRST# Active [A:C]# Active Resume Well Power RSMRST# Active SUSCLK RSMRST# Inactive SUS[A:C]# Inactive Unit Notes
NOTE: These signals controlled internal clock. unit approximately
Pentium® Processor Mobile Module Design Guide
7.1.4.5
Clock Control Timings
This section describes timing requirements control system PCICLK. system PCICLK timing shown Figure must followed exactly proper operation PC/PCI Serial logic. When PC/PCI Serial IRQs used system, system PCICLK stop timings must meet system developer's requirements. Figure Clock Stop Timing
PCI_STP# PIIX4 PCICLK SYSTEM PCICLK
Figure describes timing requirements control system PCICLK. system PCICLK timings shown Figure must followed exactly proper operation PC/PCI Serial logic. When PC/PCI Serial IRQs used system, system PCICLK stop timings must meet system developers requirements. Figure Clock Start Timing
PCI_STP# PIIX4 PCICLK SYSTEM PCICLK
Pentium® Processor Mobile Module Design Guide
7.1.4.6
Core Well Power PWROK Activated Signals (RSMRST# Inactive Before Core Well Power Applied)
Figure shows timing relations Power Management signals powered from PIIX4E Main Core well. Here Suspend well power active status signals (RSMRST#) transitions before application core well power PIIX4E. This figure corresponds usage model PIIX4E power management. Figure Core Well Power PWROK Activated Signals (RSMRST# Inactive before Core Well Power Applied)
Well Power Suspend Well Power RSMRST# SUS[C:A]# Core Well Power PWROK
Float
CPU_STP# PCI_STP#
Running
Stopped
PCICLK
PCIRST#
CPURST
Active
SLP#
STPCLK#
Table Core Well Power PWROK Timing
Parameter Core Well Power PWROK Inactive CPU_STP# PCI_STP# Float Core Well Power PWROK Inactive PCIRST# Active Core Well Power PWROK Inactive CPURST Active Core Well Power PWROK Inactive SLP# Active Core Well Power PWROK Inactive STPCLK# Active Unit Notes
NOTES: These signals controlled internal clock. unit approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks power meet other system specifications. minimum, clocks must available stable after time shown Figure
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Table Core Well Power PWROK Timing
CPU_STP# PCI_STP# Float Clocks Running PWROK Active CPU_STP# PCI_STP# Active CPU_STP# PCI_STP# Active Clocks Stopped
NOTES: These signals controlled internal clock. unit approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks power meet other system specifications. minimum, clocks must available stable after time shown Figure
7.1.4.7
Core Well Power PWROK Activated Signals (Core Well Power Applied Before RSMRST# Inactive)
Figure shows timing relations Power Management signals powered from PIIX4E Core well. Here power active status signals (RSMRST# PWROK) transition after application power PIIX4E. This example implementation which Core Well power plane controlled SUSB# signal. applied situations where more PIIX4E power planes connected together. also shows timings when RSMRST# PWROK connected together. Figure Core Well Power PWROK Activated Signals (Core Well Power Applied before RSMRST# Inactive)
Well Power Suspend Well Power Core Well Power RSMRST# PWROK CPU_STP# PCI_STP# PCICLK PCI_RST# CPURST
Active
Float
Stopped
SLP# t19a t18a
STPCLK#
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Table Core Well Power PWROK Timing
t18a t19a Parameter Core Well Power PWROK Inactive CPU_STP# PCI_STP# Float Core Well Power PWROK Inactive PCIRST# Active Core Well Power PWROK Inactive CPURST Active Core Well Power PWROK Inactive SLP# Inactive Core Well Power PWROK Inactive STPCLK# Inactive CPU_STP# PCI_STP# Float Clocks Running PWROK Active CPU_STP# PCI_STP# Active CPU_STP# PCI_STP# Active Clocks Stopped PWROK Active SLP# Active PWROK Active STPCLK# Active PWROK Active SLP# Inactive PWROK Active STPCLK# Inactive Unit Notes
NOTES: These signals controlled internal clock. unit approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks power meet other system specifications. minimum, clocks must available stable after time shown Figure These timings depend relative timings between RSMRST# PWROK. RSMRST# goes inactive periods before PWROK active, then SLP# STPCLK# will remain inactive. RSMRST# goes inactive less than periods before PWROK active, then active pulse will seen SLP# STPCLK#.
Pentium® Processor Mobile Module Design Guide
7.1.5
Power Management State Transition Timings 7.1.5.1 Mechanical
Figure shows transition from Mechanical condition condition. Figure Mechanical
RSMRST# PWROK SUS[A-C]# SUS_STAT[1-2]# SUSCLK CPU_STP# PCI_STP# PCICLK PCI_RST# CPURST SLP# STPCLK#
Active Float
Running
Stopped Running
Inactive
Table Mechanical Timing
Parameter SUS[A:C]# Inactive CPU_STP# PCI_STP# Inactive CPU_STP# PCI_STP# Inactive Clocks Running CPU_STP# PCI_STP# Inactive SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive SUSCLK Running SUS_STAT[1:2]# Inactive PCI_RST# Inactive PCI_RST# Inactive CPURST Inactive Unit PCICLK Notes
NOTES: This transition requires minimum wait clock synthesizer lock PWROK active. PWROK goes active after from SUS[A:C]# inactive, transition occurs minimum period from PWROK active. Table Table exact PCICLK requirements with PC/PCI Serial IRQs. These signals controlled from internal clock. unit approximately
Pentium® Processor Mobile Module Design Guide
7.1.5.2
Figure describes signal transitions from state Power Suspend state. Figure
PWROK
SUS_STAT[1-2]#
SUS[A]# SUS[B-C]# SUSCLK CPU_STP# PCI_STP#
Running
PCICLK PCI_RST# CPURST
Clocks Running
Clocks Stopped
Inactive
SLP#
STPCLK#
Table Timing
Parameter CPU_STP# PCI_STP# Inactive STPCLK# Active STPCLK# Active SLP# Active SLP# Active SUS_STAT[1:2]# Active SUS_STAT[1:2]# Active CPU_STP# PCI_STP# Active CPU_STP# PCI_STP# Active SUS[A]# Active CPU_STP# PCI_STP# Active Clocks Stopped applicable) Unit PCICLK Notes
NOTES: These signals controlled from internal clock. unit approximately CPU_STP# PCI_STP# will only active when system under clock control. This transition waits Stop Grant cycle execute. system vendor determine whether CPU_STP# PCI_STP# signals used control system clocks. Table Table exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
7.1.5.3
(with Processor Reset)
Figure describes system transition from Power Suspend with full system reset. Figure (with Processor Reset)
Resume Event PWROK
SUS_STAT[1-2]#
SUS[A]# SUS[B-C]# SUSCLK CPU_STP# PCI_STP#
Running
PCICLK PCI_RST#
Clocks Stopped
Clocks Running
Active Inactive
CPURST SLP#
Inactive
STPCLK#
Table Timing
Parameter Resume Event SUS[A]# Inactive Resume Event PCI_RST# Active Resume Event CPURST Active Resume Event SLP# Inactive Resume Event STPCLK# Inactive SUS[A]# Inactive PCI_STP# CPU_STP# Inactive PCI_STP# CPU_STP# Inactive Clocks Running PCI_STP# CPU_STP# Inactive SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive PCI_RST# Inactive PCI_RST# Inactive PCI_STP# CPU_STP# allowed change PCI_RST# Inactive CPURST Inactive Unit PCICLK Notes
NOTES: These signals controlled from internal clock. unit approximately This transition requires minimum wait clock synthesizer lock PWROK active. PWROK goes active after from SUS[A:C]# inactive, transition will occur minimum period from PWROK active. PWROK remains active throughout system usage. Table Table exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
7.1.5.4
(with Processor Reset)
Figure describes system transition from Power Suspend (POS) with only processor reset. Figure (with Processor Reset)
Resume Event PWROK
SUS_STAT[1-2]#
SUS[A]# SUS[B-C]# SUSCLK CPU_STP# PCI_STP#
Running
PCICLK PCI_RST#
Clocks Stopped
Clocks Running
Active Inactive
CPURST SLP#
Inactive
STPCLK#
Table (with Processor Reset) Timing
Parameter Resume Event SUSA# Inactive Resume Event CPURST Active Resume Event SLP# Inactive Resume Event STPCLK# Inactive SUS[A]# Inactive PCI_STP# CPU_STP# Inactive PCI_STP# CPU_STP# Inactive Clocks Running PCI_STP# CPU_STP# Inactive SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive PCI_STP# CPU_STP# allowed change SUS_STAT[1:2]# Inactive CPURST Inactive Unit PCICLK Notes
NOTES: These signals controlled from internal clock. unit approximately This transition requires both minimum wait clock synthesizer lock PWROK active. PWROK goes active after from SUS[A:C]# inactive, transition will occur minimum period from PWROK active. PWROK remains active throughout system usage. Table Table exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
7.1.5.5
Reset)
Figure describes system transition from Power Suspend with resets performed. Figure Reset)
Resume Event PWROK
SUS_STAT[1-2]#
SUS[A]# SUS[B-C]# SUSCLK CPU_STP# PCI_STP#
Running
PCICLK PCI_RST# CPURST SLP#
Clocks Stopped
Clocks Running
Inactive
STPCLK#
Table Reset) Timing
Parameter Resume Event SUS[A]# Inactive SUS[A]# Inactive PCI_STP# CPU_STP# Inactive PCI_STP# CPU_STP# Inactive Clocks Running PCI_STP# CPU_STP# Inactive SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive PCI_STP# CPU_STP# allowed change SUS_STAT[1:2]# Inactive SLP# Inactive SLP# Inactive STPCLK# Inactive Unit PCICLK Notes
NOTES: These signals controlled from internal clock. approximately This transition requires both minimum wait clock synthesizer lock PWROK active. PWROK goes active after from SUS[A:C]# inactive, transition will occur minimum period from PWROK active. PWROK remains active throughout system usage. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
7.1.5.6
Figure describes signal transitions from state Suspend state. Figure
PWROK
Core Well Power
STAT[1-2]# SUS[A-B]# SUS[C]# SUSCLK STP# /PCI_STP#
Running Float Stopped Invalid
PCICLK PCI_RST#
Running
Invalid Invalid
Active Invalid Invalid
CPURST SLP#
Inactive
Invalid
STPCLK#
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Table Timing
Parameter CPU_STP# PCI_STP# Inactive STPCLK# Active STPCLK# Active SLP# Active SLP# Active SUS_STAT[1:2]# Active SUS_STAT[1:2]# Active CPU_STP# PCI_STP# Active CPU_STP# PCI_STP# Active CLOCKS Stopped CPU_STP# PCI_STP# Inactive SUS[A:B]# Active SUS[A:B]# Active PWROK Inactive PWROK Inactive CPU_STP# PCI_STP# Float PWROK Inactive PCI_RST# Active PWROK Inactive CPURST Active PWROK Inactive SLP# Inactive PWROK Inactive STPCLK# Inactive CPU_STP# PCI_STP# Float Clocks Invalid PWROK Inactive Core Well Power Removed Core Well Power Removed PCI_STP# CPU_STP# Invalid Core Well Power Removed PCIRST# Invalid Core Well Power Removed CPURST Invalid Core Well Power Removed SLP# Invalid Core Well Power Removed STPCLK# Invalid Unit PCICLK Notes
NOTES: These signals controlled from internal clock. approximately CPU_STP# PCI_STP# will only active system under clock control. This transition will also wait Stop Grant cycle execute. system vendor determine CPU_STP# PCI_STP# signals used control system clocks. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs. system vendor determine SUS[A:B]# signals used control system power planes. power remains applied system board PWROK stays active during STR, PIIX4E signals will remain states shown after t73. Clocks running depending condition Power Supply voltages.
Pentium® Processor Mobile Module Design Guide
7.1.5.7
Figure describes system transition from Suspend with full system reset. Figure
Resume Event
PWROK
Core Well Power SUS_STAT[1-2]# SUS[A-B]# SUS[C]# SUSCLK
Running t101 Float Running Stopped t100
CPU_STP# /PCI_STP# PCICLK PCI_RST# CPURST SLP# STPCLK#
Invalid
Invalid
Running t101a
Invalid Invalid Invalid Invalid Active t102 Inactive
Table Timing (Sheet
Parameter Resume Event SUS[A:B]# Inactive SUS[A:B]# Inactive Core Well Power Applied Core Well Power Applied PCI_STP# CPU_STP# Float Core Well Power Applied PCI_RST# Active Core Well Power Applied CPURST Active Core Well Power Applied SLP# Inactive Core Well Power Applied STPCLK# Inactive PCI_STP# CPU_STP# Float Clocks Running Core Well Power Applied PWROK Active Unit Notes
NOTES: These signals controlled from internal clock. approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks meet other system specifications upon power minimum, clocks must available stable after time t99. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
Table Timing (Sheet
t100 t101 t101a t102 Parameter PWROK Active CPU_STP# PCI_STP# Active PCI_STP# CPU_STP# Active Clocks Stopped PWROK Active CPU_STP# PCI_STP# Inactive SUS[A-B]# Inactive CPU_STP# PCI_STP# Inactive CPU_STP# PCI_STP# Inactive Clocks Running CPU_STP# PCI_STP# Inactive SUS_STAT[12]# Inactive SUS_STAT[1-2]# Inactive CPU_STP# PCI_STP# allowed change SUS_STAT[1-2]# Inactive PCI_RST# Inactive PCI_RST# Inactive CPURST Inactive PCICLK PCICLK Unit Notes
NOTES: These signals controlled from internal clock. approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks meet other system specifications upon power minimum, clocks must available stable after time t99. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
7.1.5.8
STD/SOff
Figure describes signal transitions from state Suspend Disk/Soft state. Figure STD/SOff
t110
PWROK
t117
Core Well Power
t105
SUS_STAT[1-2]#
t108
SUS[A-C]#
t109
SUSCLK CPU_STP# PCI_STP#
Running t106 t111 Float t107 t116 Stopped t112 t118 Invalid
PCICLK PCI_RST#
Running
Invalid t119 Invalid
t113
t120 Active Invalid t121 Invalid
CPURST SLP# STPCLK#
Inactive t104 t114
t103
t115
t122 Invalid
Table STD/SOff Timing (Sheet
t103 t104 t105 t106 t107 t108 Parameter CPU_STP# PCI_STP# Inactive STPCLK# Active STPCLK# Active SLP# Active SLP# Active SUS_STAT[1:2]# Active SUS_STAT[1:2]# Active CPU_STP# PCI_STP# Active CPU_STP# PCI_STP# Inactive CLOCKS Stopped CPU_STP# PCI_STP# Inactive SUS[A:C]# Active Unit PCICLK Notes
NOTES: These signals controlled from internal clock. approximately CPU_STP# PCI_STP# will only active system under clock control. This transition will also wait Stop Grant cycle execute. system vendor determine CPU_STP# PCI_STP# signals used control system clocks. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs. system vendor determine SUS[A:C]# signals used control system power planes. power remains applied system board PWROK stays active during STD, PIIX4E signals will remain states shown after t110.
Pentium® Processor Mobile Module Design Guide
Table STD/SOff Timing (Sheet
t109 t110 t111 t112 t113 t114 t115 t116 t117 t118 t119 t120 t121 t122 Parameter SUS[A:C]# Active SUSCLK SUS[A:C]# Active PWROK Inactive PWROK Inactive CPU_STP# PCI_STP# Float PWROK Inactive PCI_RST# Active PWROK Inactive CPURST Active PWROK Inactive SLP# Inactive PWROK Inactive STPCLK# Inactive CPU_STP# PCI_STP# Float Clocks Invalid PWROK Inactive Core Well Power Removed Core Well Power Removed PCI_STP# CPU_STP# Invalid Core Well Power Removed PCIRST# Invalid Core Well Power Removed CPURST Invalid Core Well Power Removed SLP# Invalid Core Well Power Removed STPCLK# Invalid Unit Notes
NOTES: These signals controlled from internal clock. approximately CPU_STP# PCI_STP# will only active system under clock control. This transition will also wait Stop Grant cycle execute. system vendor determine CPU_STP# PCI_STP# signals used control system clocks. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs. system vendor determine SUS[A:C]# signals used control system power planes. power remains applied system board PWROK stays active during STD, PIIX4E signals will remain states shown after t110.
Pentium® Processor Mobile Module Design Guide
7.1.5.9
STD/SOff
Figure describes system transition from Suspend Disk with full system reset. Figure STD/SOff
Resume Event
t131
PWROK
t124
Core Well Power
t137
SUS_STAT[1-2]#
t123
SUS[A-C]#
t138
SUSCLK
t134 t135 t125 Invalid Float t130 t133 Running t126 t136 Stopped t132 t140
Running
CPU_STP# PCI_STP# PCICLK PCI_RST# CPURST SLP# STPCLK#
Invalid
Running t139
Invalid t127 Invalid t128 Invalid t129 Invalid Active t141 Inactive
Table STD/SOff Timing (Sheet
t123 t124 t125 t126 t127 t128 t129 t130 t131 Parameter Resume Event SUS[A:C]# Inactive SUS[A-C]# Inactive Core Well Power Applied Core Well Power Applied PCI_STP# CPU_STP# Float Core Well Power Applied PCI_RST# Active Core Well Power Applied CPURST Active Core Well Power Applied SLP# Inactive Core Well Power Applied STPCLK# Inactive PCI_STP# CPU_STP# Float Clocks Running Core Well Power Applied PWROK Active Unit Notes
These signals controlled from internal clock. approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks power meet other system specifications. minimum, clocks must available stable after time t136. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs.
Pentium® Processor Mobile Module Design Guide
Table STD/SOff Timing (Sheet
t132 t133 t134 t135 t136 t137 t138 t139 t140 t141 Parameter PWROK Active CPU_STP# PCI_STP# Active PCI_STP# CPU_STP# Active Clocks Stopped SUS[A-C]# Inactive CPU_STP# PCI_STP# Inactive PWROK Active CPU_STP# PCI_STP# Inactive PCI_STP# CPU_STP# Active Clocks Running CPU_STP# PCI_STP# Inactive SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive SUSCLK Running SUS_STAT[1:2]# Inactive PCI_RST# Inactive SUS_STAT[1:2]# Inactive CPU_STP# PCI_STP# allowed change PCI_RST# Inactive CPURST Inactive PCICLK PCICLK Unit Notes
These signals controlled from internal clock. approximately There specific requirements these timings related PIIX4E. system manufacturer should make sure that clocks power meet other system specifications. minimum, clocks must available stable after time t136. Figure Figure exact PCICLK requirements with PC/PCI Serial IRQs.
7.2.1
82443BX Host Bridge Controller Power Sequencing
Power Sequencing Requirements
systems requiring tolerance, REFVCC5 signal must tied 5-V. This signal must power before simultaneous VCC. must power down after simultaneous VCC. non-5-V tolerant system (3.3-V only), this signal tied directly VCC. There then sequencing requirements. Refer Figure example circuit schematic that used ensure proper REFVCC5 sequencing. This same circuit that recommended PIIX4E VREF supply. However, different power planes supply PIIX4E core 82443BX Host Bridge controller (the PIIX4E core powered down during STR). this case separate circuit must used each devices. must power before simultaneous supplies (VCC_AGP AGP_REF) Power GTL+ supplies (VTT GTL_REF). must power down after simultaneous Power GTL+ supplies. Power GTL+ supplies must powered while powered down. There other power sequencing requirements 82443BX Host Bridge controller.
Pentium® Processor Mobile Module Design Guide
Figure REFVCC5 Supply Circuit Schematic
Supply (3.3V) Schottky Diode Supply
System
REFVCC5
System
7.2.2
440BX AGPset Power Management
440BX AGPset supports variety system-wide low-power modes using following functions:
Hardware interface with PIIX4E that used indicate:
Suspend mode entry Resume from suspend Whether automatically switch from suspend normal refresh
Automatic transition from normal suspend refresh Optional automatic transition from suspend normal refresh Optional reset during resume from Power Suspend (POS) Variety Suspend refresh types: Self Refresh SDRAMs Optional Self Refresh Optional Before (CBR) refresh EDO. Integrated Ring oscillator used provide time base associated logic. Programmable slow refresh (relevant refresh only)
Isolated pins significantly reduce power consumption while modes
Based above functions, 440BX AGPset recognizes following system-wide power modes:
suspend entry exit generally handled same manner. following
exceptions related mode: resume sequence include processor reset. STR, with PCIRST# active always includes processor reset. resume sequence requires hardware transition from suspend normal refresh. with PCIRST# active requires software initiated transition.
resume handled same power sequence, including complete reset
440BX AGPset state.
Pentium® Processor Mobile Module Design Guide
7.2.2.1
System Power Modes
following table provides overview above features into system-wide power modes. Table System-wide Low-power Modes
System Suspend State 82443BX State Description 82443BX fully operating normally. Power Internal clock gating well CLKRUN# enabled. This transparent 82443BX since external HCLK PCLK unaffected. Host Idle. Internal clock gating CLKRUN# enabled. System PLLs remain powered, disabled. HCLK clock kept low. only guaranteed running clock SUSCLK. 82443BX maintains DRAM refresh using suspend refresh. 82443BX's internal PLLs disabled. 82443BX arbiters disabled. System PLLs powered down. only running clock clock SUSCLK. 82443BX maintains DRAM refresh using suspend refresh. Power Suspend (POS) 82443BX's PLLs disabled. 82443BX arbiters disabled. When resumed, 82443BX generate processor reset. 82443BX logic, with exception resume refresh, inactive. processor other components (with exception DRAM PIIX4E resume logic) assumed powered OFF. 82443BX supply buffers isolated (with exception suspend DRAM signals). 82443BX Power GTL+ supplies should powered down with processor. 82443BX maintains DRAM refresh using suspend refresh. 82443BX logic, with exception resume refresh, inactive. Suspend -to-Disk (STD) Powered-Off entire system powered except PIIX4E resume wells. Upon resume, 82443BX resets entire state. Active Active Active Exit PCIRST External HCLK PCLK
STOP_GRANT QUICK_START (C2)
Active
Active
STOP CLOCK (C3) (DEEP SLEEP)
Suspend (STR)
NOTE: processor will generally powered during (the processor voltage regulator will controlled PIIX4E's SUSB# signal). this case, 82443BX Power GTL+ supply (VTT GTL_REF) should also controlled SUSB#, hence powered during STR.
Pentium® Processor Mobile Module Design Guide
7.2.2.2
System Power-up Sequencing
following waveforms show powerup sequence timing information 440BX AGPset. Figure System Power-up Sequencing
PIIX4E VCC(SUS)
RSMRST#
SUS[C:A]#
PIIX4E VCC(CORE)
PIIX4E PWROK
SUS_STAT#
CPU_STP# PCI_STP# FLOAT
CLOCKS
RUNNING
PCIRST#
BX_VCC
BXPWROK
CPURST#
Pentium® Processor Mobile Module Design Guide
Table System Power-up Sequencing Timing
Parameter PIIX4E VCC(SUS) nominal SUS[C:A]# active PIIX4E VCC(SUS) nominal SUS_STAT[2:1]# active PIIX4E VCC(SUS) nominal RSMRST# active RSMRST# inactive SUS[C:A]# inactive SUS[B]# inactive PIIX4E VCC(CORE) nominal SUS[C]# inactive BX_VCC nominal PIIX4E VCC(CORE) nominal CPU_STP#, PCI_STP# float PIIX4E VCC(CORE) nominal PCIRST# active PIIX4E VCC(CORE) nominal PIIX4E PWROK active BX_VCC nominal CPURST# active BX_VCC nominal BXPWROK active BXPWROK active PIIX4E PWROK active PIIX4E PWROK active CPU_STP#, PCI_STP# active SUS[C:A]# inactive CPU_STP#, PCI_STP# inactive CPU_STP#, PCI_STP# inactive clocks running CPU_STP#, PCI_STP# inactive SUS_STAT[2:1]# inactive SUS_STAT[2:1]# inactive PCIRST# inactive PCIRST# inactive CPURST# inactive Units PCICLK Notes
NOTES: unit approximately This parameter only applies BXPWROK will transition active state within SUS[C:A]# de-assertion This transition requires both minimum wait clock synthesizer lock PIIX4 PWROK active. PWROK goes active after from SUS[C:A]# inactive, transition will occur minimum period from PWROK active.
7.2.2.3
Suspend Resume Protocols
suspend resume sequences indicated 82443BX PIIX4E, using SUS_STAT# PCIRST#. addition, 82443BX contains NREF_EN CRst_En configuration bits that participate suspend resume sequences. result suspend resume, 82443BX performs following activities:
Changing refresh mode Performing internal processor reset Isolate re-enable normal buffers
Table describes suspend resume events activities.
Pentium® Processor Mobile Module Design Guide
Table Suspend Resume Events Activities
SUSSTAT# Assert PCIRST# Inactive CrstEn Reset Reset exclude resume/ref logic resets Reset processor only Refresh Switch suspend refresh Suspend refresh NREF_EN remains inactive Auto switch normal NREF_EN Auto switch normal NREF_EN Enable Buffers Isolate
Deassert
Active
Deassert
Inactive
Enable
Deassert
Inactive
Enable
requirements suspending 82443BX are:
system must idle when SUS_STAT# asserted. There must active processor
masters' cycles there must meaningful pending cycle's information chipset peripheral device's buffers.
After assertion SUS_STAT#, PIIX4E provides 82443BX with stable power
clocks perform necessary suspend sequence.
PCICLK must stopped with CLKRUN# during suspend sequence. 82443BX isolates buffers within less than time allocated from SUS_STAT#
assertion. 82443BX does isolate PCIRST# (being pulled clock inputs. clock inputs driven clock synthesizer, later clock synthesizer device powered down. requirements resuming 82443BX are:
Power clocks must stable least before SUS_STAT# deasserted. When resuming from POS, STPCLK# remains active about after SUS_STAT#
deassertion, allow automatic switch normal DRAM operation before processor pending cycles take place. 82443BX provides isolation buffers during STR. During events that were specified Table isolation takes effect. Table provides information about state each 82443BX signals during STR.
Pentium® Processor Mobile Module Design Guide
Table 443BX Signal States During Modes (Sheet
Signal Name CPURST# A[31:3]# HD[63:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# RASA[5:0]# CSA[5:0]# RASB[5:0]# CSB[5:0]# CKE[3:2] CSA[7:6]# CKE[5:4] CSB[7:6]# CASA[7:0]# DQMA[7:0]# CASB[5,1]# DQMB[5,1]# GCKE CKE1 SRAS[B:A]# CKE0 FENA SCAS[B:A]# MAA[13:0] MAB[9:7]# MAB[13,10] MAB[12:11]# MAB[6:0]# WEA#, WEB# [63:0] MECC[7:0] Tri-state Tri-state Tri-state High1 High1 Low/High2 Low/High2 High1 High1 Low/High2 Low/High2 Low/High2 High/Low2 Driven3 Driven3 Driven3 Driven3 High Driven3 Driven3 State During POS/STR Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state
NOTES: SDRAM Mode: After putting SDRAMs into self-refresh mode, these signals driven high. Mode: self-refresh mode, driven low. Otherwise, 82443BX continues refresh during POS/STR state. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] GCKE driven first value listed. Mode: These signals driven second value listed. lines always driven 82443BX, except MAB[13:11,9:0]# MAB10, which three-stated during reset. MD/MECC always driven 82443BX when there active cycle. values driven MECC indeterminate during after reset.
Pentium® Processor Mobile Module Design Guide
Table 443BX Signal States During Modes (Sheet
Signal Name AD[31:0] DEVSEL# FRAME# IRDY# C/BE[3:0]# PLOCK# TRDY# SERR# STOP# PHOLD# PHLDA# WSC# PREQ[4:0]# PGNT[4:0]# PIPE# SBA[7:0] RBF# ST[2:0] AD_STBA AD_STBB SB_STB G_FRAME# G_IRDY# G_TRDY# G_STOP# G_DEVSEL# G_REQ# G_GNT# G_AD[31:0] G_C/BE[3:0]# G_PAR HCLKIN NOTES: SDRAM Mode: After putting SDRAMs into self-refresh mode, these signals driven high. Mode: self-refresh mode, driven low. Otherwise, 82443BX continues refresh during POS/STR state. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] GCKE driven first value listed. Mode: These signals driven second value listed. lines always driven 82443BX, except MAB[13:11,9:0]# MAB10, which three-stated during reset. MD/MECC always driven 82443BX when there active cycle. values driven MECC indeterminate during after reset. State During POS/STR Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state
Pentium® Processor Mobile Module Design Guide
Table 443BX Signal States During Modes (Sheet
Signal Name PCLKIN DCLKO DCLKRD DCLKWR CRESET# PCIRST# GCLKIN GCLKO TESTIN# SMBCLK SMBDATA CLKRUN# SUSTAT# NOTES: SDRAM Mode: After putting SDRAMs into self-refresh mode, these signals driven high. Mode: self-refresh mode, driven low. Otherwise, 82443BX continues refresh during POS/STR state. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] GCKE driven first value listed. Mode: These signals driven second value listed. lines always driven 82443BX, except MAB[13:11,9:0]# MAB10, which three-stated during reset. MD/MECC always driven 82443BX when there active cycle. values driven MECC indeterminate during after reset. Tri-state Tri-state Tri-state Tri-state State During POS/STR
7.2.2.4
82443BX Suspend/Resume Sequences Timing
Table Suspend/Resume Timing (Sheet
Parameter BX_VCC stable BXPWROK asserted.
Unit
BXPWROK asserted SUS_STAT# inactive Clocks running SUS_STAT# inactive, guarantee BX_VCC active BXPWROK inactive CPURST# active SUS_STAT# deasserted PCIRST# deasserted, guarantee PCIRST# deasserted CPURST# deasserted SUS_STAT# deasserted buffers valid SUS_STAT# asserted clocks stopped, guarantee SUS_STAT# asserted suspend refresh
HCLK
"BX_VCC stable" means BX_VCC within specified Functional Operating Range.
Pentium® Processor Mobile Module Design Guide
Table Suspend/Resume Timing (Sheet
Parameter SUS_STAT# asserted buffers isolated PCIRST# asserted CPURST# asserted PCIRST# asserted SUS_STAT# deasserted, guarantee SUS_STAT# de-asserted normal refresh SUS_STAT# de-asserted CPURST# asserted CPURST# pulse width Unit HCLK
"BX_VCC stable" means BX_VCC within specified Functional Operating Range.
7.2.2.5
Suspend/Resume with PCIRST# Active
following resume sequence typically used when resuming from STR. includes following components:
BXPWROK must transition from inactive (low) active (high) minimum after
BX_VCC within specified Functional Operating Range.
When more elapse from time that PIIX4E deasserts SUS[C:A]# until
BXPWROK asserted, BXPWROK must asserted before simultaneous PWROK being asserted PIIX4E.
Upon resume, 82443BX detects that PCIRST# signal active (low) drives
CPURST# processor. Note that CPURST# driven active based PCIRST# timing, independent SUS_STAT# timing.
Based assertion SUS_STAT#, 82443BX isolates buffer within Based deassertion SUS_STAT#, 82443BX enables buffer normal Software must release memory controller from suspend refresh state normal
refresh state.
operation within Clock inputs PCIRST# never gated 82443BX thus affect before deassertion SUS_STAT#.
82443BX clears internal state, with exception resume/refresh logic, since
sampled PCIRST# asserted.
Pentium® Processor Mobile Module Design Guide
Figure Suspend/Resume with PCIRST# Active
BX_VCC
RESET
SUSPEND
BXPWROK
SUS_STAT#
CLOCKS
Running
Running
PCIRST#
CPURST#
Refresh Buffers
Normal Refresh Buffers valid
Suspend Refresh
Normal Refresh Buffers valid
7.2.2.6
Suspend/Resume with inactive PCIRST#, CPURST#
following resume sequence typically used when resuming from POS. includes following components:
Since PCIRST# signal inactive, resume 82443BX does drive CPURST#
processor, since CrstEn `0'.
Based assertion SUS_STAT#, 82443BX isolates buffer within Based deassertion SUS_STAT#, 82443BX enables buffer normal
operation within
82443BX switches from suspend refresh normal DRAM operation mode. processor starts execution from instruction just prior stop grant request being
recognized. 82443BX switches normal DRAM operation before deassertion STPCLK#.
82443BX state reset.
Pentium® Processor Mobile Module Design Guide
Figure Suspend/Resume with CPURST, PCIRST# Inactive
BX_VCC
RESET
SUSPEND
BXPWROK
SUS_STAT#
CLOCKS
Running
Running
PCIRST#
CPURST#
Refresh Buffers
Normal Refresh Buffers valid
Suspend Refresh
Normal Refresh Buffers valid
Pentium® Processor Mobile Module Design Guide
7.2.2.7
Suspend/Resume with CPURST Active, PCIRST# Inactive
following resume sequence typically used when resuming from POS. includes following components:
PCIRST# signal inactive, upon resume 82443BX drives CPURST# processor
since CrstEn `1'. CPURST# active
Based assertion SUS_STAT#, 82443BX isolates buffer within Based deassertion SUS_STAT#, 82443BX enables buffer normal
operation within
82443BX automatically switches from suspend refresh normal DRAM operation mode
when SUS_STAT# deassertion detected.
82443BX state reset.
Figure Suspend/Resume with Inactive PCIRST Active CPURST#
BX_VCC
RESET
SUSPEND
BXPWROK
SUS_STAT#
CLOCKS
Running
Running
PCIRST#
CPURST#
Refresh Buffers
Normal Refresh Buffers valid
Suspend Refresh
Normal Refresh Buffers valid
Pentium® Processor Mobile Module Design Guide
7.2.2.8
Suspend/Resume from
following resume sequence typically used when resuming from STD. includes following components:
When BXPWROK sampled `0', 82443BX undergoes complete reset asserts
CPURST#.
Based deassertion SUS_STAT#, 82443BX enables buffer normal operation
within less than Clock inputs PCIRST# never gated 82443BX thus affect before deassertion SUS_STAT#. refresh state, enable refresh with appropriate refresh rate. Figure Suspend/Resume from
Software must release memory controller from suspend refresh state normal
BX_VCC
RESET
SUSPEND
RESET
BXPWROK
SUS_STAT#
CLOCKS
Running
Running
PCIRST#
CPURST#
Refresh Buffers
Normal Refresh Buffers valid
Norm Valid
7.3.1
EMC-2 Power Sequencing
Voltage Regulator Control
EMC-2 VR_ON EMC-2 module connector allows digital signal (3.3 safe) control voltage regulator. system manufacturer this signal turn Pentium processor module voltage regulator off. VR_ON should controlled function same digital control signal (SUSB#) used control system's switched /3.3-V power planes. PIIX4E defines Suspend (STR) power-management state which power physically removed from most system components except DRAM. this state, SUSB# PIIX4E controls these power planes.
Pentium® Processor Mobile Module Design Guide
Caution:
VR_ON should switch high only when following conditions met: V_5(s) 4.5-V, V_DC 4.75-V Turning VR_ON prior meeting these conditions will severely damage module.
7.3.2
Voltage Signal Definition Sequencing
Table Voltage Signal Definitions Sequences
Signal Source Definitions Sequences voltage driven from power supply required between 21-V V_DC powers processor module's DC-to-DC converter processor core voltages. processor module cannot inserted removed while V_DC powered supplied system electronics 82443BX. supplied system electronics 82443BX's reference voltage processor module's voltage regulator. V_3S supplied system electronics cache devices. Each must powered during system states. VR_ON enables processor module's voltage regulator circuit. When driven active high (3.3-V) voltage regulator circuit processor module activated. signal driving VR_ON should digital signal with rise/fall time less than equal result VR_ON being asserted, V_CORE output DC-DC regulator processor module driven core voltage processor. also used host GTL+ termination voltage (VTT). V_BSB_IO 1.8-V. system electronics uses this voltage power cache-to-processor interface circuitry. Upon sampling voltage level V_CORE processors, minus tolerances ripple, VR_PWRGD driven active high (3.3 system electronics sample prior providing PWROK PIIX4. VR_PWRGD sampled active within second assertion VR_ON system electronics should de-assert VR_ON. V_CPUPU 2.5-V. system electronics uses this voltage power PIIX4E-to-processor interface circuitry V_CLK 2.5-V. system electronics uses this voltage power HCLK_(0:1) drivers processor clock.
V_DC
System Electronics
System Electronics System Electronics
V_3S
System Electronics
VR_ON
System Electronics
V_CORE (also used host GTL+ termination voltage VTT) V_BSB_IO
Processor module only; module interface. Processor module only; module interface.
VR_PWRGD
Processor module
V_CPUPU V_CLK
Processor module Processor module
Figure details sequencing signals voltage planes required normal operation processor module. processor module provides VR_PWRGD signal, which indicates that voltage regulator power operating stable voltage level. system manufacturer should this signal system electronics control power inputs gate PWROK PIIX4E.
Pentium® Processor Mobile Module Design Guide
Figure Power Sequence
V_DC V_3S VR_ON VR_PWRGD V_CPUIO NOTE NOTE
Power Sequence Timing PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4. V_DC 4.7V, 4.5V, V_3S 3.0V. V_CPUIO generated Intel® Pentium® Processor Mobile Module. This power supplie
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