CS5581 ±2.5 kSps, 16-bit, High-throughput Features Descripti

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CS5581 ±2.5 kSps, 16-bit, High-throughput Features Descripti

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3/25/08 15:11
CS5581
±2.5 kSps, 16-bit, High-throughput
Features Description
Single-ended Analog Input On-chip Buffers High Input Impedance Conversion Time Settles Conversion Linearity Error 0.0008% Signal-to-Noise S/(N ±0.1 Max. Simple three/four-wire serial interface Power Supply Configurations:
Analog: +5V/GND; +1.8V +3.3V Analog: ±2.5V; +1.8V +3.3V
General Description
CS5581 single-channel, 16-bit analog-to-digital converter capable kSps conversion rate. input accepts single-ended analog input signal. On-chip buffers provide high input impedance both input VREF+ input. This significantly reduces drive requirements signal sources reduces errors source impedances. CS5581 delta-sigma converter capable switching multiple input channels high rate with loss throughput. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter's 16-bit data output serial format, with serial port acting either master slave. converter designed support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. converter operate from analog supply 0-5V from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5, ORDERING INFORMATION: Ordering Information page
Power Consumption:
Input Buffers Input Buffers Off:
CS5581
VREF+ VREFDIGITAL FILTER LOGIC SERIAL INTERFACE SMODE SCLK ACOM
BUFEN DIGITAL CONTROL OSC/CLOCK GENERATOR
CONV BP/UP MCLK
VLR2
VLR3
Preliminary Product Information
http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2008 (All Rights Reserved)
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CS5581
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS SWITCHING CHARACTERISTICS DIGITAL CHARACTERISTICS GUARANTEED LOGIC LEVELS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS OVERVIEW THEORY OPERATION Converter Operation Clock Voltage Reference Analog Input Output Coding Format Typical Connection Diagrams VREF Sampling Structures Converter Performance Digital Filter Characteristics 3.10 Serial Port 3.10.1 Mode 3.10.2 Mode 3.11 Power Supplies Grounding 3.12 Using CS5581 Multiplexing Applications 3.13 Synchronizing Multiple Converters DESCRIPTIONS PACKAGE DIMENSIONS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION REVISION HISTORY
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CS5581
LIST FIGURES
Figure Mode Read Timing, remaining Figure Mode Read Timing, falling after falls Figure Mode Continuous SCLK Read Timing Figure Mode Discontinuous SCLK Read Timing Figure Voltage Reference Circuit Figure CS5581 Configured Using ±2.5V Analog Supplies Figure CS5581 Configured Unipolar Measurement Using Single Analog Supply Figure CS5581 Configured Bipolar Measurement Using Single Analog Supply Figure CS5581 Plot. Figure CS5581 Error Plot with Histogram. Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, -100 Figure Spectral Plot Noise with Shorted Input Figure Noise Histogram (4096 Conversions) Figure CS5581 Spectral Response fs/2) Figure CS5581 Spectral Response kHz) Figure CS5581 Spectral Response 8fs) Figure Simple Multiplexing Scheme Figure More Complex Multiplexing Scheme
LIST TABLES
Table Output Coding, Two's Complement Table Output Coding, Offset Binary
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CHARACTERISTICS SPECIFICATIONS
CS5581
characteristics specifications guaranteed over specified operating conditions. Typical characteristics specifications measured nominal supply voltages 25°C. voltages measured with respect
+2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE unless otherwise stated; BUFEN unless otherwise stated. Connected Figure Bipolar mode unless otherwise stated. Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N Ratio Input Bandwidth
ANALOG CHARACTERISTICS
(Note (Note (Note (Note kHz, -0.5 Input kHz, -0.5 Input kHz, -0.5 Input -0.5 Input, Input, (Note
0.0008
±0.1
Unit ±%FS LSB16 LSB16 LSB16 LSB16 µVrms
missing codes guaranteed bits resolution over specified temperature range. Total drift over specified temperature range after reset power-up, equivalent VREF 4.096 65536 62.5 Scales with MCLK.
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ANALOG CHARACTERISTICS (CONTINUED)
CS5581
+2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE unless otherwise stated; BUFEN unless otherwise stated. Connected Figure Parameter Analog Input Analog Input Range Input Capacitance Current (Note Buffer (BUFEN Buffer (BUFEN ACOM Unipolar Bipolar +VREF ±VREF Unit
Voltage Reference Input Voltage Reference Input Range (VREF+) (VREF-) Input Capacitance Current VREF+ Buffer (BUFEN VREF+ Buffer (BUFEN VREFIV1 Normal Operation Buffers Buffers (Note Supplies V1-, Supplies (Note 4.096
Power Supplies Power Supply Currents
Power Consumption Power Supply Rejection
Measured using input signal optimum performance, VREF+ should always less than (V+) volts prevent saturation VREF+ input buffer. Tested with mVP-P supply kHz. supplies same voltage potential, supplies same voltage potential.
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SWITCHING CHARACTERISTICS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter Master Clock Frequency Master Clock Duty Cycle Reset Time rising falling Conversion CONV Pulse Width BP/UP setup CONV falling CONV start conversion Perform Single Conversion (CONV high before falling) Conversion Time
CS5581
Symbol Internal Oscillator External Clock fclk
1536
16.2
Unit MCLKs MCLKs MCLKs MCLKs MCLKs
(Note Internal Oscillator External Clock
tres twup
tcpw (Note tscn tscn tbus tbuh
(Note Start Conversion falling
Reset must released until power supplies voltage reference within specification. BP/UP changed coincident CONV falling. BP/UP must remain stable until falls. CONV held continuously, conversions occur every MCLK cycles. tied CONV, conversions will occur every MCLKs. CONV operated asynchronously MCLK, conversion take MCLKs. falls conversion.
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter Serial Port Timing Mode (SMODE falling stable Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising
CS5581
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
SCLK will high impedance when high. some systems SCLK require pull-down resistors. SCLK MCLK/2.
MCLK
SCLK(o)
MSB-1
LSB+1
Figure Mode Read Timing, remaining (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter Serial Port Timing Mode (SMODE Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising falling stable First SCLK rising after falling hold time (low) after SCLK rising SCLK, tristate after rising
CS5581
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
SCLK will high impedance when high. some systems SCLK require pull-down resistors. SCLK MCLK/2.
MCLK SCLK(o)
MSB-1 LSB+1
Figure Mode Read Timing, falling after falls (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter Serial Port Timing Mode (SMODE VLR) SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) hold time (high) after falling hold time (high) after SCLK rising Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising hold time (low) after SCLK rising rising after SCLK falling
CS5581
Symbol
SCLK
Unit
(Note
will high impedance when high. some systems require pull-down resistor.
MCLK SCLK(i)
Figure Mode Continuous SCLK Read Timing (Not Scale)
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CS5581
MCLK
SCLK(i)
Figure Mode Discontinuous SCLK Read Timing (Not Scale)
DIGITAL CHARACTERISTICS
TMIN TMAX; 3.3V, 2.5V, 1.8V, ±5%; Parameter Input Leakage Current Digital Input Capacitance Digital Output Capacitance Symbol Cout Unit
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GUARANTEED LOGIC LEVELS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Guaranteed Limits Parameter Logic Inputs
Minimum High-level Input Voltage:
CS5581
Unit
Conditions
0.95
Maximum Low-level Input Voltage:
Logic Outputs
Minimum High-level Output Voltage:
1.65 0.36 0.36 0.44
Maximum Low-level Output Voltage:
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RECOMMENDED OPERATING CONDITIONS
(VLR Note
CS5581
Parameter Single Analog Supply Power Supplies: (Note V1V2-
Symbol
Unit
V2V1+
4.75 4.75
5.25 5.25
Dual Analog Supplies Power Supplies: (Note V1V2(Note [VREF+] [VREF-] V2V1+ V2VREF +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 4.096 +2.625 +2.625 -2.625 -2.625
Analog Reference Voltage
logic supply value +1.71 +3.465 volts long 3.465 differential voltage reference magnitude constrained supply magnitude.
ABSOLUTE MAXIMUM RATINGS
(VLR
Parameter Power Supplies: [V1+] [V1-] (Note |V1-| (Note Input Current, Except Supplies Analog Input Voltage Digital Input Voltage Storage Temperature Notes: V2+; V219.
Symbol VINA VIND Tstg
(V1-)
(V1+)
Unit
(Note
(AIN VREF pins)
V2Transient currents will cause latch-up.
WARNING: Recommended Operating Conditions indicate limits which device functionally operational. Absolute Maximum Ratings indicate limits beyond which permanent damage device occur. Absolute Maximum Ratings stress ratings only device should operated these limits. Operation conditions beyond Recommended Operating Conditions affect device reliability, functional operation beyond Recommended Operating Conditions implied. Performance specifications intended conditions specified each table Characteristics Specifications section.
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OVERVIEW
CS5581
CS5581 16-bit analog-to-digital converter capable kSps conversion rate. analog input accepts single-ended input with magnitude ±VREF volts. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter serial output device. serial port configured function either master slave. converter operate from analog supply from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5, CS5581 convert rates kSps when operating from input clock.
THEORY OPERATION
CS5581 converter provides high-performance measurement signals. converter used perform single conversions continuous conversions upon command. Each conversion independent previous conversions settles full specified accuracy, even with full-scale input voltage step. This converter architecture which uses combination high-speed delta-sigma modulator low-latency filter architecture. Once power established converter, reset must performed. reset initializes internal converter logic. CONV held low, converter will convert continuously with falling every MCLKs. This equivalent kSps MCLK 16.0 MHz. CONV tied RDY, conversion will occur every MCLKs. CONV operated asynchronously MCLK, take MCLKs from CONV falling falling. Multiple converters operate synchronously they driven same MCLK source CONV each converter falls same MCLK falling edge. Alternately, CONV held devices synchronized they reset with rising same falling edge MCLK. output coding conversion word function BP/UP pin.
Converter Operation
converter should reset after power supplies voltage reference stable. CS5581 converts kSps when synchronously operated (CONV VLR) from 16.0 master clock. Conversion initiated taking CONV low. conversion lasts master clock cycles, CONV asynchronous MCLK there uncertainty MCLK cycles after CONV falls when conversion actually begins. This extend throughput MCLKs conversion. When conversion completed, output word placed into serial port goes low. convert continuously, CONV should held low. continuous conversion mode with CONV held low, conversion performed MCLK cycles. Alternately tied CONV conversion will occur every MCLK cycles. perform only conversion, CONV should return high least master clock cycles before falls.
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CS5581
Once conversion completed falls, will return high when bits data word emptied from serial port conversion data read held low, will high MCLK cycles before conversion. will fall next conversion when data into port register. Serial Port page information about reading conversion data. Conversion performance affected several factors. These include choice clock source chip, timing CONV, choice serial port mode. converter operated from internal oscillator. This clock source greater jitter than external crystal-based clock. Jitter issue when measuring signals, very-low-frequency signals, become issue higher frequency signals. maximum performance when digitizing signals, low-jitter MCLK should used. maximize performance, CONV should held continuous conversion state perform multiple conversions, CONV should occur synchronous MCLK, falling when MCLK falls. converter operated maximum throughput, serial port mode less likely cause interference measurements SCLK output synchronized MCLK. Alternately, interference serial port clocking also minimized data read serial port mode when conversion progress.
Clock
CS5581 operated from internal oscillator from external master clock. state MCLK determines which clock source will used. MCLK tied low, internal oscillator will start used clock source converter. external CMOS-compatible clock input into MCLK, converter will power down internal oscillator external clock. MCLK held high, internal oscillator will held stopped state. MCLK input held high delete clock cycles synchronizing multiple converters different phase relationships. internal oscillator used signals measured essentially internal oscillator exhibits jitter about picoseconds rms. CS5581 used digitize signals, external low-jitter clock source should used. internal oscillator used clock CS5581, maximum conversion rate will dictated oscillator frequency. driven from external MCLK source, fast rise fall times MCLK signal result clock coupling from internal bond wire analog input. Adding resistor external MCLK source significantly reduces this effect.
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Voltage Reference
CS5581
voltage reference CS5581 range from volt volts. 4.096 volt reference required achieve specified signal-to-noise performance. Figure Figure illustrate connection voltage reference with either single analog supply with ±2.5 optimum performance, voltage reference device should that provides capacitor connection provide means noise filtering, output should include some type bandwidth-limiting filter. Some 4.096 volt reference devices need only volts total supply operation connected shown Figure Figure reference should have local bypass capacitor appropriate output capacitor. Some older 4.096 voltage reference designs require more headroom must operate from input voltage volts. this type voltage reference used ensure that when power applied system, voltage reference rise time slower than rise time power supply voltage converter. example circuit slow output startup time reference illustrated Figure
10µF
VOUT Refer VREF1 pins. 4.096
Figure Voltage Reference Circuit
Analog Input
analog input converter single-ended with full-scale input ±2.048 volts, relative ACOM pin. This illustrated Figure Figure These diagrams also illustrate differential buffer amplifier configuration driving CS5581. capacitors outputs amplifiers provide charge reservoir dynamic current from inputs while resistors isolate dynamic current from amplifier. amplifiers powered from higher supplies than those used precautions should taken ensure that output voltage remains within power supply limits A/D, especially under start-up conditions.
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Output Coding Format
CS5581
reference voltage directly defines input voltage range both unipolar bipolar configurations. unipolar configuration (BP/UP low), first code transition occurs above zero, final code transition occurs LSBs below VREF. bipolar configuration (BP/UP high), first code transition occurs above -VREF last transition occurs LSBs below +VREF. Table output coding converter.
Table Output Coding, Two's Complement
Bipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 -0.5 -VREF+0.5 <(-VREF+0.5 LSB)
Two's Complement
NOTE: VREF [(VREF+) (VREF-)]
Table Output Coding, Offset Binary
Unipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 (VREF/2)-0.5 +0.5 <(+0.5 LSB)
Offset Binary
NOTE: VREF [(VREF+) (VREF-)]
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Typical Connection Diagrams
CS5581
following figure depicts CS5581 powered from bipolar analog supplies, +2.5
+2.048 -2.048
CS5571 CS5581
49.9
150pF
4700pF
SMODE SCLK
CS3003
ACOM
(V+) Buffers BUFEN +2.5 (V-) Buffers BP/UP +4.096 Voltage Reference (NOTE VREF+
CONV
MCLK VREF-2.5
+2.5
+3.3 +1.8
V20.1
VLR3 VLR2 V1VLR
-2.5 NOTES Section Voltage Reference information required voltage reference performance criteria. 2.Locate capacitors minimize loop length. ±2.5 supplies should also bypassed ground converter. power supply ground ±2.5 should connected same ground plane under chip. SCLK require pull-down resistors some applications.
Figure CS5581 Configured Using ±2.5V Analog Supplies
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CS5581
following figure depicts CS5581 part powered from single analog supply configured unipolar measurement.
+2.048
CS5581 CS5571
49.9
150pF
4700pF
SMODE SCLK
CS3003 CS3004
ACOM (V+) Buffers BUFEN (V-) Buffers BP/UP +4.096 Voltage Reference (NOTE VREF+
CONV
MCLK VREFTST
+3.3
V20.1
VLR3 VLR2 V1VLR
NOTES Section Voltage Reference information required voltage reference performance criteria. Locate capacitors minimize loop length. V1-, V2-, should connected same ground plane under chip. SCLK require pull-down resistors some applications.
Figure CS5581 Configured Unipolar Measurement Using Single Analog Supply
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CS5581
following figure depicts CS5581 part powered from single analog supply configured bipolar measurement, referenced common mode voltage
0.458 4.548
49.9
150pF 4700pF
CS5581 CS5571 CS5581
SMODE
CS3003 CS3004
Common Mode Voltage (2.5 Typ.)
49.9
SCLK
ACOM
150pF 4700pF
CS3003 CS3004
(V+) Buffers (V-) Buffers +4.096 Voltage Reference (NOTE VREF+
CONV BUFEN BP/UP
MCLK VREFTST
+3.3
V20.1
VLR3 VLR2 V1VLR
NOTES Section Voltage Reference information required voltage reference performance criteria. Locate capacitors minimize loop length. V1-, V2-, should connected same ground plane under chip. SCLK require pull-down resistors some applications.
Figure CS5581 Configured Bipolar Measurement Using Single Analog Supply
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VREF Sampling Structures
CS5581
CS5581 uses on-chip buffers VREF+ inputs. Buffers provide much higher input impedance therefore reduce amount drive current required from external source. This helps minimize errors. Buffer Enable (BUFEN) determines on-chip buffers used not. BUFEN connected supply, buffers will enabled. BUFEN connected pin, buffers off. converter will consume about less power when buffers off, input impedances AIN, ACOM VREF+ will significantly less than with buffers enabled.
Converter Performance
CS5581 achieves excellent differential nonlinearity (DNL) shown Figures Figure illustrates code widths typical scale LSB. Figure illustrates zoomed scale ±0.1 LSB. error histogram Figure indicates that more than half codes accurate better than ±0.01 LSB.
1.00
Error LSBs
0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 65535
Codes
Figure CS5581 Plot
+0.10 +0.08 +0.06 +0.04 +0.02 -0.02 -0.04 -0.06 -0.08 -0.10 65535 +0.1 +0.09 +0.08 +0.07 +0.06 +0.05 +0.04 +0.03 +0.02 +0.01
Error LSBs
-0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.1
Codes
Counts 0.01 Error
Figure CS5581 Error Plot with Histogram DS796PP1
Error LSBs
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CS5581
Figures through illustrate performance CS5581 when driven 5.55 sine wave various amplitudes. each case, captured data windowed with seven-term window function that exhibits attenuation before being processed FFT. Figure illustrates converter performance with input that 1/10,000 full scale. This signal magnitude about codes, peak peak. Figure illustrates converter performance with input that 1/100,000 full scale, about 0.65 code, peak peak. These plots illustrate that this converter excellent small-signal performance near-perfect converter.
-100 -120 -140 -160 Frequency (Hz) 100k
5.55 kHz, Samples kSps
-100 -120 -140 -160 Frequency (Hz) 100k
5.55 kHz, Samples kSps
Figure Spectral Performance,
-100 -120 -140 -160 Frequency (Hz) 100k
5.55 kHz, Samples kSps
Figure Spectral Performance,
-100 -120 -140 -160 Frequency (Hz) 100k
5.55 kHz, Samples kSps
Figure Spectral Performance,
-100 -120 -140 -160
Figure Spectral Performance,
5.55 kHz, -100 Samples kSps
Frequency (Hz)
100k
Figure Spectral Performance, -100
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CS5581
Figure illustrates noise floor converter from kHz. While plot does exhibit some noise lower frequencies, noise floor entirely free spurious frequency content digital activity inside chip. Figure illustrates noise histogram 4096 samples.
-100 -120 -140 -160 Frequency (Hz) 100k
Shorted Input Samples kSps Averages
Figure Spectral Plot Noise with Shorted Input
Mean -0.61 Std. 2.33
Output (Codes)
Figure Noise Histogram (4096 Conversions)
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Digital Filter Characteristics
CS5581
digital filter designed fast settling, therefore exhibits very little in-band attenuation. filter attenuation 0.26347 when sampling kSps.
0.00
-0.01049
kSps
-0.04206 -0.09443
-0.05 -0.10 -0.15
-0.16813
-0.20 -0.25
-0.26347
-0.30 100k Frequency (Hz)
Figure CS5581 Spectral Response fs/2)
0.00
-0.006283 -0.002622
kSps
-0.005
-0.005901
-0.01
-0.01049
-0.015 Frequency (Hz)
Figure CS5581 Spectral Response kHz)
-100 -120 400k 800k Frequency (Hz) 1.2M 1.6M
kSps
Figure CS5581 Spectral Response 8fs)
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3.10 Serial Port
CS5581
serial port CS5581 operate different modes: synchronous self clock (SSC) mode synchronous external clock (SEC) mode. 3.10.1 Mode SMODE high (SMODE VL), serial port operates (Synchronous Self Clock) mode. mode port shifts conversion data words with SCLK output. SCLK generated inside converter from MCLK. Data output from (Serial Data Output) pin. high, SCLK pins will stay high-impedance state. when falls, conversion data word will output from first. Data output rising edge SCLK should latched into external logic subsequent rising edge SCLK. When bits conversion word output from port signal will return high. 3.10.2 Mode SMODE (SMODE VLR), serial port operates (Synchronous External Clock mode). this mode, user usually monitors RDY. When falls conversion, conversion data word placed into output data register serial port. then activated enable data output. Note that held continuously necessary have output operate high impedance state. When taken (after falls) conversion data word then shifted driving SCLK from system logic external converter. Data bits advanced rising edges SCLK latched subsequent rising edge SCLK. held continuously, signal will fall conversion conversion data will placed into serial port. user starts read, user will maintain control over serial port until port empty. However, SCLK toggled, converter will overwrite conversion data completion next conversion. held read performed, will rise just prior next conversion then fall signal that data been written into serial port.
3.11 Power Supplies Grounding
CS5581 configured operate with analog supply operating from with analog supplies operating from ±2.5V. digital interface supports digital logic operating from either 1.8V, 2.5V, 3.3V. Figure page illustrates device configured operate from ±2.5V analog. Figure page illustrates device configured operate from analog. maximize converter performance, analog ground logic ground converter should connected converter. dual analog supply configuration, analog ground ±2.5V supplies should connected converter with converter placed entirely over analog ground plane. single analog supply configuration (+5V), ground supply should directly tied converter with converter placed entirely over analog ground plane. Refer Figure page
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3.12 Using CS5581 Multiplexing Applications
CS5581
CS5581 delta-sigma converter. Delta-sigma converters oversampling means achieve high signal noise. This means that once conversion started, converter takes many samples compute resulting output word. analog input signal converted must remain active during entire conversion until falls. CS5581 used multiplexing applications, system timing changing multiplexer channel starting conversion will depend upon multiplexer system architecture. simplest system illustrated Figure time multiplexer changed, analog signal presented converter must fully settle. After signal settled, CONV signal issued converter start conversion. Being delta-sigma converter, signal must remain present input converter until conversion completed. Once conversion completed, falls. this time multiplexer changed next channel data read from serial port. CONV signal should delayed until after data read until analog signal settled. this configuration, throughput converter will dictated settling time analog input circuit conversion time converter. conversion data read from serial port after multiplexer changed channel while analog input signal settling.
CS5581
150pF 4700pF
ACOM
Amplifier Settling Time
Conversion Time
Amplifier Settling Time
CONV
Advance
Throughput
Figure Simple Multiplexing Scheme
more complex multiplexing scheme used increase throughput converter illustrated Figure this circuit, banks multiplexers used.
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CS5581
same time converter performing conversion channel from bank multiplexers, second multiplexer bank used select channel next conversion. This configuration allows buffer amplifier second multiplexer bank fully settle while conversion being performed channel from first multiplexer bank. multiplexer output buffer amplifier CONV signal changed same time this configuration. This multiplexing architecture allows maximum multiplexing throughput from converter. following figure depicts recommended analog input amplifier circuit.
150pF 4700pF
CS5581
150pF 4700pF
ACOM
CONV
Select Select Select Select Select
Select
Select
Select
Select
Select
Select
Convert
Convert
Convert
Convert
Convert
Figure More Complex Multiplexing Scheme
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3.13 Synchronizing Multiple Converters
CS5581
Many measurement systems have multiple converters that need operate synchronously. converters should driven from same master clock. this configuration, converters will convert synchronously same CONV signal used drive converters, CONV falls falling edge MCLK. CONV held continuously, reset (RST) used synchronize multiple converters released falling edge MCLK.
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DESCRIPTIONS
Chip Select Factory Test Serial Mode Select Analog Input Analog Return Negative Power Positive Power Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Logic Interface Return SMODE ACOM V1V1+ BUFEN VREF+ VREFBP/UP VLR2
CS5581
SCLK MCLK V2V2+ CONV VLR3
Ready Serial Clock Input/Output Serial Data Output Logic Interface Power Logic Interface Return Master Clock Negative Voltage Positive Voltage Digital Core Regulator Convert Logic Interface Return Reset
Chip Select, Chip Select allows external device access serial port. When held high, output will held high-impedance output state. Factory Test, factory only. Connect VLR. SMODE Serial Mode Select, serial interface mode (SMODE) dictates whether serial port behaves master slave interface. SMODE tied high VL), port will operate Synchronous Self-Clocking (SSC) mode. mode, port acts master which converter outputs both SCLK signals. SMODE tied VLR), port will operate Synchronous External Clocking (SEC) mode. mode, port acts slave which external logic microcontroller generates SCLK used output conversion data word from pin. Analog Input, single-ended input. ACOM Analog Return, ACOM analog return input signal. Negative Power pins provide negative supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally (Ground). dual-supply, operation they nominally -2.5 Positive Power pins provide positive supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally dual-supply operation, they nominally +2.5 BUFEN Buffer Enable, Buffers input pins ACOM enabled BUFEN connected disabled connected V1-. VREF+, VREF- Voltage Reference Input, Pins differential voltage reference input these pins functions voltage reference converter. voltage between these pins range between volts volts, with 4.096 volts being nominal reference voltage value.
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CS5581
BP/UP Bipolar/Unipolar Select, BP/UP determines span output coding converter. When high select (bipolar), input span converter -2.048 volts +2.048 volts (assuming voltage reference 4.096 volts) output data coded two's complement format. When select (unipolar), input span +2.048 output data coded binary format. Reset, Reset necessary after power initially applied converter. When input taken low, logic converter will reset. When released high, certain portions analog circuitry started. falls when reset complete. CONV Convert, CONV initiates conversion cycle taken low, unless previous conversion progress. When conversion cycle completed, conversion word output serial port register signal goes low. CONV held remains when falls, another conversion cycle will started. Digital Core Regulator, output on-chip regulator digital logic core. should bypassed with capacitor shown Typical Connection Diagrams page designed power external load. Positive Power pins provide positive supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally dual-supply operation, they nominally +2.5 Negative Power pins provide negative supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally (Ground). dual-supply operation, they nominally -2.5 MCLK Master Clock, master clock (MCLK) multi-function pin. tied (MCLK VLR), on-chip oscillator will enabled. tied high (MCLK VL), clocks internal circuitry converter will stop. When MCLK held high internal oscillator will also stopped. MCLK also function input external CMOS-compatible clock that conforms supply voltages pins. VLR2, VLR3, Logic Interface Power/Return, Pins VLR, supply voltages digital logic interface. configured with wide range common mode voltage. following interface pins function from VL/VLR supply: SMODE, SCLK, TST, SDO, RDY, CONV, RST, BP/UP, MCLK. Serial Data Output, output serial output port. Data from this will output rate determined SCLK format determined BP/UP pin. Data output first advances next data rising edges SCLK. will high impedance state when high.
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CS5581
SCLK Serial Clock Input/Output, SMODE determines whether SCLK signal input output signal. SCLK determines rate which data clocked pin. converter mode, SCLK frequency will determined master clock frequency converter (either MCLK internal oscillator). mode, user determines SCLK frequency. SCLK output (SMODE VL), will high-impedance state when high. Ready, conversion falls indicate that conversion word been placed into serial port. will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high); master clock cycles before data becomes available user holds started reading data from converter when mode.
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PACKAGE DIMENSIONS
CS5581
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.323 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -8.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03
JEDEC MO-150
Controlling Dimension Millimeters. Notes:
1."D" "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. 2.Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. 3.These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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ORDERING INFORMATION
Model Linearity Temperature Conversion Time Throughput
CS5581
Package
CS5581-ISZ
.0008%
kSps
24-pin SSOP
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days
CS5581-ISZ
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
REVISION HISTORY
Revision Date 2008 Changes Preliminary release.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that production, which full characterization data available. Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
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CS5581 ±2.5 kSps, 16-bit, High-throughput Features Descripti

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