Delta-sigma Converter Linearity Error: 0.0015%FS Noise-free Resol
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CS5525 CS5526 16-bit/20-bit, Multi-range with 4-bit Latch
Delta-sigma Converter
Linearity Error: 0.0015%FS Noise-free Resolution: 18-bits
General Description
16-bit CS5525 20-bit CS5526 highly integrated converters which include instrumentation amplifier, (programmable gain amplifier), eight digital filters, self system calibration circuitry. converters designed provide their negative supply which enables their on-chip instrumentation amplifiers measure bipolar ground-referenced signals ±100 directly supplying with -2.5 with ±2.5 signals (with respect ground) measured. digital filters provide programmable output update rates between 3.76 (XIN 32.768 kHz). Output word rates increased approximately using kHz. Each filter designed settle full accuracy output update rate conversion cycle. filters with word rates less (XIN 32.768 kHz) reject both line interference simultaneously. power, single conversion settling time, programmable output rates, ability handle negative input signals make these single supply products ideal solutions isolated non-isolated applications. ORDERING INFORMATION page
Bipolar/Unipolar Input Ranges
Chopper Stabilized Instrumentation Amplifier On-chip Charge Pump Drive Circuitry 4-bit Output Latch Simple three-wire serial interface
SPIand MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
Programmable Output Word Rates
3.76 (XIN 32.768 kHz) 11.47 (XIN kHz)
Output Settles Conversion Cycle Simultaneous 50/60 Noise Rejection System Self-calibration with Read/Write Registers Single Analog Supply +3.0 Digital Supply Low-power Mode Consumption:
Input Ranges
AGND VREF+
VREF-
DGND
AIN+ AIN-
Programmable Gain
Differential Order Delta-Sigma Modulator
Digital Filter
Calibration Register
SCLK
Control Register
Latch Calibration Memory Calibration Clock Gen.
Output Register
XOUT
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Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved)
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CS5525 CS5526
VA+, ±5%; VREF+ VREF- AGND, -2.1 FCLK 32.768 kHz, (Output Word Rate) Sps, Bipolar Mode, Input Range ±100 Notes CS5525 Parameter Accuracy Linearity Error Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift Voltage Reference Input Range Common Mode Rejection Input Capacitance Current (Note (VREF+) (VREF-) µA/V (Note (Note (Note (Notes ±0.0015 ±0.003 ±0.0007 ±0.0015 Bits nV/°C ppm/°C CS5526 Unit
ANALOG CHARACTERISTICS
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. LSB16 CS5525, LSB20 CS5526. Drift over specified temperature range after calibration power-up section data sheet which discusses input models page
NOISE (Notes
Output Rate Filter (Sps) Frequency 3.76 3.27 7.51 6.55 15.0 12.7 30.1 25.4 60.0 50.4 123.2 (Note 103.6 168.9 (Note 141.3 202.3 (Note 169.2 Input Range, (Bipolar/Unipolar Mode) 20.0
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown Peak-to-Peak Noise multiply ranges output rates. input ranges <100 output word rates Sps, 32.768 chopping frequency used. Specifications subject change without notice.
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CS5525 CS5526
ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode Signal AIN+ AINBipolar/Unipolar Mode -1.8 -2.5 Range Range AGND Range Range Common Mode Rejection Input Capacitance Current AIN+ AIN(Note Range Range System Calibration Specifications Full-scale Calibration Range Offset Calibration Range Power Supplies Power Supply Currents (Normal Mode) INBV Power Consumption Normal Mode Power Mode Standby Sleep Positive Supplies (Note 1.65 12.7 Bipolar/Unipolar Mode (Note 17.5 38.5 0.70 1.75 3.50 Bipolar/Unipolar Mode ±12.5 ±27.5 ±0.5 ±1.25 ±2.50 32.5 71.5 1.30 3.25 -0.150 1.85 0.950 2.65 µA/V Unit
(Note
Power Supply Rejection
Notes: minimum Full-scale Calibration Range (FSCR) limited maximum allowed gain register value (with margin). maximum FSCR limited modulator's density range. maximum full-scale signal limited saturation circuitry within internal signal path. outputs unloaded. input CMOS levels.
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CS5525 CS5526
DIGITAL CHARACTERISTICS VA+, ±5%;
Notes 12.)) Parameter High-level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+) 0.45 (VA+) (VD+) (VD+) Cout Unit
Low-level Input Voltage
High-level Output Voltage Pins Except (Note CPD, Iout -4.0 SDO, Iout -5.0 Low-level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-state Leakage Current Digital Output Capacitance Notes: measurements performed under static conditions.
Iout -100 unless stated otherwise. (VOH Iout µA.)
DIGITAL CHARACTERISTICS ±5%; ±10%;
Notes 12.)) Parameter High-level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol 0.54 (VD+) 0.45 (VA+) (VD+) (VD+) Cout 0.16 Unit
Low-level Input Voltage
High-level Output Voltage Pins Except SDO, Iout -400 CPD, Iout -4.0 SDO, Iout -5.0 Low-level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-state Leakage Current Digital Output Capacitance
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CS5525 CS5526
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/2 1/fout Unit
RECOMMENDED OPERATING CONDITIONS (AGND, DGND Note 14.))
Parameter Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: voltages with respect ground. Positive Digital Positive Analog (VREF+) (VREF-) Symbol VRefdiff 4.75 -1.8 -2.1 5.25 5.25 -2.5 Unit
ABSOLUTE MAXIMUM RATINGS (AGND, DGND Note 14.)
Parameter Power Supplies (Note Positive Digital Positive Analog Negative Potential (Note (Note VREF pins Pins Symbol IOUT VINR VINA VIND Tstg -0.3 -0.3 +0.3 -0.3 -0.3 +6.0 +6.0 -3.0 (VA+) (VA+) (VD+) Unit
Negative Bias Voltage Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: should more negative than Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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CS5525 CS5526
SWITCHING CHARACTERISTICS ±5%; ±10% ±5%;
Input Levels: Logic Logic VD+; pF.)) Parameter Master Clock Frequency (Note Internal Clock External Clock (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note Symbol trise tfall tost tpor 1003 cycles 32.768 32.768 Unit
Master Clock Duty Cycle Rise Times
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency SCLK Falling Falling continuous running SCLK (Note Serial Clock Write Timing Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable Read Timing Data Valid SCLK Falling Data Rising Hi-Z Pulse Width High Pulse Width SCLK
Notes: Device parameters specified with 32.768 clock; however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. Applicable when SCLK continuously running.
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SCLK
Continuous Running SCLK Timing (Not Scale)
Write Timing (Not Scale)
SCLK
Read Timing (Not Scale)
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DETAILED DESCRIPTION
CS5525 CS5526 16-bit 20-bit compatible converters which include chopperstabilized instrumentation amplifier input, on-chip programmable gain amplifier. They both optimized measuring low-level unipolar bipolar signals process control medical applications. CS5525/26 also include fourth order deltasigma modulator, calibration microcontroller, eight digital filters, 4-bit analog latch, serial port. digital filters provide eight different output update rates. CS5525/26 include (Charge Pump Drive) output (shown Figure provides negative bias voltage on-chip instrumentation amplifier when used with combination external diodes capacitors. This enables CS5525/26 measure negative voltages with respect ground, making converters ideal thermocouple temperature measurements.
Theory Operation
CS5525/26 converters designed operate from single analog supply provide several different input ranges. Analog Characteristics section page details. Figure illustrates CS5525/26 connected generate their negative bias supply using on-chip (Charge Pump Drive). This enables CS5525/26 measure ground referenced signals with magnitudes down (Negative Bias Voltage, approximately -2.1 this example). Figure illustrates charge pump circuit when converters powered from +3.0 digital supply. Alternatively, negative bias supply generated from negative supply voltage resistive divider illustrated Figure
Figure CS5525/26 Configured on-chip charge pump supply NBV.
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CS5525 CS5526
Figure illustrates CS5525/26 connected measure ground referenced unipolar signals positive polarity using input voltage ranges converter. ranges signal must have common mode near +2.5 (NBV 0V). CS5525/26 optimized measurement thermocouple outputs, they also well suited measurement ratiometric bridge transducer outputs. Figure illustrates CS5525/26 connected measure output ratiometric differential bridge transducer while operating from single supply.
5087
Figure Charge Pump Drive Circuit
Figure Alternate Circuits.
Figure CS5525/26 Configured ground-referenced Unipolar Signals.
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CS5525 CS5526
Figure CS5525/26 Configured Single Supply Bridge Measurement.
System Initialization
When power CS5525/26 applied, they held reset condition until their 32.768 oscillators have started their start-up counter-timer elapses. high 32.768 crystal, oscillators take 400-600 start. converter's counter-timer counts more than 1024 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register set. reset initiated time writing logic (Reset System) configuration register. This automatically sets until written logic configuration register read. After reset, on-chip registers initialized following states converters ready perform conversions.
configuration register: offset register: gain register: 000040(H) 000000(H) 800000(H)
Command Operation
CS5525/26 include microcontroller with five registers used control converter. Each register 24-bits length except 8-bit command register (command, configuration, offset, gain, conversion data). After system initialization reset, serial port initialized command mode converter stays this mode until valid 8-bit command received (the first 8-bits into serial port). Table lists valid commands. Once valid 8-bit command read write command word) received interpreted command register, serial port enters data mode. data mode next serial clock pulses shift data either into serial port serial clock pulses needed set-up register selected). Table configuring CS5525/26.
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Reading/Writing On-Chip Registers
CS5525/26's offset, gain, configuration registers read/writable while conversion data register read only. perform read from specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. perform write specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. Figure illustrates serial sequence necessary write read from serial port. Set-up Registers chosen with RSB2RSB0 bits, registers read written following sequence: Offset, Gain Configuration. This accomplished following 8-bit command word with three 24-bit data words total data bits.
Command Register
D7(MSB) NAME Command Bit, RSB2 VALUE D3-D1 Single Conversion, Continuous Conversions, Read/Write, Register Select Bit, RSB2-RSB0 RSB1 RSB0 PS/R FUNCTION Null command operation). command bits, including must Logic executable commands. Single Conversion active. Perform conversion. Continuous Conversions active. Perform conversions continuously. Write selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Power Save
Power Save/Run, PS/R
Table Command
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Configuration Register
D23(MSB) D23-D20 D15-D13 NAME Latch Outputs, A3-A0 Used, Chop Frequency Select, Used, Power Mode, Word Rate, WR2-0 Note: 32.768kHz VALUE 0000 110/111 Must always logic Amplifier chop frequency 32768 Amplifier chop frequency Must always logic Normal Mode Reduced Power mode 15.0 (2182 cycles) 30.1 (1090 cycles) 60.0 (546 cycles) 123.2 (266 cycles) 168.9 (194 cycles) 202.3 (162 cycles) 3.76 (8722 cycles) 7.51 (4362 cycles) Bipolar Measurement mode Unipolar Measurement mode (assumes VREF 2.5V) Used. Charge Pump Enabled goes Hi-Z output state. Normal Operation Activate Reset cycle. return Normal Operation write zero. reset occurred been cleared (read only). Valid Reset occurred. (Cleared when read.) Port Flag mode inactive Port Flag mode active Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) Done Flag cleared (read only). Calibration Conversion cycle completed (read only). Normal Operation calibration) Offset Self-Calibration Gain Self-Calibration Offset Self-Calibration followed Gain Self-Calibration used. Offset System Calibration Gain System Calibration Used. FUNCTION Latch Output Pins A3-A0 mimic D23-D20 Register bits.
D11-D9
Unipolar/Bipolar, Gain Bits, G2-G0
D2-D0
Pump Disable, Reset System, Reset Valid Port Flag, Power Save Select, Done Flag, Calibration Control Bits, CC2-CC0
indicates value after part reset Table Configuration Register DS202F5
CS5525 CS5526
SCLK
giste rite ycle
SCLK
et-u gisters Read ycle
SCLK
clock ycles each convers except first conv ersion hich take clock ycles
nversion
Figure Command Data Word Timing.
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CS5525 CS5526
Analog Input
Figure illustrates block diagram analog input signal path inside CS5525/26. front consists chopper-stabilized instrumentation amplifier with gain programmable gain section. instrumentation amplifier powered from from (Negative Bias Voltage) allowing CS5525/26 operated either analog input configurations. biased negative voltage between -1.8 -2.5 tied AGND. choice operating mode voltage depends upon input signal common mode voltage. input ranges, input signals AIN+ AIN- amplified instrumentation amplifier. ground referenced signals with magnitudes less then should biased with -1.8 -2.5 tied between -1.8 -2.5 (Common Mode Signal) input AIN+ AIN- must stay between -0.150 0.950 ensure proper operation. Alternatively, tied AGND where input (Common Mode Signal) AIN+ AIN- must stay between 1.85 2.65 ensure that amplifier operates properly. input ranges, instrumentation amplifier bypassed input signals directly connected Programmable Gain block. With tied between -1.8 -2.5 (Common Mode Signal) input AIN+ AIN- must stay between VA+. Alternatively, tied AGND where input (Common Mode Signal) AIN+ AIN- pins span entire range between AGND VA+. CS5525/26 accommodate full scale ranges other than performing system calibration within limits specified. Calibration section more details. Another change full scale range increase decrease voltage reference other than Voltage Reference section more details. Three factors operating limits input span. They include: instrumentation amplifier saturation, modulator density, lower reference voltage. When range selected, input signal (including common mode voltage amplifier offset voltage) must cause amplifier saturate either input stage output stage. prevent saturation absolute voltages AIN+ AINmust stay within limits specified (refer `Analog Input' table page Additionally, differential output voltage amplifier must exceed equation ABS(VIN VOS) defines differential output limit, where (AIN+) (AIN-) differential input voltage absolute maximum offset voltage instrumentation amplifier (VOS will exceed mV).
VREF+ VREF-
iffere ntial rder
ilter
Figure Block Diagram Analog Signal Path DS202F5
CS5525 CS5526
Max. Differential Output Amplifier Nominal(1) Differential Input -(1) Max. Input 0.75 1.65
Input Range(1)
VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Gain Factor 2.272727. 1.25
Note:
converter's actual input range, delta-sigma's nominal full scale input, delta-sigma's maximum full scale input scale directly with value voltage reference. values table assume VREF voltage. Table Relationship between Full Scale Input, Gain Factors, Internal Analog Signal Limitations
differential output voltage from amplifier exceeds amplifier saturate, which will cause measurement error. input voltage into modulator must cause modulator exceed percent high percent density. nominal full scale input span modulator (from percent percent density) determined VREF voltage divided Gain Factor. Table determine CS5525/26 being used properly. example, range determine nominal input voltage modulator, divide VREF (2.5 Gain Factor (2.2727). When smaller voltage reference used, resulting code widths smaller causing converter output codes exhibit more changing codes fixed amount noise. Table based upon VREF other values VREF, values Table must scaled accordingly. Figure's illustrate input models VREF pins. dynamic input current each pins determined from models shown dependent upon setting (Chop Frequency Select) bit. effective input impedance AIN+ AIN- pins remains constant three level measurement ranges mV). input current lowest with cleared logic
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Note: Residual noise appears converter's baseband output word rates greater than logic setting logic amplifier's chop frequency chops 32768 eliminating residual noise, increasing current. Note that C=48pF input current modeling only. physical input capacitance `Input Capacitance' specification under `Analog Characteristics' page
100m anges
48pF
32.76
nges
32pF
32.768 Figure Input models AIN+ AIN- pins
VREF+ VREFC 16pF
Figure Input model VREF+ VREF- pins.
CS5525 CS5526
Charge Pump Drive
(Charge Pump Drive) converters used with external components (shown Figure develop appropriate negative bias voltage pin. When used generate NBV, voltage regulated with internal regulator loop referenced VA+. Therefore, change results proportional change NBV. With NBV's regulation proportional approximately -2.1 Figure illustrates means supplying voltage from supply. ground based signals with instrumentation amplifier engaged (when 25mV, 55mV, 100mV ranges), voltage should time less negative than -1.8 more negative than -2.5 prevent excessive voltage stress chip voltage should more negative than -3.0 components Figure preferred components filter. However, smaller capacitors used with acceptable results. ensures very ripple NBV. Intrinsic safety requirements prohibit electrolytic capacitors. this case, 0.47 ceramic capacitors parallel used. itself tri-state output enters tri-state whenever converters placed into Sleep Mode, Standby Mode, when charge pump disabled (when Pump Disable bit, configuration register, set). Once tristate, digital current increase this output floats near digital supply. ensure stays near ground minimize digital current, resistor between DGND (see Figure resistor left out, digital supply current increase from
Voltage Reference
CS5525/26 specified operation with reference voltage between VREF+ VREF- pins devices. single-ended reference voltage, such LT1019-2.5, reference's output connected VREF+ CS5525/26. ground reference LT10192.5 connected VREF- pin. differential voltage between VREF+ VREF- voltage from however, VREF- below analog ground.
Calibration
CS5525/26 offer five different calibration functions including self calibration system calibration. However, after CS5525/26 reset, they perform measurements without being calibrated. this case, converters will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words ±100 range. initial offset gain errors internal circuitry chips will remain. gain offset registers, which used both self system calibration, used zero full-scale points converter's transfer function. offset register 2-24 proportion input span (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). converters typically trim percent input span. gain register spans from 2-23). decimal equivalent meaning gain register
where binary numbers have value either zero corresponds MSB). Refer Table details.
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CS5525 CS5526
Offset Register
Register
Reset
Sign
2-20 2-21 2-22 2-23 2-24
2-19
represents 2-24 proportion input span (bipolar span times unipolar span) Offset data word bits align (bit MSB-4 offset register changes MSB-4 data)
Gain Register
Register
Reset
2-23
gain register span from (2-2-23). After Reset other bits Table Table Offset Gain Registers
offset gain calibration steps each take conversion cycle complete. calibration step, calibration control bits will back logic (Done Flag) will logic combination self-calibration (CC2-CC0= 011; offset followed gain), calibration will take conversion cycles complete will after gain calibration completed. will cleared time data register, offset register, gain register, setup register read. Reading configuration register alone will clear bit.
modulator connected together then routed VREF- shown Figure self-calibration gain, differential inputs modulator connected VREF+
OPEN AIN+ CLOSED AIN+
Self Calibration
CS5525/26 offer both self offset self gain calibrations. self-calibration offset ranges, converter internally ties inputs instrumentation amplifier together routes them AIN- shown Figure proper self-calibration offset occur ranges, AIN- must proper common-mode-voltage (i.e. AIN- must between -1.8 -2.5 self-calibration offset ranges, inputs
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Figure Self Calibration Offset (Low Ranges).
OPEN
AIN+
CLOSED OPEN
CLOSED
AINVREF-
Figure Self Calibration Offset (High Ranges).
CS5525 CS5526
OPEN AIN+ AINVREF+ Reference VREFCLOSED CLOSED OPEN
External Connections AIN+ AINX20
Figure Self Calibration Gain (All Ranges).
Figure System Calibration Offset (Low Ranges).
VREF- shown Figure input range other than range, modulator gain error completely calibrated out. This lack accurate full scale voltage internal chips. range exception because external reference voltage nominal used full scale voltage. addition, when self-calibration gain performed input ranges, instrumentation amplifier's gain calibrated. These factors leave converters with gain error ±20% after self-calibration gain. Therefore, system gain required better accuracy, except range.
External Connections AIN+ AINX20
Figure System Calibration Offset (High Ranges).
External Connections AINAIN+ Full Scale
System Calibration
system calibration functions, user must supply converters calibration signals which represent ground full scale. When system offset calibration performed, ground reference signal must applied converter. Figures shown Figures user must input signal representing positive full scale point perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications).
Figure System Calibration Gain (Low Ranges)
External Connections AIN+ Full Scale AINX20
Figure System Calibration Gain (High Ranges).
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CS5525 CS5526
Assuming system provide known voltages, equations allow user manually compute calibration register's values based uncalibrated conversions. offset gain calibration registers used adjust typical conversion follows: Co>>4) 223. Calibration performed using following equations: (Rc0/G Ru0) where (Rc1 Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that gain offset registers default {gain register 0x800000 (Hex) offset register 0x000000 (Hex)}. bits. equations work correctly results with four zeros right).
Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near devices, user should wait each calibration step completed before reading writing serial port. maximum accuracy, calibrations should performed offset gain each gain setting (selected changing G2-G0 bits configuration register). factory calibration performed using system calibration capabilities CS5525/26, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converters when power first applied system, when gain range changed. final tips include ways determine when calibration complete: wait fall. falls logic (Port Flag) configuration register logic poll (Done Flag) configuration register which completion calibration. Whichever method used, calibration control bits (CC2CC0) will return logic upon completion calibration.
variables defined below.
First calibration voltage Second calibration voltage (greater than Result uncalibrated conversion Result uncalibrated conversion (20-bit integer complement) Result uncalibrated conversion (20-bit integer complement) Result conversion Desired calibration result converting (20-bit integer complement) Desired calibration result converting (20-bit integer complement) Offset calibration register value (24-bit complement) Gain calibration register value (24-bit integer)
shift right operator (e.g. shifted right bits) shift left operator (e.g. x<<2 shifted left bits)
Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. System calibration also limited intrinsic gain errors instrumentation amplifier modulator. gain calibrations
Note: shift operators used here align decimal points words various lengths. Data right decimal point used calculations shown. CS5525 conversion results (Ru, Rc.) bits instead DS202F5
CS5525 CS5526
input signal reduced point which gain register reaches upper limit (decimal) [FFFFFF Hex] (this most likely occur with input signal approximately nominal range). Alternatively, input signal increased point which modulator reaches one's density upper limit (this most likely occur with input signal approximately times nominal range). Also, full scale inputs larger than nominal full scale value range selected, there some voltage which various internal circuits saturate limited amplifier headroom (this most likely occur range setting when
Serial Port Initialization
serial port initialized command mode whenever power-on reset performed inside converter, when port initialization sequence completed, whenever command byte, data word sequence completed. port initialization sequence involves clocking more) bytes 1's, followed byte with following contents (11111110). This sequence places chips command mode where waits valid command.
Performing Conversions (With
Setting (Single Conversion) command word logic with other command bits CS5525/CS5526 will perform conversion. completion conversion (Done Flag) configuration register will logic user read configuration register determine set. been set, command issued read conversion data register obtain conversion data word. configuration register will cleared logic when data register, gain register, offset register, set-up registers read. Reading only configuration register will clear flag bit. command issued converters while they performing conversion, filter will restart convolution cycle perform conversion.
Analog Output Latch Pins
A3-A0 pins converters mimic D23D20 bits configuration register. A3-A0 used control multiplexers other logic functions outside converter. outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA+, hence, their output voltage logic will limited voltage.
Serial Port Interface
CS5525/26 serial interface consist four pins, SCLK, SDO, SDI, must held (logic before SCLK transitions recognized port logic. output will held high impedance time logic tied low, port function three wire interface. SCLK input designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. output capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
Performing Conversions (With
Setting configuration register logic enables output behave flag signal whenever conversions completed. This eliminates need user read flag configuration register determine conversion data word available. (Single Conversion) command issued other command bits will completion converDS202F5
CS5525 CS5526
sion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic data conversion word must read before command entered command used with (Continuous Conversion) command issued other command bits will completion conversion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic When operating continuous conversion mode, user need read every conversion. user does nothing after falls, will rise clock cycle before next conversion word available then fall again signal that another conversion word available. user begins clear flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data. exit continuous conversion mode, issue valid command input when flag falls. command issued converter while performing conversion, filter will restart convolution cycle perform conversion.
Output Word Rate Selection
WR2-WR0 bits configuration register output conversion word rate converters shown Table word rates indicated table assume master clock 32.768 kHz. Upon reset converters operate with output word rate 15.0 Sps.
Clock Generator
CS5525/26 include gate which connected with external crystal provide master clock chips. They designed operate using low-cost 32.768 "tuning fork" type crystal. 32.768 crystal should connected shown Figure Lead lengths should minimized reduce stray capacitance. converters will operate with external (CMOS compatible) clock with frequencies three times typical crystal frequency 32.768 kHz. Figure details converter's performance increased clock rates.
Figure High Speed Clock Performance
32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. °C). However, applications with CS5525/26 don't generally require such tight tolerances. When 32.768 tuning fork crystals used, recommended that protection components, external resistor capacitor shown Figure used.
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15.0 47.5 65.5
Attenuation (dB)
-100
Figure Tuning Fork Crystal Connection Diagram
-110 -120 -130
Digital Filter
CS5525/26 have eight different linear phase digital filters which output word rates (OWRs) stated Table These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield better than rejection both with output word rates below 15.0 Sps. converter's digital filters scale with XIN. example with output word rate filter's corner frequency typically 12.7 increased 64.536 doubles filter's corner frequency moves 25.4
Figure Filter Response (Normalized Output Word Rate
first followed rest data bits descending order. CS5525 last byte composed bits D7-D4, which always logic D3-D2, which always logic bits D1-D0 which flag bits. CS5526 last byte includes data bits D7-D4, D3-D2 which always logic flag bits. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than zero (unipolar mode), more negative than negative full scale (bipolar mode). cleared back logic whenever conversion word occurs which overranged.
(Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converters extremely overranged. set,
Output Coding
CS5525/26 output data binary format when operating unipolar mode two's complement when operating bipolar mode. output conversion word bits, three bytes long, shown Table output
Output Conversion Data CS5525 bits flags)
Output Conversion Data CS5526 bits flags)
Table Data Conversion Word
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CS5525 16-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) VFS-1.5 FFFF FFFF -FFFE 8000 -7FFF 0001 -0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000 CS5526 20-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFFF VFS-1.5 FFFFF -FFFFE 80000 -7FFFF 00001 -00000 00000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFF 7FFFF -7FFFE 00000 -FFFFF 80001 -80000 80000
VFS/2-0.5
-0.5
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table 5525/26 Output Coding
conversion data bits completely erroneous. flag will cleared logic when modulator becomes stable. Table illustrates output coding CS5525/26.
Power Consumption
CS5525/26 accommodate four power consumption modes: normal, power, standby, sleep. normal mode, default mode, entered after power-on-reset typically consumes power mode alternate mode that reduces consumed power entered setting (the power mode bit) configuration register logic Since converter's noise performance improves with increased power consumption, slightly degraded noise linearity performance should expected power mode. final modes referred power save modes. They power down most analog portion chips stop filter convolutions. power save modes entered whenever PS/R command word logic particular power save mode entered depends state (the Power Save Select bit) configuration register. logic converters enters standby mode reducing power consumption
1.2mW. standby mode leaves oscillator on-chip bias generator running. This allows converters quickly return normal power mode once PS/R back logic configuration register PS/R command word logic sleep mode entered reducing consumed power less than Since sleep mode disables oscillator, approximately 500ms oscillator start-up delay period required before returning normal power mode.
Layout
CS5525/26 should placed entirely over analog ground plane with both AGND DGND pins device connected analog plane. Place analog-digital plane split immediately adjacent digital portion chip. represents very high impedance when used with crystal, care should taken routing trace from crystal keep short possible. Stray capacitance between should minimizedby keeping trace away from XIN.
DS202F5
CS5525 CS5526
DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT LOGIC OUTPUT CHARGE PUMP DRIVE CRYSTAL CRYSTAL AGND AIN+ AINNBV XOUT
VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT CHIP SELECT SERIAL DATA INPUT LOGIC OUTPUT LOGIC OUTPUT SERIAL DATA OUTPUT POSITIVE DIGITAL POWER
DGND DIGITAL GROUND SCLK SERIAL CLOCK INPUT
Clock Generator
XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device.
Control Pins Serial Data
Chip Select, When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input, input serial input port. Data will input rate determined SCLK. Serial Data Output, serial data output. will output high impedance state SCLK Serial Clock Input, clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Logic Outputs, logic states A0-A3 mimic states D20-D23 bits configuration register. Logic Output AGND, Logic Output VA+.
DS202F5
CS5525 CS5526
Measurement Reference Inputs
AIN+, AIN- Differential Analog Input, Pins Differential input pins into device. VREF+, VREF- Voltage Reference Input, Pins Fully differential inputs which establish voltage reference on-chip modulator. Negative Bias Voltage, Input supply negative supply voltage gain instrumentation amplifier. tied AGND AIN+ AIN- inputs centered around +2.5 tied negative supply voltage (-2.1 typical) allow amplifier handle level signals more negative than ground. Charge Pump Drive, Square wave output used provide energy charge pump.
Power Supply Connections
Positive Analog Power, Positive analog supply voltage. Nominally Positive Digital Power, Positive digital supply voltage. Nominally +3.0 AGND Analog Ground, Analog Ground. DGND Digital Ground, Digital Ground.
DS202F5
CS5525 CS5526
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin.). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition(111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
DS202F5
CS5525 CS5526
PLASTIC (PDIP) PACKAGE DRAWING
SEATING PLANE
VIEW
SIDE VIEW
BOTTOM VIEW
INCHES 0.155 0.020 0.015 0.050 0.008 0.960 0.240 0.095 0.300 0.125 0.180 0.040 0.022 0.065 0.015 1.040 0.260 0.105 0.325 0.150
MILLIMETERS 3.94 4.57 0.51 1.02 0.38 0.56 1.27 1.65 0.20 0.38 24.38 26.42 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81
Notes: Positional tolerance leads shall within 0.25 (0.010 in.) maximum material condition, relation seating plane each other. Dimension center leads when formed parallel. Dimension does include mold flash.
DS202F5
CS5525 CS5526
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS202F5
CS5525 CS5526
ORDERING INFORMATION
Model Package Linearity Error (Max) ±0.003% Temperature
CS5525-AS CS5525-ASZ (Lead Free) CS5526-BP CS5526-BS CS5526-BSZ (Lead Free)
20-pin SSOP 20-pin Plastic (0.300") 20-pin SSOP
±0.0015%
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days Days Limit Days Days
CS5525-AS CS5525-ASZ (Lead Free) CS5526-BP CS5526-BS CS5526-BSZ (Lead Free)
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS202F5
CS5525 CS5526
REVISION HISTORY
Revision Date 2005 2005 Changes Added Lead-free device ordering information. Revised Lead-free device ordering information. Added data.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
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DS202F5
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