Compatible Modes User Configurable Page Size Bytes Page Byte

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Compatible Modes User Configurable Page Size Bytes Page Byte

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Single 2.5V 2.7V 3.6V Supply RapidS® Serial Interface: Maximum Clock Frequency
Compatible Modes
User Configurable Page Size
Bytes Page Bytes Page Page Program Operation Intelligent Programming Operation 2,048 Pages (256/264 Bytes/Page) Main Memory Flexible Erase Options Page Erase (256 Bytes) Block Erase Kbytes) Sector Erase Kbytes) Chip Erase Mbits) SRAM Data Buffers (256/264 Bytes) Allows Receiving Data while Reprogramming Flash Array Continuous Read Capability through Entire Array Ideal Code Shadowing Applications Low-power Dissipation Active Read Current Typical Standby Current Typical Deep Power-down Typical Hardware Software Data Protection Features Individual Sector Sector Lockdown Secure Code Data Storage Individual Sector Security: 128-byte Security Register 64-byte User Programmable Space Unique 64-byte Device Identifier JEDEC Standard Manufacturer Device Read 100,000 Program/Erase Cycles Page Minimum Data Retention Years Industrial Temperature Range Green (Pb/Halide-free/RoHS Compliant) Packaging Options
4-megabit 2.5-volt 2.7-volt DataFlash® AT45DB041D
Description
AT45DB041D 2.5V 2.7V, serial-interface Flash memory ideally suited wide variety digital voice-, image-, program code- data-storage applications. AT45DB041D supports RapidS serial interface applications requiring very high speed operations. RapidS serial interface compatible frequencies MHz. 4,325,376 bits memory organized 2,048 pages bytes bytes each. addition main memory, AT45DB041D also contains SRAM buffers 256/264 bytes each. buffers allow receiving data while page main Memory being reprogrammed, well writing continuous data stream. EEPROM emulation (bit byte alterability) easily handled with self-contained three step read-modify-write operation. Unlike conventional Flash memories that accessed randomly with multiple address lines parallel interface, DataFlash uses RapidS serial interface sequentially access data. simple sequential access dramatically reduces active count, facilitates hardware layout,
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increases system reliability, minimizes switching noise, reduces package size. device optimized many commercial industrial applications where high-density, low-pin count, low-voltage low-power essential. allow simple in-system reprogrammability, AT45DB041D does require high input voltages programming. device operates from single power supply, 2.5V 3.6V 2.7V 3.6V, both program read operations. AT45DB041D enabled through chip select (CS) accessed three-wire interface consisting Serial Input (SI), Serial Output (SO), Serial Clock (SCK). programming erase cycles self-timed.
Configurations Pinouts
Table 2-1.
Symbol
Configurations
Asserted State Type
Name Function Chip Select: Asserting selects device. When deasserted, device will deselected normally placed standby mode (not Deep Power-Down mode), output (SO) will high-impedance state. When device deselected, data will accepted input (SI). high-to-low transition required start operation, low-to-high transition required operation. When ending internally self-timed operation such program erase cycle, device will enter standby mode until completion operation. Serial Clock: This used provide clock device used control flow data from device. Command, address, input data present always latched rising edge SCK, while output data always clocked falling edge SCK. Serial Input: used shift data into device. used data input including command address sequences. Data always latched rising edge SCK. Serial Output: used shift data from device. Data always clocked falling edge SCK. Write Protect: When asserted, sectors specified protection Sector Protection Register will protected against program erase operations regardless whether Enable Sector Protection command been issued not. functions independently software controlled protection method. After goes low, content Sector Protection Register cannot modified.
Input
Input
Input Output
program erase command issued device while asserted, device will simply ignore command perform operation. device will return idle state once been deasserted. Enable Sector Protection command Sector Lockdown command, however, will recognized device when asserted. internally pulled-high left floating hardware controlled protection will used. However, recommended that also externally connected whenever possible. Reset: state reset (RESET) will terminate operation progress reset internal state machine idle state. device will remain reset condition long level present RESET pin. Normal operation resume once RESET brought back high level. device incorporates internal power-on reset circuit, there restrictions RESET during power-on sequences. this feature utilized recommended that RESET driven high externally. Device Power Supply: used supply source voltage device. Operations invalid voltages produce spurious results should attempted. Ground: ground reference power supply. should connected system ground.
Input
RESET
Input
Power Ground
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Figure 2-1. View
RESET
Figure 2-2.
SOIC View
RESET
Block Diagram
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER (256/264 BYTES)
BUFFER (256/264 BYTES)
RESET
INTERFACE
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Memory Array
provide optimal flexibility, memory array AT45DB041D divided into three levels granularity comprising sectors, blocks, pages. "Memory Architecture Diagram" illustrates breakdown each level details number pages sector block. program operations DataFlash occur page-by-page basis. erase operations performed chip, sector, block page level. Figure 4-1. Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR
SECTOR
BLOCK BLOCK BLOCK
SECTOR ARCHITECTURE
SECTOR Pages 2,048/2,112 bytes
PAGE ARCHITECTURE
Pages
BLOCK
PAGE PAGE
SECTOR Pages 63,488/65,472 bytes
PAGE PAGE PAGE
BLOCK BLOCK
SECTOR Pages 65,536/67,584 bytes
BLOCK SECTOR Pages 65,536/67,584 bytes
SECTOR
BLOCK
BLOCK
PAGE
PAGE PAGE
BLOCK BLOCK BLOCK SECTOR Pages 65,536/67,584 bytes BLOCK
PAGE PAGE PAGE
SECTOR Pages 65,536/67,584 bytes
BLOCK BLOCK
PAGE 2,046 PAGE 2,047
Block 2,048/2,112 bytes
Page 256/264 bytes
Device Operation
device operation controlled instructions from host processor. list instructions their associated opcodes contained Tables 15-1 through 15-7. valid instruction starts with falling edge followed appropriate 8-bit opcode desired buffer main memory address location. While low, toggling controls loading opcode desired buffer main memory address location through (serial input) pin. instructions, addresses, data transferred with most significant (MSB) first. Buffer addressing DataFlash standard page size (264 bytes) referenced datasheet using terminology BEA8 BFA0 denote address bits required designate byte address within buffer. Main memory addressing referenced using terminology PA10 BA0, where PA10 denotes address bits required designate page address denotes address bits required designate byte address within page. "Power binary page size (256 bytes), Buffer addressing referenced datasheet using conventional terminology BFA7 BFA0 denote address bits required designate byte address within buffer. Main memory addressing referenced using terminology where denotes address bits required designate page address denotes address bits required designate byte address within page.
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Read Commands
specifying appropriate opcode, data read from main memory from either SRAM data buffers. DataFlash supports RapidS protocols Mode Mode Please refer "Detailed Bit-level Read Timing" diagrams this datasheet details clock cycle sequences each mode.
Continuous Array Read (Legacy Command E8H):
supplying initial starting address main memory array, Continuous Array Read command utilized sequentially read continuous stream data from device simply providing clock signal; additional addressing information control signals need provided. DataFlash incorporates internal address counter that will automatically increment every clock cycle, allowing continuous read operation without need additional address sequences. perform continuous read from DataFlash standard page size (264 bytes), opcode must clocked into device followed three address bytes (which comprise 24-bit page byte address sequence) don't care bytes. first bits (PA10 PA0) 20-bit address sequence specify which page main memory array read, last bits (BA8 BA0) 20-bit address sequence specify starting byte address within page. perform continuous read from binary page size (256 bytes), opcode (E8H) must clocked into device followed three address bytes don't care bytes. first bits (A18 19-bits sequence specify which page main memory array read, last bits 19-bits address sequence specify starting byte address within page. don't care bytes that follow address bytes needed initialize read operation. Following don't care bytes, additional clock pulses will result data being output (serial output) pin. must remain during loading opcode, address bytes, don't care bytes, reading data. When page main memory reached during Continuous Array Read, device will continue reading beginning next page with delays incurred during page boundary crossover (the crossover from page beginning next page). When last main memory array been read, device will continue reading back beginning first page memory. with crossing over page boundaries, delays will incurred when wrapping around from array beginning array. low-to-high transition will terminate read operation tri-state output (SO). maximum frequency allowable Continuous Array Read defined fCAR1 specification. Continuous Array Read bypasses both data buffers leaves contents buffers unchanged.
Continuous Array Read (High Frequency Mode 0BH):
This command used with serial interface read main memory array sequentially high speed mode clock frequency maximum specified fCAR1. perform continuous read array with page size bytes, must first asserted then opcode must clocked into device followed three address bytes dummy byte. first bits (PA10 PA0) 20-bit address sequence specify which page main memory array read, last bits (BA8 BA0) 20-bit address sequence specify starting byte address within page. perform continuous read with page size bytes, opcode, 0BH, must clocked into device followed three address bytes (A18 dummy byte. Following dummy byte, additional clock pulses will result data being output (serial output) pin.
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must remain during loading opcode, address bytes, reading data. When page main memory reached during Continuous Array Read, device will continue reading beginning next page with delays incurred during page boundary crossover (the crossover from page beginning next page). When last main memory array been read, device will continue reading back beginning first page memory. with crossing over page boundaries, delays will incurred when wrapping around from array beginning array. low-to-high transition will terminate read operation tri-state output (SO). maximum frequency allowable Continuous Array Read defined fCAR1 specification. Continuous Array Read bypasses both data buffers leaves contents buffers unchanged.
Continuous Array Read (Low Frequency Mode: 03H):
This command used with serial interface read main memory array sequentially without dummy byte maximum frequencies specified fCAR2. perform continuous read array with page size bytes, must first asserted then opcode, 03H, must clocked into device followed three address bytes (which comprise 24-bit page byte address sequence). first bits (PA10 PA0) 20-bit address sequence specify which page main memory array read, last bits (BA8 BA0) 20-bit address sequence specify starting byte address within page. perform continuous read with page size bytes, opcode, 03H, must clocked into device followed three address bytes (A18 A0). Following address bytes, additional clock pulses will result data being output (serial output) pin. must remain during loading opcode, address bytes, reading data. When page main memory reached during Continuous Array Read, device will continue reading beginning next page with delays incurred during page boundary crossover (the crossover from page beginning next page). When last main memory array been read, device will continue reading back beginning first page memory. with crossing over page boundaries, delays will incurred when wrapping around from array beginning array. low-to-high transition will terminate read operation tri-state output (SO). Continuous Array Read bypasses both data buffers leaves contents buffers unchanged.
Main Memory Page Read
main memory page read allows user read data directly from 2,048 pages main memory, bypassing both data buffers leaving contents buffers unchanged. start page read from DataFlash standard page size (264 bytes), opcode must clocked into device followed three address bytes (which comprise 24-bit page byte address sequence) don't care bytes. first bits (PA10 PA0) 20-bit address sequence specify page main memory read, last bits (BA8 BA0) 20-bit address sequence specify starting byte address within that page. start page read from binary page size (256 bytes), opcode must clocked into device followed three address bytes don't care bytes. first bits (A18 19-bits sequence specify which page main memory array read, last bits 19-bits address sequence specify starting byte address within page. don't care bytes that follow address bytes sent initialize read operation. Following don't care bytes, additional pulses result data being output (serial output) pin. must remain during loading opcode, address bytes, don't care bytes, reading data. When page main
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memory reached, device will continue reading back beginning same page. low-to-high transition will terminate read operation tri-state output (SO). maximum frequency allowable Main Memory Page Read defined fSCK specification. Main Memory Page Read bypasses both data buffers leaves contents buffers unchanged.
Buffer Read
SRAM data buffers accessed independently from main memory array, utilizing Buffer Read Command allows data sequentially read directly from buffers. Four opcodes, buffer buffer used Buffer Read Command. each opcode depends maximum frequency that will used read data from buffer. opcode used frequency maximum specified fCAR1. opcode used lower frequency read operations maximum specified fCAR2. perform buffer read from DataFlash standard buffer (264 bytes), opcode must clocked into device followed three address bytes comprised don't care bits buffer address bits (BFA8 BFA0). perform buffer read from binary buffer (256 bytes), opcode must clocked into device followed three address bytes comprised don't care bits buffer address bits (BFA7 BFA0). Following address bytes, don't care byte must clocked initialize read operation. must remain during loading opcode, address bytes, don't care bytes, reading data. When buffer reached, device will continue reading back beginning buffer. low-to-high transition will terminate read operation tri-state output (SO).
Program Erase Commands
Buffer Write
Data clocked from input (SI) into either buffer buffer load data into DataFlash standard buffer (264 bytes), 1-byte opcode, buffer buffer must clocked into device, followed three address bytes comprised don't care bits buffer address bits (BFA8 BFA0). buffer address bits specify first byte buffer written. load data into binary buffers (256 bytes each), 1-byte opcode buffer buffer must clocked into device, followed three address bytes comprised don't care bits buffer address bits (BFA7 BFA0). buffer address bits specify first byte buffer written. After last address byte been clocked into device, data then clocked subsequent clock cycles. data buffer reached, device will wrap around back beginning buffer. Data will continue loaded into buffer until low-to-high transition detected pin.
Buffer Main Memory Page Program with Built-in Erase
Data written into either buffer buffer programmed into main memory. 1-byte opcode, buffer buffer must clocked into device. DataFlash standard page size (264 bytes), opcode must followed three address bytes consist don't care bits, page address bits (PA10 PA0) that specify page main memory written don't care bits. perform buffer main memory page program with built-in erase binary page size (256 bytes), opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits
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page address bits (A18 that specify page main memory written don't care bits. When low-to-high transition occurs pin, part will first erase selected page main memory (the erased state logic then program data stored buffer into specified page main memory. Both erase programming page internally self-timed should take place maximum time tEP. During this time, status register will indicate that part busy.
Buffer Main Memory Page Program without Built-in Erase
previously-erased page within main memory programmed with contents either buffer buffer 1-byte opcode, buffer buffer must clocked into device. DataFlash standard page size (264 bytes), opcode must followed three address bytes consist don't care bits, page address bits (PA10 PA0) that specify page main memory written don't care bits. perform buffer main memory page program without built-in erase binary page size (256 bytes), opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits, page address bits (A18 that specify page main memory written don't care bits. When low-to-high transition occurs pin, part will program data stored buffer into specified page main memory. necessary that page main memory that being programmed been previously erased using erase commands (Page Erase Block Erase). programming page internally self-timed should take place maximum time During this time, status register will indicate that part busy.
Page Erase
Page Erase command used individually erase page main memory array allowing Buffer Main Memory Page Program utilized later time. perform page erase DataFlash standard page size (264 bytes), opcode must loaded into device, followed three address bytes comprised don't care bits, page address bits (PA10 PA0) that specify page main memory erased don't care bits. perform page erase binary page size (256 bytes), opcode must loaded into device, followed three address bytes consist don't care bits, page address bits (A18 that specify page main memory erased don't care bits. When low-to-high transition occurs pin, part will erase selected page (the erased state logical erase operation internally self-timed should take place maximum time tPE. During this time, status register will indicate that part busy.
Block Erase
block eight pages erased time. This command useful when large amounts data written into device. This will avoid using multiple Page Erase Commands. perform block erase DataFlash standard page size (264 bytes), opcode must loaded into device, followed three address bytes comprised don't care bits, page address bits (PA10 PA3) don't care bits. page address bits used specify which block eight pages erased. perform block erase binary page size (256 bytes), opcode must loaded into device, followed three address bytes consisting don't care bits, page address bits (A18 A11) don't care bits. page address bits used specify which block eight pages erased. When lowto-high transition occurs pin, part will erase selected block eight pages. erase operation internally self-timed should take place maximum time tBE. During this time, status register will indicate that part busy.
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Table 7-1.
PA10/
Block Erase Addressing
PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/ Block
Sector Erase
Sector Erase command used individually erase sector main memory. There sectors only sector erased time. perform sector sector erase DataFlash standard page size (264 bytes), opcode must loaded into device, followed three address bytes comprised don't care bits, page address bits (PA10 PA3) don't care bits. perform sector erase, opcode must loaded into device, followed three address bytes comprised don't care bits, page address bits (PA10 PA8) don't care bits. perform sector sector erase binary page size (256 bytes), opcode must loaded into device, followed three address bytes comprised don't care page address bits (A18 A11) don't care bits. perform sector 1-15 erase, opcode must loaded into device, followed three address bytes comprised don't care page address bits (A18 A16) don't care bits. page address bits used specify valid address location within sector which erased. When low-to-high transition occurs pin, part will erase selected sector. erase operation internally self-timed should take place maximum time tSE. During this time, status register will indicate that part busy.
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Table 7-2.
PA10/
Sector Erase Addressing
PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/ Sector
Chip Erase(1)
entire main memory erased time using Chip Erase command. execute Chip Erase command, 4-byte command sequence C7H, 94H, must clocked into device. Since entire memory array erased, address bytes need clocked into device, data clocked after opcode will ignored. After last opcode sequence been clocked deasserted start erase process. erase operation internally self-timed should take place time tCE. During this time, Status Register will indicate that device busy. Chip Erase command will affect sectors that protected locked down; contents those sectors will remain unchanged. Only those sectors that protected locked down will erased. asserted while device erasing, protection will activated until internal erase cycle completes.
Command Chip Erase Byte Byte Byte Byte
Figure 7-1.
Chip Erase
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte
Note:
Refer errata regarding Chip Erase page
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Main Memory Page Program Through Buffer
This operation combination Buffer Write Buffer Main Memory Page Program with Built-in Erase operations. Data first clocked into buffer buffer from input (SI) then programmed into specified page main memory. perform main memory page program through buffer DataFlash standard page size (264 bytes), 1-byte opcode, buffer buffer must first clocked into device, followed three address bytes. address bytes comprised don't care bits, page address bits, (PA10 PA0) that select page main memory where data written, buffer address bits (BFA8 BFA0) that select first byte buffer written. perform main memory page program through buffer binary page size (256 bytes), opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits, page address bits (A18 that specify page main memory written, buffer address bits (BFA7 BFA0) that selects first byte buffer written. After address bytes clocked part will take data from input pins store specified data buffer. buffer reached, device will wrap around back beginning buffer. When there low-to-high transition pin, part will first erase selected page main memory then program data stored buffer into that memory page. Both erase programming page internally self-timed should take place maximum time tEP. During this time, status register will indicate that part busy.
Sector Protection
protection methods, hardware software controlled, provided protection against inadvertent erroneous program erase cycles. software controlled method relies software commands enable disable sector protection while hardware controlled method employs Write Protect (WP) pin. selection which sectors that protected unprotected against program erase operations specified nonvolatile Sector Protection Register. status whether sector protection been enabled disabled either software hardware controlled methods determined checking Status Register.
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8.1.1
Software Sector Protection
Enable Sector Protection Command Sectors specified protection Sector Protection Register protected from program erase operations issuing Enable Sector Protection command. enable sector protection using software controlled method, must first asserted would with other command. Once been asserted, appropriate 4-byte command sequence must clocked input (SI). After last command sequence been clocked must deasserted after which sector protection will enabled.
Command Enable Sector Protection Byte Byte Byte Byte
Figure 8-1.
Enable Sector Protection
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte
8.1.2
Disable Sector Protection Command disable sector protection using software controlled method, must first asserted would with other command. Once been asserted, appropriate 4-byte sequence Disable Sector Protection command must clocked input (SI). After last command sequence been clocked must deasserted after which sector protection will disabled. must deasserted state; otherwise, Disable Sector Protection command will ignored.
Command Disable Sector Protection Byte Byte Byte Byte
Figure 8-2.
Disable Sector Protection
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte
8.1.3
Various Aspects About Software Controlled Protection Software controlled protection useful applications which cannot controlled host processor. such instances, left floating (the internally pulled high) sector protection controlled using Enable Sector Protection Disable Sector Protection commands. device power cycled, then software controlled protection will disabled. Once device powered Enable Sector Protection command should reissued sector protection desired used.
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Hardware Controlled Protection
Sectors specified protection Sector Protection Register Sector Protection Register itself protected from program erase operations asserting keeping asserted state. Sector Protection Register sector specified protection cannot erased reprogrammed long asserted. order modify Sector Protection Register, must deasserted. permanently connected GND, then content Sector Protection Register cannot changed. deasserted, permanently connected VCC, then content Sector Protection Register modified. will override software controlled protection method only protecting sectors. example, sectors were previously protected Enable Sector Protection command, then simply asserting would enable sector protection within maximum specified tWPE time. When deasserted; however, sector protection would longer enabled (after maximum specified tWPD time) long Enable Sector Protection command issued while asserted. Enable Sector Protection command issued before while asserted, then simply deasserting would disable sector protection. this case, Disable Sector Protection command would need issued while deasserted disable sector protection. Disable Sector Protection command also ignored whenever asserted. noise filter incorporated help protect against spurious noise that inadvertently assert deassert pin. table below details sector protection status various scenarios pin, Enable Sector Protection command, Disable Sector Protection command. Figure 9-1. Protection Status
Table 9-1.
Time Period
Protection Status
Enable Sector Protection Command Command Issued Previously Issue Command Command Issued During Period Issue Command Disable Sector Protection Command Issue Command Issued Issue Command Sector Protection Status Disabled Disabled Enabled Enabled Enabled Disabled Enabled Sector Protection Register Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write
High
High
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Sector Protection Register
nonvolatile Sector Protection Register specifies which sectors protected unprotected with either software hardware controlled protection methods. Sector Protection Register contains bytes data, which byte locations through contain values that specify whether sectors through will protected unprotected. Sector Protection Register user modifiable must first erased before reprogrammed. Table illustrates format Sector Protection Register.: Table 9-2. Sector Protection Register
(0a, Table Unprotected
Sector Number Protected
Table 9-3.
Sector (0a,
(Page 0-7)
(Page 8-255)
Data Value
Sectors Unprotected Protect Sector Protect Sector (Page 8-255) Protect Sectors (Page 0-7), (Page 8-255)(1) Note:
default value bytes through when shipped from Atmel® 00H. don't care.
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9.1.1 Erase Sector Protection Register Command order modify change values Sector Protection Register, must first erased using Erase Sector Protection Register command. erase Sector Protection Register, must first asserted would with other command. Once been asserted, appropriate 4-byte opcode sequence must clocked into device pin. 4-byte opcode sequence must start with followed 2AH, 7FH, CFH. After last opcode sequence been clocked must deasserted initiate internally self-timed erase cycle. erasing Sector Protection Register should take place time tPE, during which time Status Register will indicate that device busy. device powereddown before completion erase cycle, then contents Sector Protection Register cannot guaranteed. Sector Protection Register erased with sector protection enabled disabled. Since erased state (FFH) each byte Sector Protection Register used indicate that sector specified protection, leaving sector protection enabled during erasing register allows protection scheme more effective prevention accidental programming erasing device. some reason erroneous program erase command sent device immediately after erasing Sector Protection Register before register reprogrammed, then erroneous program erase command will processed because sectors would protected.
Command Erase Sector Protection Register Byte Byte Byte Byte
Figure 9-2.
Erase Sector Protection Register
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte
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9.1.2
Program Sector Protection Register Command Once Sector Protection Register been erased, reprogrammed using Program Sector Protection Register command. program Sector Protection Register, must first asserted appropriate 4-byte opcode sequence must clocked into device pin. 4-byte opcode sequence must start with followed 2AH, 7FH, FCH. After last opcode sequence been clocked into device, data contents Sector Protection Register must clocked described Section 9.1, Sector Protection Register contains bytes data, bytes must clocked into device. first byte data corresponds sector second byte corresponds sector with last byte data corresponding sector After last data byte been clocked must deasserted initiate internally self-timed program cycle. programming Sector Protection Register should take place time during which time Status Register will indicate that device busy. device powered-down during program cycle, then contents Sector Protection Register cannot guaranteed. proper number data bytes clocked before deasserted, then protection status sectors corresponding bytes clocked guaranteed. example, only first bytes clocked instead complete bytes, then protection status last sectors cannot guaranteed. Furthermore, more than bytes data clocked into device, then data will wrap back around beginning register. instance, bytes data clocked then byte will stored byte location Sector Protection Register. value other than clocked into byte location Sector Protection Register, then protection status sector corresponding that byte location cannot guaranteed. example, value clocked into byte location Sector Protection Register, then protection status sector cannot guaranteed. Sector Protection Register reprogrammed while sector protection enabled disabled. Being able reprogram Sector Protection Register with sector protection enabled allows user temporarily disable sector protection individual sector rather than disabling sector protection completely. Program Sector Protection Register command utilizes internal SRAM buffer processing. Therefore, contents buffer will altered from previous state when this command issued.
Command Program Sector Protection Register Byte Byte Byte Byte
Figure 9-3.
Program Sector Protection Register
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte Data Byte Data Byte Data Byte
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9.1.3 Read Sector Protection Register Command read Sector Protection Register, must first asserted. Once been asserted, opcode dummy bytes must clocked pin. After last opcode dummy bytes have been clocked additional clock pulses pins will result data content Sector Protection Register being output pin. first byte corresponds sector (0a, 0b), second byte corresponds sector last byte (byte corresponds sector Once last byte Sector Protection Register been clocked out, additional clock pulses will result undefined data being output pin. must deasserted terminate Read Sector Protection Register operation output into high-impedance state.
Command Read Sector Protection Register Note: Dummy Byte Byte Byte Byte Byte
Figure 9-4.
Read Sector Protection Register
Opcode
Data Byte Each transition represents bits
Data Byte
Data Byte
9.1.4
Various Aspects About Sector Protection Register Sector Protection Register subject limit 10,000 erase/program cycles. Users encouraged carefully evaluate number times Sector Protection Register will modified during course applications' life cycle. application requires that Sector Protection Register modified more than specified limit 10,000 cycles because application needs temporarily unprotect individual sectors (sector protection remains enabled while Sector Protection Register reprogrammed), then application will need limit this practice. Instead, combination temporarily unprotecting individual sectors along with disabling sector protection completely will need implemented application ensure that limit 10,000 cycles exceeded.
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Security 10.1 Sector Lockdown
device incorporates Sector Lockdown mechanism that allows each individual sector permanently locked that becomes read only. This useful applications that require ability permanently protect number sectors against malicious attempts altering program code security information. Once sector locked down, never erased programmed, never unlocked. issue Sector Lockdown command, must first asserted would other command. Once been asserted, appropriate 4-byte opcode sequence must clocked into device correct order. 4-byte opcode sequence must start with followed 2AH, 7FH, 30H. After last byte command sequence been clocked then three address bytes specifying address within sector locked down must clocked into device. After last address been clocked must then deasserted initiate internally self-timed lockdown sequence. lockdown sequence should take place maximum time during which time Status Register will indicate that device busy. device powered-down before completion lockdown sequence, then lockdown status sector cannot guaranteed. this case, recommended that user read Sector Lockdown Register determine status appropriate sector lockdown bits bytes reissue Sector Lockdown command necessary.
Command Sector Lockdown Byte Byte Byte Byte
Figure 10-1. Sector Lockdown
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte Address Bytes Address Bytes Address Bytes
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10.1.1 Sector Lockdown Register Sector Lockdown Register nonvolatile register that contains bytes data, shown below:
Sector Number Locked Below Unlocked (0a,
Table 10-1.
Sector (0a,
(Page 0-7)
(Page 8-255)
Data Value
Sectors Unlocked Sector Locked (Page 0-7) Sector Locked (Page 8-255) Sectors Locked (Page 0-255)
10.1.2
Reading Sector Lockdown Register Sector Lockdown Register read determine which sectors memory array permanently locked down. read Sector Lockdown Register, must first asserted. Once been asserted, opcode dummy bytes must clocked into device pin. After last opcode dummy bytes have been clocked data contents Sector Lockdown Register will clocked pin. first byte corresponds sector (0a, second byte corresponds sector byte (byte corresponds sector After last byte Sector Lockdown Register been read, additional pulses will simply result undefined data being output pin. Deasserting will terminate Read Sector Lockdown Register operation into high-impedance state. Table 10-2 details values read from Sector Lockdown Register. Table 10-2.
Command Read Sector Lockdown Register Note: Dummy Byte
Sector Lockdown Register
Byte Byte Byte Byte
Figure 10-2. Read Sector Lockdown Register
Each transition represents bits Opcode
Data Byte
Data Byte
Data Byte
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10.2
Security Register
device contains specialized Security Register that used purposes such unique device serialization locked storage. register comprised total bytes that divided into portions. first bytes (byte locations through Security Register allocated one-time user programmable space. Once these bytes have been programmed, they cannot reprogrammed. remaining bytes register (byte locations through 127) factory programmed Atmel will contain unique value each device. factory programmed data fixed cannot changed. Table 10-3. Security Register
Security Register Byte Number Data Type
One-time User Programmable
Factory Programmed Atmel
10.2.1
Programming Security Register user programmable portion Security Register does need erased before programmed. program Security Register, must first asserted appropriate 4-byte opcode sequence must clocked into device correct order. 4-byte opcode sequence must start with followed 00H, 00H, 00H. After last opcode sequence been clocked into device, data contents 64-byte user programmable portion Security Register must clocked After last data byte been clocked must deasserted initiate internally self-timed program cycle. programming Security Register should take place time during which time Status Register will indicate that device busy. device powered-down during program cycle, then contents 64-byte user programmable portion Security Register cannot guaranteed. full bytes data clocked before deasserted, then values byte locations clocked cannot guaranteed. example, only first bytes clocked instead complete bytes, then remaining bytes user programmable portion Security Register cannot guaranteed. Furthermore, more than bytes data clocked into device, then data will wrap back around beginning register. instance, bytes data clocked then 65th byte will stored byte location Security Register. user programmable portion Security Register only programmed time. Therefore, possible only program first bytes register then program remaining bytes later time. Program Security Register command utilizes internal SRAM buffer processing. Therefore, contents buffer will altered from previous state when this command issued.
Figure 10-3. Program Security Register
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte Data Byte Data Byte Data Byte
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10.2.2 Reading Security Register Security Register read first asserting then clocking opcode followed three dummy bytes. After last don't care been clocked content Security Register clocked pins. After last byte Security Register been read, additional pulses will simply result undefined data being output pins. Deasserting will terminate Read Security Register operation pins into high-impedance state. Figure 10-4. Read Security Register
Each transition represents bits Opcode
Data Byte
Data Byte
Data Byte
Additional Commands
11.1 Main Memory Page Buffer Transfer
page data transferred from main memory either buffer buffer start operation DataFlash standard page size (264 bytes), 1-byte opcode, buffer buffer must clocked into device, followed three address bytes comprised don't care bits, page address bits (PA10 PA0), which specify page main memory that transferred, don't care bits. perform main memory page buffer transfer binary page size (256 bytes), opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits, page address bits (A18 which specify page main memory that transferred, don't care bits. must while toggling load opcode address bytes from input (SI). transfer page data from main memory buffer will begin when transitions from high state. During transfer page data (tXFR), status register read determine whether transfer been completed.
11.2
Main Memory Page Buffer Compare
page data main memory compared data buffer buffer initiate operation DataFlash standard page size, 1-byte opcode, buffer buffer must clocked into device, followed three address bytes consisting don't care bits, page address bits (PA10 PA0) that specify page main memory that compared buffer, don't care bits. start main memory page buffer compare binary page size, opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits, page address bits (A18 that specify page main memory that compared buffer, don't care bits. must while toggling load opcode
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address bytes from input (SI). low-to-high transition pin, data bytes selected main memory page will compared with data bytes buffer buffer During this time (tCOMP), status register will indicate that part busy. completion compare operation, status register updated with result compare.
11.3
Auto Page Rewrite
This mode only needed multiple bytes within page multiple pages data modified random fashion within sector. This mode combination operations: Main Memory Page Buffer Transfer Buffer Main Memory Page Program with Built-in Erase. page data first transferred from main memory buffer buffer then same data (from buffer buffer programmed back into original page main memory. start rewrite operation DataFlash standard page size (264 bytes), 1-byte opcode, buffer buffer must clocked into device, followed three address bytes comprised don't care bits, page address bits (PA10-PA0) that specify page main memory rewritten don't care bits. initiate auto page rewrite binary page size (256 bytes), opcode buffer buffer must clocked into device followed three address bytes consisting don't care bits, page address bits (A18 that specify page main memory that written don't care bits. When lowto-high transition occurs pin, part will first transfer data from page main memory buffer then program data from buffer back into same page main memory. operation internally self-timed should take place maximum time tEP. During this time, status register will indicate that part busy. sector programmed reprogrammed sequentially page page, then programming algorithm shown Figure 25-1 (page recommended. Otherwise, multiple bytes page several pages programmed randomly sector, then programming algorithm shown Figure 25-2 (page recommended. Each page within sector must updated/rewritten least once within every 10,000 cumulative page erase/program operations that sector.
11.4
Status Register Read
status register used determine device's ready/busy status, page size, Main Memory Page Buffer Compare operation result, Sector Protection status device density. Status Register read time, including during internally self-timed program erase operation. read status register, must asserted opcode must loaded into device. After opcode clocked 1-byte status register will clocked output (SO), starting with next clock cycle. data status register, starting with (bit will clocked during next eight clock cycles. After byte status register been clocked out, sequence will repeat itself long remains being toggled). data status register constantly updated, each repeating sequence will output data. Ready/busy status indicated using status register. then device busy ready accept next command. then device busy state. Since data status register constantly updated, user must toggle check ready/busy status. There several operations that cause device busy state: Main Memory Page Buffer Transfer, Main Memory Page Buffer Compare, Buffer Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase, Block Erase, Sector Erase, Chip Erase Auto Page Rewrite.
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result most recent Main Memory Page Buffer Compare operation indicated using status register. then data main memory page matches data buffer. then least data main memory page does match data buffer. Status Register used provide information user whether sector protection been enabled disabled, either software-controlled method hardware-controlled method. logic indicates that sector protection been enabled logic indicates that sector protection been disabled. Status Register indicates whether page size main memory array configured "power binary page size (256 bytes) DataFlash standard page size (264 bytes). then page size bytes. then page size bytes. device density indicated using bits status register. AT45DB041D, four bits 0111 decimal value these four binary bits does equate device density; four bits represent combinational code relating differing densities DataFlash devices. device density same density code indicated JEDEC device information. device density provided only backward compatibility. Table 11-1.
RDY/BUSY
Status Register Format
COMP PROTECT PAGE SIZE
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Deep Power-down
After initial power-up, device will default standby mode. Deep Power-down command allows device enter into lowest power consumption mode. enter Deep Powerdown mode, must first asserted. Once been asserted, opcode command must clocked input (SI). After last command been clocked must de-asserted initiate Deep Power-down operation. After de-asserted, will device enter Deep Power-down mode within maximum tEDPD time. Once device entered Deep Power-down mode, instructions ignored except Resume from Deep Power-down command.
Command Deep Power-down Opcode
Figure 12-1. Deep Power-down
Opcode Each transition represents bits
12.1
Resume from Deep Power-down
Resume from Deep Power-down command takes device Deep Power-down mode returns normal standby mode. Resume from Deep Power-down mode, must first asserted opcode command must clocked input (SI). After last command been clocked must de-asserted terminate Deep Power-down mode. After de-asserted, device will return normal standby mode within maximum tRDPD time. must remain high during tRDPD time before device receive commands. After resuming form Deep Powerdown, device will return normal standby mode.
Command Resume from Deep Power-down Opcode
Figure 12-2. Resume from Deep Power-Down
Opcode Each transition represents bits
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"Power Binary Page Size Option
"Power binary page size Configuration Register user-programmable nonvolatile register that allows page size main memory configured binary page size (256 bytes) DataFlash standard page size (264 bytes). "power page size one-time programmable configuration register once device configured "power page size, cannot reconfigured again. devices initially shipped with page size bytes. binary "power page size become effective, following steps must followed: Program one-time programmable configuration resister using opcode sequence 3DH, 2AH, (please Section 13.1). Power cycle device (i.e. power down power again). page binary page size programmed. above steps followed page size prior page programming, incorrect data during read operation encountered.
13.1
Programming Configuration Register
program Configuration Register "power binary page size, must first asserted would with other command. Once been asserted, appropriate 4-byte opcode sequence must clocked into device correct order. 4-byte opcode sequence must start with followed 2AH, 80H, A6H. After last opcode sequence been clocked must deasserted initiate internally self-timed program cycle. programming Configuration Register should take place time during which time Status Register will indicate that device busy. device must power-cycled after completion program cycle "power page size. device powered-down before completion program cycle, then setting Configuration Register cannot guaranteed. However, user should check status register whether page size configured binary page size. not, command re-issued again.
Command Power Page Size Byte Byte Byte Byte
Figure 13-1. Erase Sector Protection Register
Opcode Byte Each transition represents bits Opcode Byte Opcode Byte Opcode Byte
Manufacturer Device Read
Identification information read from device enable systems electronically query identify device while system. identification method command opcode comply with JEDEC standard "Manufacturer Device Read Methodology Compatible Serial Interface Memory Devices". type information that read from device includes JEDEC defined Manufacturer vendor specific Device vendor specific Extended Device Information. read identification information, must first asserted opcode must clocked into device. After opcode been clocked device will begin outputting identification data during subsequent clock cycles. first byte
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that will output will Manufacturer followed bytes Device information. fourth byte output will Extended Device Information String Length, which will indicating that Extended Device Information follows. indicated JEDEC standard, reading Extended Device Information String Length subsequent data optional. Deasserting will terminate Manufacturer Device Read operation into high-impedance state. deasserted time does require that full byte data read.
14.1
14.1.1
Value
Manufacturer Device Information
Byte Manufacturer
JEDEC Assigned Code Manufacturer Atmel
14.1.2
Value
Byte Device (Part
Family Code Density Code Family Code Density Code DataFlash 00100 4-Mbit
14.1.3
Value
Byte Device (Part
Code Product Version Code Code Product Version 1-bit/Cell Technology 00000 Initial Version
14.1.4
Value
Byte Extended Device Information String Length
Byte Count Byte Count Bytes Information
Opcode
Manufacturer Byte
Device Byte
Device Byte
Extended Device Information String Length
Data
Extended Device Information Byte
Data
Extended Device Information Byte
Each transition represents bits
This information would only output Extended Device Information String Length value something other than 00H.
Note:
Based JEDEC publication (JEP106), Manufacturer data comprised number bytes. Some manufacturers have Manufacturer codes that two, three even four bytes long with first byte(s) sequence being 7FH. system should detect code "Continuation Code" continue read Manufacturer bytes. first non-7FH byte would signify last byte Manufacturer data. Atmel (and some other manufacturers), Manufacturer data comprised only byte.
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14.2 Operation Mode Summary
commands described previously grouped into four different categories better describe which commands executed what times. Group commands consist Main Memory Page Read Continuous Array Read Read Sector Protection Register Read Sector Lockdown Register Read Security Register Group commands consist Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Buffer Transfer Main Memory Page Buffer Compare Buffer Main Memory Page Program with Built-in Erase Buffer Main Memory Page Program without Built-in Erase Main Memory Page Program through Buffer Auto Page Rewrite Group commands consist Buffer Read Buffer Write Status Register Read Manufacturer Device Read Group commands consist Erase Sector Protection Register Program Sector Protection Register Sector Lockdown Program Security Register Group command progress (not fully completed), then another command Group should started. However, during internally self-timed portion Group commands, command Group executed. Group commands using buffer should Group commands using buffer vice versa. Finally, during internally selftimed portion Group command, only Status Register Read command should executed.
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Command Tables
Table 15-1.
Command Main Memory Page Read Continuous Array Read (Legacy Command) Continuous Array Read (Low Frequency) Continuous Array Read (High Frequency) Buffer Read (Low Frequency) Buffer Read (Low Frequency) Buffer Read Buffer Read
Read Commands
Opcode
Table 15-2.
Command Buffer Write Buffer Write
Program Erase Commands
Opcode C7H, 94H, 80H,
Buffer Main Memory Page Program with Built-in Erase Buffer Main Memory Page Program with Built-in Erase Buffer Main Memory Page Program without Built-in Erase Buffer Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer Main Memory Page Program Through Buffer
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Table 15-3.
Command Enable Sector Protection Disable Sector Protection Erase Sector Protection Register Program Sector Protection Register Read Sector Protection Register Sector Lockdown Read Sector Lockdown Register Program Security Register Read Security Register
Protection Security Commands
Opcode
Table 15-4.
Command
Additional Commands
Opcode
Main Memory Page Buffer Transfer Main Memory Page Buffer Transfer Main Memory Page Buffer Compare Main Memory Page Buffer Compare Auto Page Rewrite through Buffer Auto Page Rewrite through Buffer Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer Device Read
Table 15-5.
Command Buffer Read Buffer Read
Legacy Commands(1)
Opcode
Main Memory Page Read Continuous Array Read Status Register Read Note: These legacy commands recommended designs.
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Table 15-6.
Detailed Bit-level Addressing Sequence Binary Page Size (256 Bytes)
Address Byte
Reserved Reserved Reserved Reserved Reserved
Page Size bytes
Address Byte
Address Byte Additional Don't Care Bytes
Opcode
Opcode
Notes:
Don't Care
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Table 15-7. Detailed Bit-level Addressing Sequence Standard DataFlash Page Size (264 Bytes)
Address Byte
Reserved Reserved Reserved Reserved
Page Size bytes
Address Byte
Address Byte Additional Don't Care Bytes
PA10
Opcode
Opcode
Notes:
Page Address
Byte/Buffer Address
Don't Care
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Power-on/Reset State
When power first applied device, when recovering from reset condition, device will default Mode addition, output (SO) will high impedance state, high-to-low transition will required start valid instruction. mode (Mode Mode will automatically selected every falling edge sampling inactive clock state.
16.1
Initial Power-up/Reset Timing Restrictions
power device must selected until supply voltage reaches (min.) further delay tVCSL. During power-up, internal Power-on Reset circuitry keeps device reset mode until rises above Power-on Reset threshold value (VPOR). this time, operations disabled device does respond commands. After power applied minimum operating voltage (min.), tVCSL delay required before device selected order perform read operation. Similarly, tPUW delay required after rises above Power-on Reset threshold value (VPOR) before device perform write (Program Erase) operation. After initial power-up, device will default Standby mode.
Symbol tVCSL tPUW VPOR Parameter (min.) Chip Select Power-Up Device Delay before Write Allowed Power-ON Reset Voltage Units
System Considerations
RapidS serial interface controlled clock SCK, serial input chip select pins. These signals must rise fall monotonically free from noise. Excessive noise ringing these pins misinterpreted multiple edges cause improper operation device. board traces must kept minimum distance appropriately terminated ensure proper operation. necessary, decoupling capacitors added these pins provide filtering against noise glitches. system complexity continues increase, voltage regulation becoming more important. element voltage regulation scheme current sourcing capability. Like Flash memories, peak current DataFlash occur during programming erase operation. regulator needs supply this peak current requirement. under specified regulator cause current starvation. Besides increasing system noise, current starvation during programming erase lead improper operation possible data corruption.
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Electrical Specifications
Table 18-1. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Temperature under Bias -55°C +125°C Storage Temperature -65°C +150°C Input Voltages (including Pins) with Respect Ground .-0.6V +6.25V Output Voltages with Respect Ground .-0.6V 0.6V
Table 18-2.
Operating Range
AT45DB041D (2.5V Version) AT45DB041D -40°C 85°C 2.7V 3.6V
Operating Temperature (Case) Power Supply
Ind.
-40°C 85°C 2.5V 3.6V
Table 18-3.
Symbol
Characteristics
Parameter Deep Power-down Current Standby Current Condition RESET, VIH, inputs CMOS levels RESET, VIH, inputs CMOS levels MHz; IOUT 3.6V MHz; IOUT 3.6V MHz; IOUT 3.6V MHz; IOUT 3.6V 2.7V -100 0.2V Units
ICC1(1)
Active Current, Read Operation
ICC2 Notes:
Active Current, Program/Erase Operation Input Load Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage inputs volts tolerant.
3.6V CMOS levels VI/O CMOS levels
ICC1 during buffer read maximum MHz.
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Table 18-4.
Characteristics RapidS/Serial Interface
AT45DB041D (2.5V Version) AT45DB041D Units V/ns V/ns
Symbol fSCK fCAR1 fCAR2 tSCKR(1) tSCKF(1) tCSS tCSH tDIS tWPE tWPD tEDPD tRDPD tXFR tcomp tRST tREC
Parameter Frequency Frequency Continuous Array Read Frequency Continuous Array Read (Low Frequency) High Time Time Rise Time, Peak-to-Peak (Slew Rate) Fall Time, Peak-to-Peak (Slew Rate) Minimum High Time Setup Time Hold Time Data Setup Time Data Hold Time Output Hold Time Output Disable Time Output Valid Protection Enabled High Protection Disabled High Deep Power-down Mode High Standby Mode Page Buffer Transfer Time Page Buffer Compare Time Page Erase Programming Time (256/264 bytes) Page Programming Time (256/264 bytes) Page Erase Time (256/264 bytes) Block Erase Time (2,048/2,112 bytes) Sector Erase Time (65,536/67,584 bytes) Chip Erase Time RESET Pulse Width RESET Recovery Time
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Input Test Waveforms Measurement Levels
DRIVING LEVELS 2.4V 1.5V 0.45V MEASUREMENT LEVEL
(10% 90%)
Output Test Load
DEVICE UNDER TEST
Waveforms
different timing waveforms shown page Waveform shows signal being when makes high-to-low transition, waveform shows signal being high when makes high-to-low transition. both cases, output becomes valid while signal still (SCK time specified tWL). Timing waveforms conform RapidS serial interface frequencies MHz. Waveforms compatible with Mode Mode respectively. Waveform waveform illustrate general timing diagram RapidS serial interface. These similar waveform waveform except that output restricted become valid during period. These timing waveforms valid over full frequency range (maximum frequency MHz) RapidS serial case.
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21.1
Waveform Mode Compatible (for Frequencies MHz)
tCSS HIGH IMPEDANCE VALID VALID tDIS HIGH IMPEDANCE tCSH
21.2
Waveform Mode Compatible (for Frequencies MHz)
tCSS HIGH VALID VALID tDIS HIGH IMPEDANCE tCSH
21.3
Waveform RapidS Mode (FMAX MHz)
tCSS
tCSH
HIGH IMPEDANCE
VALID
tDIS
HIGH IMPEDANCE
VALID
21.4
Waveform RapidS Mode (FMAX MHz)
tCSS
tCSH
HIGH
VALID
tDIS
HIGH IMPEDANCE
VALID
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21.5 Utilizing RapidS Function
take advantage RapidS function's ability operate higher clock frequencies, full clock cycle must used transmit data back forth across serial bus. DataFlash designed always clock data falling edge signal clock data rising edge SCK. full clock cycle operation achieved, when DataFlash clocking data falling edge SCK, host controller should wait until next falling edge latch data Similarly, host controller should clock data rising edge order give DataFlash full clock cycle latch incoming data next rising edge SCK. Figure 21-1. RapidS Mode
Slave
MOSI
BYTE-MOSI
MISO
MOSI Master Out, Slave MISO Master Slave Master host controller Slave DataFlash
BYTE-SO
Master always clocks data rising edge always clocks data falling edge SCK. Slave always clocks data falling edge always clocks data rising edge SCK. Master clocks first BYTE-MOSI rising edge SCK. Slave clocks first BYTE-MOSI next rising edge SCK. Master clocks second BYTE-MOSI same rising edge SCK. Last BYTE-MOSI clocked from Master. Last BYTE-MOSI clocked into slave. Slave clocks first BYTE-SO. Master clocks first BYTE-SO. Slave clocks second BYTE-SO. Master clocks last BYTE-SO.
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21.6
Reset Timing
tREC tCSS
tRST
RESET HIGH IMPEDANCE HIGH IMPEDANCE
(OUTPUT)
(INPUT)
Note:
signal should high state before RESET signal deasserted.
21.7
Command Sequence Read/Write Operations Page Size Bytes (Except Status Register Read, Manufacturer Device Read)
(INPUT) bits bits bits
XXXXX Don't Care Bits
XXXX XXXX
XXXX XXXX
Page Address (A18
Byte/Buffer Address A0/BFA7 BFA0)
21.8
Command Sequence Read/Write Operations Page Size Bytes (Except Status Register Read, Manufacturer Device Read)
(INPUT) bits bits bits
XXXX
XXXX XXXX Page Address (PA10 PA0)
XXXX XXXX
Don't Care Bits
Byte/Buffer Address (BA8 BA0/BFA8 BFA0)
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Write Operations
following block diagram waveforms illustrate various write sequences available.
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER MAIN MEMORY PAGE PROGRAM BUFFER MAIN MEMORY PAGE PROGRAM
BUFFER (256/264 BYTES)
BUFFER WRITE
BUFFER (256/264 BYTES)
BUFFER WRITE
INTERFACE
22.1
Buffer Write
Completes writing into selected buffer
BINARY PAGE SIZE DON'T CARE BFA7-BFA0
(INPUT)
BFA8
BFA7-0
Last Byte
22.2
Buffer Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
BINARY PAGE SIZE A18-A8 DON'T CARE BITS
(INPUT)
Each transition represents bits
PA10-7
PA6-0,
XXXX
byte read byte read
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Read Operations
following block diagram waveforms illustrate various read sequences available.
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
MAIN MEMORY PAGE BUFFER MAIN MEMORY PAGE BUFFER
BUFFER (256/264 BYTES)
BUFFER READ
BUFFER (256/264 BYTES)
MAIN MEMORY PAGE READ BUFFER READ
INTERFACE
23.1
Main Memory Page Read
ADDRESS BINARY PAGE SIZE A15-A8 A18-A16 A7-A0
(INPUT)
PA10-7
PA6-0,
BA7-0
Dummy Bytes
(OUTPUT)
23.2
Main Memory Page Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
BINARY PAGE SIZE A18-A8 DON'T CARE BITS
(INPUT)
PA10-7
PA6-0,
XXXX XXXX
(OUTPUT)
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23.3 Buffer Read
BINARY PAGE SIZE DON'T CARE BFA7-BFA0
(INPUT)
X.X, BFA8
BFA7-
Dummy Byte (opcodes D3H) Dummy Byte (opcodes D6H)
(OUTPUT)
Each transition represents bits
Detailed Bit-level Read Waveform RapidS Serial Interface Mode 0/Mode
24.1
Continuous Array Read (Legacy Opcode E8H)
OPCODE ADDRESS BITS
DON'T CARE BITS
DATA BYTE
HIGH-IMPEDANCE
PAGE
2047/2111 PAGE
24.2
Continuous Array Read (Opcode 0BH)
OPCODE ADDRESS BITS
DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
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24.3
Continuous Array Read (Low Frequency: Opcode 03H)
OPCODE ADDRESS BITS A18-A0
DATA BYTE
HIGH-IMPEDANCE
24.4
Main Memory Page Read (Opcode: D2H)
OPCODE ADDRESS BITS
DON'T CARE BITS
DATA BYTE
HIGH-IMPEDANCE
24.5
Buffer Read (Opcode D6H)
OPCODE
ADDRESS BITS BINARY PAGE SIZE DON'T CARE BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE DON'T CARE BFA8-BFA0
DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
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24.6 Buffer Read (Low Frequency: Opcode D3H)
OPCODE
ADDRESS BITS BINARY PAGE SIZE DON'T CARE BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE DON'T CARE BFA8-BFA0
DATA BYTE
HIGH-IMPEDANCE
24.7
Read Sector Protection Register (Opcode 32H)
OPCODE DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
24.8
Read Sector Lockdown Register (Opcode 35H)
OPCODE DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
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24.9
Read Security Register (Opcode 77H)
OPCODE DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
24.10 Status Register Read (Opcode D7H)
OPCODE
STATUS REGISTER DATA
STATUS REGISTER DATA
HIGH-IMPEDANCE
24.11 Manufacturer Device Read (Opcode 9FH)
OPCODE
HIGH-IMPEDANCE
DEVICE BYTE
DEVICE BYTE
Note: Each transition
shown represents byte bits)
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Auto Page Rewrite Flowchart
Figure 25-1. Algorithm Programming Reprogramming Entire Array Sequentially
START provide address data
BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER MAIN MEMORY PAGE PROGRAM (83H, 86H)
Notes: This type algorithm used applications which entire array programmed sequentially, filling array page-bypage. page written using either Main Memory Page Program operation Buffer Write operation followed Buffer Main Memory Page Program operation. algorithm above shows programming single page. algorithm will repeated sequentially each page within entire array.
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Figure 25-2. Algorithm Randomly Modifying Data
START provide address page modify MAIN MEMORY PAGE BUFFER TRANSFER (53H, 55H) planning modify multiple bytes currently stored within page Flash array
BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER MAIN MEMORY PAGE PROGRAM (83H, 86H)
AUTO PAGE REWRITE (58H, 59H)
INCREMENT PAGE ADDRESS POINTER
Notes: preserve data integrity, each page DataFlash sector must updated/rewritten least once within every 10,000 cumulative page erase program operations. Page Address Pointer must maintained indicate which page rewritten. Auto Page Rewrite command must address specified Page Address Pointer. Other algorithms used rewrite portions Flash array. Low-power applications choose wait until 10,000 cumulative page erase program operations have accumulated before rewriting pages sector. application note AN-4 ("Using Atmel's Serial DataFlash") more details.
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Ordering Information
26.1 Green Package Options (Pb/Halide-free/RoHS Compliant)
(mA) Active Standby Ordering Code AT45DB041D-SSU 0.05 AT45DB041D-SU AT45DB041D-MU AT45DB041D-SSU-2.5 0.05 AT45DB041D-SU-2.5 AT45DB041D-MU-2.5 Package 8M1-A 8M1-A Industrial (-40°C 85°C) Operation Range
fSCK (MHz)
Package Type 8M1-A 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-lead, Very Thin Micro Lead-frame Package (MLF)
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Packaging Information
27.1 JEDEC SOIC
VIEW VIEW
SYMBOL COMMON DIMENSIONS (Unit Measure NOTE
0.10
0.25
SIDE VIEW
Note: These drawings general information only. Refer JEDEC Drawing MS-012, Variation proper dimensions, tolerances, datums, etc.
3/17/05 1150 Cheyenne Mtn. Blvd. Colorado Springs, 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING REV.
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27.2 EIAJ SOIC
VIEW
VIEW
SYMBOL
COMMON DIMENSIONS (Unit Measure NOTE
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 1.27
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85
SIDE VIEW
Notes:
This drawing general information only; refer EIAJ Drawing EDR-7320 additional information. Mismatch upper lower dies resin burrs included. recommended that upper lower cavities equal. they different, larger dimension shall regarded. Determines true geometric position. Values apply plated terminal. standard thickness plating layer shall measure between 0.007 .021
4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING REV.
2325 Orchard Parkway Jose, 95131
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27.3
8M1-A
SIDE VIEW
VIEW
0.08
0.45
SYMBOL
COMMON DIMENSIONS (Unit Measure 0.85 0.65 0.20 0.35 5.90 5.70 3.20 4.90 4.70 3.80 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.50 0.25 0.60 0.75 0.48 6.10 5.80 3.60 5.10 4.80 4.20 1.00 0.05 NOTE
Notch (0.20
BOTTOM VIEW
9/8/06 2325 Orchard Parkway Jose, 95131 TITLE 8M1-A, 8-pad, 1.00 Body, Very Thin Dual Flat Package Lead (MLF) DRAWING 8M1-A REV.
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AT45DB041D
Revision History
Revision Level Revision Date October 2005 History Initial Release Added "Preliminary". Added text, "Programming Configuration Register", indicate that power cycling required switch "power page size after opcode enable been executed. Added "Legacy Commands" table. Corrected typographical errors. Corrected typographical errors. Added errata regarding Chip Erase. Removed "Preliminary". Removed RDY/BUSY references. Changed page size description from Table 15-6. Changed page size description from Table 15-7. Added additional text "power binary page size option. Removed SER/BYTE statement from descriptions Table 2-1. Changed number don't care bits from sector 1-15 erase Section 7.6. Corrected density code description from 16-Mbit 4-Mbit Section 14.1.2. Changed address opcode from Table 15-6. Chagned address opcode from Table 15-7. Changed tXFR tCOMP values from Changed tVCSL from Changed tRDPD from
March 2006
June 2006 July 2006 August 2006 November 2006 February 2007 March 2007
April 2007
August 2007
3595J-DFLASH-08/07
Errata
29.1
29.1.1
Chip Erase
Issue certain percentage units, Chip Erase feature function correctly adversely affect device operation. Therefore, recommended that Chip Erase commands (opcodes C7H, 94H, 80H, 9AH) used.
29.1.2
Workaround Block Erase (opcode 50H) alternative. Block Erase function affected Chip Erase issue.
29.1.3
Resolution Chip Erase feature fixed with revision device. Please contact Atmel estimated availability devices with fix.
AT45DB041D
3595J-DFLASH-08/07
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3595J-DFLASH-08/07

Compatible Modes User Configurable Page Size Bytes Page Byte

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