µPD70F3038, 70F3038Y, 70F3040, 70F3040Y V850/SV1 32-BIT SINGLE-CH

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µPD70F3038, 70F3038Y, 70F3040, 70F3040Y V850/SV1 32-BIT SINGLE-CH

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INTEGRATED CIRCUIT
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
V850/SV1 32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD70F3038, µPD70F3038Y, µPD70F3040, µPD70F3040Y products that substitute flash memory mask µPD703038, µPD703038Y, µPD703039, 703040, 703041, µPD703039Y, 703040Y, 703041Y, respectively. Since µPD70F3038, µPD70F3038Y, µPD70F3040, µPD70F3040Y read written while mounted board, these products ideal evaluation during system development, multipleversion small-scale production quick product release. Detailed function descriptions provided following user's manuals. sure read them before designing. V850/SV1 User's Manual Hardware: U14462E V850 Series User's Manual Architecture: U10243E
FEATURES
compatible with µPD703038, 703039, 703040, 703041, 703038Y, 703039Y, 703040Y, 703041Y mass production, these replaced mask version.
µPD70F3038 µPD703038 µPD70F3038Y µPD703038Y µPD70F3040 µPD703039, 703040, 703041 µPD70F3040Y µPD703039Y, 703040Y, 703041Y
APPLICATIONS
Camcorders (including DVC)
information this document subject change without notice. Before using this document, please confirm that this latest version.
products and/or types available every country. Please check with Electronics sales representative availability additional information.
Document U14622EJ2V1DS00 (2nd edition) Date Published August 2005 CP(K) Printed Japan
mark
shows major revised points.
Electronics Corporation 2000
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
ORDERING INFORMATION
Part Number Package 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA 176-pin plastic LQFP (fine pitch) 176-pin plastic LQFP (fine pitch) 180-pin plastic FBGA 180-pin plastic FBGA 176-pin plastic LQFP (fine pitch) 176-pin plastic LQFP (fine pitch) 180-pin plastic FBGA 180-pin plastic FBGA
µPD70F3038F1-EN2 µPD70F3038F1-EN2-A µPD70F3038YF1-EN2 µPD70F3038YF1-EN2-A µPD70F3040GM-UEU µPD70F3040GM-UEU-A µPD70F3040F1-EN2 µPD70F3040F1-EN2-A µPD70F3040YGM-UEU µPD70F3040YGM-UEU-A µPD70F3040YF1-EN2 µPD70F3040YF1-EN2-A
Remark Products with part number lead-free products.
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal Internal None Provided (flash memory) None Provided (mask ROM) None Provided (mask ROM) None Provided None Provided (mask ROM) None Provided None
Provided
µPD70F3038 µPD70F3038Y µPD70F3040 µPD70F3040Y µPD703038 µPD703038Y µPD703039 µPD703039Y µPD703040 µPD703040Y µPD703041 µPD703041Y
(flash memory)
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
CONFIGURATION
176-pin plastic LQFP (fine pitch)
µPD70F3040GM-UEU µPD70F3040YGM-UEU
µPD70F3040GM-UEU-A µPD70F3040YGM-UEU-A
P12/SCK0/SCL0Note P13/SI1/RXD0 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note P21/SO2 P22/SCK2/SCL1Note P23/SI3/RXD1 P24/SO3/TXD1 P25/SCK3/ASCK1 P26/TI2/TO2 P27/TI3/TO3 P30/TI000 P31/TI001 P32/TI010 P33/TI011 P34/TO0 P35/TO1 P36/TI4/TO4 P37/TI5/TO5 P120/SI4 P121/SO4 P122/SCK4 P123/CLO P124/TI6/TO6 P125/TI7/TO7 P126/TI10/TO10 P127/TI11/TO11 P180 P181 P182 P183 P184 P185 P186 P187 P190 P191 P192 P193
P11/SO0 P10/SI0/SDA0Note P113 P112 P111 P110 WAIT CLKOUT P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P96/HLDRQ P95/HLDAK P94/ASTB P93/DSTB/RD P92/R/W/WRH P91/UBEN P90/LBEN/WRL AVDD AVSS AVREF
P87/ANI15 P86/ANI14 P85/ANI13 P84/ANI12 P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 P147 P146 P145/RTPTRG1 P144/TI9/INTTI9 P143/INTCP93 P142/INTCP92 P141/INTCP91 P140/INTCP90 P137/TO81 P136/TO80 P135/TCLR8/INTTCLR8 P134/TI8/INTTI8 P133/INTCP83 P132/INTCP82 P131/INTCP81 P130/INTCP80 P07/INTP6 P06/INTP5/RTPTRG0 P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P157/RTP17 P156/RTP16
Notes Connect normal operation mode. SCL0, SCL1, SDA0, SDA1 valid only µPD70F3040Y.
P194 P195 P196 P197 P170/KR0 P171/KR1 P172/KR2 P173/KR3 P174/KR4 P175/KR5 P176/KR6 P177/KR7 P160/PWM0 P161/PWM1 P162/PWM2 P163/PWM3 P164/CSYNCIN P165/VSOUT P166/HSOUT0 P167/HSOUT1 VPPNote RESET P100/RTP00 P101/RTP01 P102/RTP02 P103/RTP03 P104/RTP04 P105/RTP05 P106/RTP06 P107/RTP07 P150/RTP10 P151/RTP11 P152/RTP12 P153/RTP13 P154/RTP14 P155/RTP15
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
180-pin plastic FBGA PD70F3038F1-EN2
PD70F3038YF1-EN2 PD70F3040F1-EN2 PD70F3040YF1-EN2
View
PD70F3038F1-EN2-A PD70F3038YF1-EN2-A PD70F3040F1-EN2-A PD70F3040YF1-EN2-A
Bottom View
Number
Note
Name
Number
Note
Name
Number
Name
Number
Name
P13/SI1/RXD0 P12/SCK0/SCL0 P113 P110 P64/A20 P60/A16 P54/AD12 P50/AD8 P46/AD6 P42/AD2 P94/ASTB P91/UBEN AVDD P87/ANI15
Note
P15/SCK1/ASCK0 P20/SI2/SDA1
Note
P23/SI3/RXD1 P21/SO2 P22/SCK2/SCL1 P24/SO3/TXD1 WAIT P61/A17 P55/AD13 P51/AD9 P47/AD7 P43/AD3 P96/HLDRQ P90/LBEN/WRL P81/ANI9 P84/ANI12 P83/ANI11
Note
P11/SO0 P10/SI0/SDA0 P112 CLKOUT P62/A18 P57/AD15 P53/AD11 BVSS P45/AD5 P41/AD1 AVSS AVREF
Note
P14/SO1/TXD0 P111 P65/A21 P63/A19 P56/AD14 P52/AD10 BVDD P44/AD4 P40/AD0 P93/DSTB/RD P82/ANI10 P86/ANI14 P85/ANI13
Notes
Leave open. SCL0, SCL1, SDA0, SDA1 valid only µPD70F3038Y 70F3040Y.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Number
Name
Number
Name
Number
Name
Number
Name
P27/TI3/TO3 P25/SCK3/ASCK1 P26/TI2/TO2 P95/HLDAK P92/R/W/WRH P76/ANI6 P77/ANI7 P80/ANI8 P30/TI000 P31/TI001 P32/TI010 P33/TI011 P74/ANI4 P72/ANI2 P75/ANI5 P70/ANI0 P35/TO1 P34/TO0 P36/TI4/TO4 P37/TI5/TO5 P73/ANI3 P147 P71/ANI1 P145/RTPTRG1 P121/SO4 P120/SI4 P122/SCK4 P123/CLO
P144/TI9/INTTI9 P143/INTCP93 P146 P141/INTCP91 P125/TI7/TO7 P124/TI6/TO6 P126/TI10/TO10 P127/TI11/TO11 P140/INTCP90 P137/TO81 P142/INTCP92 P135/TCLR8/INTTCLR8 P181 P180 P182 P183 P134/TI8/INTTI8 P133/INTCP83 P136/TO80 P132/INTCP82 P185 P184 P187 P190 P07/INTP6 P131/INTCP81 P130/INTCP80
P186 P170/KR0 P174/KR4 P177/KR7 P163/PWM3 P167/HSOUT1 RESET P103/RTP03 P01/INTP0 P04/INTP3 P05/INTP4/ADTRG P03/INTP2 P06/INTP5/RTPTRG0 P191 P192 P197 P173/KR3 P175/KR5 P162/PWM2 P166/HSOUT0 P102/RTP02 P106/RTP06 P157/RTP17 P00/NMI P02/INTP1
P193 P195 P196 P176/KR6 P160/PWM0 P164/CSYNCIN P100/RTP00 P104/RTP04 P107/RTP07 P150/RTP10 P152/RTP12 P153/RTP13 P156/RTP16
Note Note
P194 P171/KR1 P172/KR2 P161/PWM1 P165/VSOUT P101/RTP01 P105/RTP05 P151/RTP11 P154/RTP14 P155/RTP15
Note
Notes
Connect this during normal operation mode. Leave open.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
IDENTIFICATION
A21: AD15: ADTRG: ANI0 ANI15: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: CLO: CSYNCIN: DSTB: HLDAK: HLDRQ: Address Address/data trigger input Analog input Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground interface power supply interface ground Clock output Clock output (divided) Csync input Data strobe Hold acknowledge Hold request P120 P127: P130 P137: P140 P147: P150 P157: P160 P167: P170 P177: P180 P187: P190 P197: PWM0 PWM3: RESET: RTP00 RTP07,: RTP10 RTP17 RTPTRG0, RTPTRG1: trigger input R/W: RXD0, RXD1: SCK0 SCK4: SCL0, SCL1: SDA0, SDA1: SI4: SO4: TCLR8: return Lower byte enable Non-maskable interrupt request Port Port Port Port Port Port Port Port Port Port Port Port TI011, TI11 TO7, TO80,: TO81, TO10, TO11 TXD0, TXD1: UBEN: VDD: VPP: VSOUT: VSS: WAIT: WRH: WRL: XT1, XT2: Transmit data Upper byte enable Power supply Programming power supply Vsync output Ground Wait Write strobe high level data Write strobe level data Crystal main system clock Crystal subsystem clock Timer output Read/write status Receive data Serial clock Serial clock Serial data Serial input Serial output Timer clear Port Port Port Port Port Port Port Port Pulse width modulation Read Reset Real-time output port
HSOUT0, HSOUT1: Hsync output INTCP80 INTCP83,: Interrupt request from peripherals INTCP90 INTCP93, INTP0 INTP6, INTTCLR8, INTTI8, INTTI9 KR7: LBEN: NMI: P07: P15: P27: P37: P47: P57: P65: P77: P87: P96: P100 P107: P110 P113:
TI000, TI001, TI010,: Timer input
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
INTERNAL BLOCK DIAGRAM
INTP0 INTP6 INTCP80 INTCP83, INTCP90 INTCP93 INTTCLR8 INTTI8, INTTI9 TI000, TI001, TI010, TI011 TO0, TO80, TO81 TI8, TCLR8 TI2/TO2, TI3/TO3 TI4/TO4, TI5/TO5 TI6/TO6, TI7/TO7 TI10/TO10, TI11/TO11 CSYNCIN HSOUT0, HSOUT1, VSOUT SI0/SDA0Note SCK0/SCL0Note SI2/SDA1Note SCK2/SCL1Note SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SCK4
INTC
correction Multiplier
Instruction queue
HLDRQ HLDAK ASTB DSTB/RD R/W/WRH UBEN LBEN/WRL WAIT AD15
Note Timer/counter 16-bit timers: TM0, 8-bit timers: TM7, TM10, TM11 24-bit timers: TM8,
32-bit barrel shifter System registers General registers bits
Vsync/Hsync CSI0/I2C0Note Ports CSI2/I2C1Note CSI1/UART0 CSI3/UART1 Variablelength CSI4 return function DMAC:
P190 P197 P180 P187 P170 P177 P160 P167 P150 P157 P140 P147 P130 P137 P120 P127 P110 P113 P100 P107
converter
AVDD AVREF AVSS ANI0 ANI15 ADTRG
CLKOUT RESET
Watch timer Watchdog timer RTP00 RTP07, RTP10 RTP17 RTPTRG0, RTPTRG1
BVDD BVSS
PWM0 PWM3
Notes µPD70F3038, 70F3038Y (flash memory) µPD70F3040, 70F3040Y (flash memory) SDA0, SDA1, SCL0, SCL1 valid only 70F3038Y µPD70F3040Y. function valid only µPD703038Y 70F3040Y.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
CONTENTS
FUNCTIONS.
Port Pins Non-Port Pins Circuits, Buffer Supply, Recommended Connection Unused Pins.17
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
FUNCTIONS Port Pins
(1/4)
Name Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 6-bit port Input/output mode specified 1-bit units. PULL Port 8-bit port Input/output mode specified 1-bit units. Function Alternate Function INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI000 TI001 TI010 TI011 TI4/TO4 TI5/TO5
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(2/4)
Name Port 7-bit port Input/output mode specified 1-bit units. Input Port 8-bit input port Input Port 8-bit input port Port 6-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. PULL Port 8-bit port Input/output mode specified 1-bit units. Function Alternate Function AD10 AD11 AD12 AD13 AD14 AD15 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(3/4)
Name P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P120 P121 P122 P123 P124 P125 P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P140 P141 P142 P143 P144 P145 P146 P147 Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. SCK4 TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 INTCP81 INTCP82 INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80 TO81 INTCP90 INTCP91 INTCP92 INTCP93 TI9/INTTI9 RTPTRG1 Port 4-bit port Input/output mode specified 1-bit units. PULL Port 7-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Function Alternate Function ASTB HLDAK HLDRQ RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP06 RTP07
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(4/4)
Name P150 P151 P152 P153 P154 P155 P156 P157 P160 P161 P162 P163 P164 P165 P166 P167 P170 P171 P172 P173 P174 P175 P176 P177 P180 P181 P182 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P195 P196 P197 Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. PULL Port 8-bit port Input/output mode specified 1-bit units. Function Alternate Function RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RTP16 RTP17 PWM0 PWM1 PWM2 PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Non-Port Pins
(1/4)
Name AD15 ADTRG ANI0 ANI7 ANI8 ANI15 ASCK0 ASCK1 ASTB AVDD AVREF AVSS BVDD BVSS CLKOUT CSYNCIN DSTB HLDAK HLDRQ HSOUT0 HSOUT1 INTCP80 INTCP83 INTCP90 INTCP93 INTP0 INTP3 INTP4 INTP5 INTP6 External interrupt request input (digital noise elimination supporting remote controller) Input External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination) P05/ADTRG P06/RTPTRG0 Input External capture input CP90 CP93 P140 P143 Input Output Input Output Output Input Output Output Input Output External address strobe signal output Positive power supply converter ports used alternate functions Reference voltage input converter Ground potential converter ports used alternate functions Positive power supply interface ports used alternate functions Ground potential interface ports used alternate functions Internal system clock output output signal Csync signal input External data strobe signal output hold acknowledge output hold request input Hsync signal output before compensation Hsync signal output after compensation External capture input CC80 CC83 P123 P164 P93/RD P166 P167 P130 P133 Input Input Input Input Baud rate clock input UART0 UART1 converter external trigger input Analog input converter Output PULL Address Address/data multiplexed Function Alternate Function P05/INTP4 P15/SCK1 P25/SCK3
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(2/4)
Name INTTCLR8 INTTI8 INTTI9 LBEN PWM0 PWM3 RESET RTP00 RTP07 RTP10 RTP17 RTPTRG0 RTPTRG1 RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 SCK4 SCL0 SCL1 SDA0 SDA1 TCLR8 Input Variable-length CSI4 serial transmit data output External clear input Output Variable-length CSI4 serial receive data input Serial transmit data output CSI0 CSI3 Input Variable-length CSI4 serial clock Serial clock (µPD70F3038Y, 70F3040Y) Serial transmit/receive data (µPD70F3038Y, 70F3040Y) Serial receive data input CSI0 CSI3 (3-wire mode)
Input Input
PULL
Function External interrupt request input (digital noise elimination)
Alternate Function P135/TCLR8 P134/TI8 P144/TI9
Input Output Input Output Output Input Output
return input Lower byte enable signal output external data Non-maskable interrupt request input Output channels read strobe signal output System reset input Real-time output port
P170 P177 P90/WRL P160 P163 P93/DSTB P100 P107 P150 P157
Input
external trigger input
P145
Output Input
External read/write status output Serial receive data input UART0 UART1
P92/WRH P13/SI1 P23/SI3
Serial clock CSI0 CSI3 (3-wire mode)
P12/SCL0 P15/ASCK0 P22/SCL1 P25/ASCK1 P122 P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0 P13/RXD0 P20/SDA1 P23/RXD1 P120 P14/TXD0 P24/TXD1 P121 P135/INTTCLR8
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(3/4)
Name TI000 TI001 TI010 TI011 TI10 TI11 TO80 TO81 TO10 TO11 TXD0 TXD1 UBEN VSOUT WAIT Output Output Input Output Higher byte enable signal output external data Positive power supply High voltage application program write/verify Vsync signal output Ground potential External WAIT signal input Higher byte write strobe signal output external data Lower byte write strobe signal output external data P92/R/W P90/LBEN P165 Output Output Input PULL Function External count clock input/external capture trigger input External capture trigger input External count clock input/external capture trigger input External capture trigger input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input TM10 External count clock input TM11 Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output TM10 Pulse signal output TM11 Serial transmit data output UART0 UART1 Alternate Function P26/TO2 P27/TO3 P36/TO4 P37/TO5 P124/TO6 P125/TO7 P134/INTTI8 P144/INTTI9 P126/TO10 P127/TO11 P26/TI2 P27/TI3 P36/TI4 P37/TI5 P124/TI6 P125/TI7 P136 P137 P126/TI10 P127/TI11 P14/SO1 P24/SO3
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
(4/4)
Name Input Input Resonator connection subsystem clock PULL Function Resonator connection main system clock Alternate Function
Remark
PULL: On-chip pull-up resistor
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Circuits, Buffer Supply, Recommended Connection Unused Pins
Table shows circuit type each recommended connection unused pins. configuration each circuit type, refer Figure 1-1. Table 1-1. Types Circuits Recommended Connection Unused Pins (1/2)
P26, P30, P32, P34, P100 P107 P110 P113 P120 INTP0 INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2, TI3/TO3 TI000, TI001 TI010, TI011 TO0, TI4/TO4 TI5/TO5 AD15 ANI0 ANI7 ANI8 ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP00 RTP07 10-E Output: Input: Independently connect resistor Leave open Output: BVDD BVDD BVDD AVDD AVDD BVDD Input: Independently connect BVDD BVSS resistor Leave open Output: Input: Independently connect BVDD BVSS resistor Leave open 10-F 10-E 10-F 10-E 10-F 10-F 10-E 10-F 10-E 10-F Output: Alternate Function Circuit Type Buffer Power Supply Input: Independently connect resistor Leave open Recommended Connection Method
Connect AVSS
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Table 1-1. Types Circuits Recommended Connection Unused Pins (2/2)
P121 P122 P123 P124 P125 P126 P127 P130 P133 P134 P135 P136, P137 P140 P143 P144 P145 P146, P147 P150 P157 P160 P163 P164 P165 P166 P167 P170 P177 P180 P187 P190 P197 CLKOUT WAIT RESET AVREF AVDD AVSS BVDD BVSS Alternate Function SCK4 TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80, TO81 INTCP90 INTCP93 TI9/INTTI9 RTPTRG1 RTP10 RTP17 PWM0 PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1 16-A 16-A BVDD BVDD Connect Connect Connect Connect Leave open Connect Leave open Connect AVSS Connect Leave open Connect resistor Circuit Type 10-G 10-H Output: Buffer Power Supply Input: Independently connect resistor Leave open Recommended Connection Method
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Figure 1-1. Circuits (1/2)
Type
Type
P-ch
Data
P-ch IN/OUT
N-ch
Output disable
N-ch
Input enable
Type
Type
Pullup enable
P-ch
P-ch IN/OUT
Data
Output disable
Input enable
N-ch
Schmitt-triggered input with hysteresis characteristics
Type
Type
Data
Data
P-ch
P-ch IN/OUT
Output disable
N-ch
Output disable
N-ch
Push-pull output that high impedance output (both P-ch N-ch off)
Input enable
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Figure 1-1. Circuits (2/2)
Type
Type 10-G
Pull-up enable Data
P-ch
Data
P-ch IN/OUT
P-ch IN/OUT
Open drain Output disable N-ch
Output disable Input enable Type
N-ch Input enable
Type 10-H P-ch Comparator Data P-ch IN/OUT Open drain Output disable N-ch
N-ch
VREF (Threshold voltage)
Input enable
Input enable
Type 10-E
Type 16-A
Pull-up enable Data
P-ch P-ch IN/OUT
Open Output disable Input enable Type 10-F
N-ch
Pull-up enable Data
P-ch P-ch IN/OUT
Open Output disable Input enable
N-ch
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C,
Parameter Supply voltage Symbol AVDD BVDD AVSS BVSS Input voltage Clock input voltage Analog input voltage Analog reference input voltage Output current, VIAN AVREF Note (VDD) Note (BVDD) Note (AVDD) AVREF Total P150 P157 Total P100 P107 P160 P167 Total P170 P177 P190 P197 Total P124 P127 P180 P187 Total P120 P123 Total P15, P110 P113 Total P57, P65, CLKOUT Total Total P130 P137 P140 P147 Output current, high Total P150 P157 Total P100 P107 P160 P167 Total P170 P177 P190 P197 Total P124 P127 P180 P187 Total P120 P123 Total P15, P110 P113 Total P57, P65, CLKOUT Total Total P130 P137 P140 P147 Output voltage Operating ambient temperature Storage temperature Tstg Note 3.6V Note CLKOUT, BVDD 3.6V Normal operation mode Flash programming mode Conditions Ratings -0.5 +4.6 -1.5 +8.5 -0.5 +4.6 -0.5 +4.6 -0.5 +0.5 -0.5 +0.5 -0.5 +0.5 -0.5 -0.5
Note Note
Unit
Note Note
-0.5 BVDD -0.5 AVDD -0.5 AVDD -4.0 -0.5 +125 -0.5 BVDD
Note Note Note
Notes
Ports (includes alternate function pins) Ports (includes alternate function pins) Ports (includes alternate function pins) sure exceed each absolute maximum rating (MAX.).
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Cautions Avoid direct connections among device output I/O) pins between GND. However, direct connections among open-drain open-connector pins possible, direct connections external circuits that have timing designed prevent output contention with pins that become high-impedance. Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. ratings conditions indicated characteristics characteristics represent quality assurance range during normal operation.
Capacitance 25°C, AVDD BVDD AVSS BVSS)
Parameter Input capacitance capacitance Output capacitance Symbol Conditions Unmeasured pins returned MIN. TYP. MAX. Unit
Operating Conditions operating frequency
Parameter operating frequency Symbol fCPU Conditions MIN. TYP. MAX. Unit
Operating frequency each supply voltage
Operating Frequency 32.768 (only watch operation) Supply Voltage (VDD AVDD BVDD)
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Recommended Oscillator
Main clock oscillator +85°C) Ceramic crystal resonator connection
Parameter Oscillation frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation stabilization time
After reset release After STOP mode release
/fXX Note
Note Values vary depending settings oscillation stabilization selection register (OSTS). Remarks Place oscillator close possible wire other signal lines within broken lines. resonator selection oscillation constants, customers advised either evaluate oscillation themselves, apply resonator manufacturer evaluation. External clock input
Open
High-speed CMOS inverter External clock
Parameter Input frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Cautions
Place high-speed CMOS inverter close possible pin. Perform sufficient evaluation determine whether µPD70F3038, 70F3038Y, 70F3040, 70F3040Y matches high-speed inverter.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Subclock oscillator +85°C)
Parameter Oscillation frequency Oscillation stabilization time
Symbol
Conditions
MIN.
TYP. 32.768
MAX.
Unit
Remarks Place oscillator close possible XT2. wire other signal lines within broken lines. resonator selection oscillation constants, customers advised either evaluate oscillation themselves, apply resonator manufacturer evaluation.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Characteristics operation +85°C, AVDD BVDD AVSS BVSS
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, VIL1 VIL2 VIL3 VIL4 VIL5 supply current Output voltage, high VPP1 VOH1 VOH2 Output voltage, VOL1 VOL2 VOL3 Input leakage current, high ILIH1 ILIH2 Input leakage current, ILIL1 ILIL2 Output leakage current, high Output leakage current, Supply current ILOH ILOL IDD1 IDD2 IDD3 IDD4 AVDD BVDD Normal operation (fXX MHz) HALT mode (fXX MHz) IDLE mode (fXX MHz) STOP mode (subclock operation: 32.768 kHz, watch timer operation STOP mode (subclock stopped, VSS) Pull-up resistor Conditions Pins Note WAIT Pins Note Pins Note RESET Pins Note Pins Note WAIT Pins Note Pins Note RESET Pins Note During normal operation Note CLKOUT Notes Note CLKOUT Notes (excluding P10, P12, P20, P22) P10, P12, P20, AVDD BVDD Other than Other than MIN. 0.7BVDD 0.7VDD 0.75VDD 0.7AVDD 0.8VDD BVSS AVSS 0.8BVDD 0.8VDD TYP. MAX. BVDD AVDD 0.3BVDD 0.3VDD 0.2VDD 0.3AVDD 0.2VDD 0.2VDD Unit
Notes Ports (includes alternate function pins) P11, P14, P21, P24, P34, P35, P100 P107, P110 P113, P121, P123, P136, P137, P146, P147, P150 P157, P160 P163, P165 P167, P180 P187, P190 P197 (includes alternate function pins) P07, P10, P12, P13, P15, P20, P22, P23, P27, P33, P36, P37, P120, P122, P124 P127, P130 P135, P140 P145, P164, P170 P177 (includes alternate function pins) Ports (includes alternate function pins) Caution TYP. value current that consumed output buffers included.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
operation +85°C, AVDD BVDD AVSS BVSS
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, VIL1 VIL2 VIL3 VIL4 VIL5 supply voltage Output voltage, high VPP1 VOH1 VOH2 Output voltage, VOL1 VOL2 Conditions Pins Note WAIT Pins Note Pins Note RESET Pins Note Pins Note WAIT Pins Note Pins Note RESET Pins Note Normal operation Note CLKOUT Notes Note CLKOUT MIN. BVDD 0.75 AVDD BVSS AVSS BVDD TYP. MAX. BVDD AVDD BVDD AVDD Unit
Notes (excluding P10, P12, P20, P22)
VOL3 Input high Input leakage current, leakage current, ILIH1 ILIH2 ILIL1 ILIL2 Output leakage current, high Output leakage current, Supply current ILOL IDD1 IDD2 IDD3 IDD4 ILOH
P10, P12, P20,
AVDD Other than BVDD Other than AVDD BVDD
Normal operation (fXX MHz) HALT mode (fXX MHz) IDLE mode (fXX MHz) STOP mode (subclock operation: 32.768 kHz, watch timer operation) STOP mode (subclock stopped, VSS)
Pull-up resistor
Notes Ports (includes alternate function pins) P11, P14, P21, P24, P34, P35, P100 P107, P110 P113, P121, P123, P136, P137, P146, P147, P150 P157, P160 P163, P165 P167, P180 P187, P190 P197 (includes alternate function pins) P07, P10, P12, P13, P15, P20, P22, P23, P27, P33, P36, P37, P120, P122, P124 P127, P130 P135, P140 P145, P164, P170 P177 (includes alternate function pins) Ports (includes alternate function pins) Caution TYP. value current that consumed output buffers included.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Data Retention Characteristics +85°C, AVSS BVSS 50pF)
Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage tDREL VIHDR VILDR input ports input ports VIHn VDDDR VILn Symbol VDDDR IDDDR tRVD tFVD tHVD Conditions STOP mode VDDDR [V], MIN. TYP. MAX. Unit
Remark
Setting STOP mode tHVD
tFVD
tRVD
VDDDR
tDREL
RESET (input)
VIHDR
STOP release interrupt (NMI, etc.) (when STOP mode released falling edge)
VIHDR
STOP release interrupt (NMI, etc.) (when STOP mode released rising edge)
VILDR
Cautions
sure shift return from STOP mode when higher (when MHz) higher (when MHz). lowest operating voltage (when MHz) V850/SV1.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Characteristics Test Input Measurement points (VDD, BVDD, AVDD)
Measurement points
Test Output Measurement points (BVDD, VDD)
BVDD
Measurement points
Load Conditions
(Device Under Test)
Caution load capacitance exceeds circuit configuration, bring load capacitance device less inserting buffer some other means.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Clock Timing operation +85°C, AVDD BVDD AVSS BVSS
Parameter input cycle input high-level width input low-level width input rise time input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol tCYX tWXH tWXL tCYK tWKH tWKL <10> 62.5 0.4tCYK-10 0.4tCYK-10 Conditions MIN. 62.5 28.2 28.2 (<1>-<2>-<3>) (<1>-<2>-<3>) MAX. Unit
operation +85°C, AVDD BVDD AVSS BVSS
Parameter input cycle input high-level width input low-level width input rise time input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tCYX tWXH tWXL tCYK tWKH tWKL Symbol <10> 0.4tCYK-10 0.4tCYK-10 Conditions MIN. 50.0 22.5 22.5 (<1>-<2>-<3>) (<1>-<2>-<3>) MAX. Unit
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Clock Timing
(input)
CLKOUT (output)
<10>
Timing Pins Other Than CLKOUT, Pins +85°C, AVDD BVDD AVSS BVSS
Parameter Output rise time Output fall time Symbol <11> <12> Conditions MIN. MAX. Unit
<11>
<12>
Output signal
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Timing (CLKOUT Asynchronous) +85°C, AVDD BVDD AVSS BVSS
Parameter Address setup time ASTB) Address hold time (from ASTB) Delay time from DSTB address float Setup time from address data input Setup time from DSTB data input Delay time from ASTB DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB ASTB Delay time from DSTB ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time DSTB) Data output hold time (from DSTB) WAIT setup time address) Symbol tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK output Delay time from HLDRQ HLDAK Delay time from HLDRQ HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> <39> <40> 0.5T 7.5)T 1.5T (0.5 (1.5 1.5T (1.5 0.5T 0.5T (1.5 Conditions MIN. 0.5T 0.5T MAX. Unit
Remarks 1/fCPU (fCPU: operation clock frequency) Number wait clocks inserted cycle. Sampling timing changes when programmable wait inserted. Number idle states inserted after read cycle specifications described above values when clock with duty ratio input from
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Timing (CLKOUT Synchronous) +85°C, AVDD BVDD AVSS BVSS
Parameter Delay time from CLKOUT address Delay time from CLKOUT address float Delay time from CLKOUT ASTB Delay time from CLKOUT DSTB Data input setup time CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT data output WAIT setup time CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT float Delay time from CLKOUT HLDAK tSWTK tHKWT tSHQK tHKHQ tDKF tDKHA <48> <49> <50> <51> <52> <53> tDKST tDKD tSIDK tHKID tDKOD <43> <44> <45> <46> <47> Symbol tDKA tFKA <41> <42> Conditions MIN. MAX. Unit
Remark specifications described above values when clock with duty ratio input from
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Read Cycle (CLKOUT Synchronous/Asynchronous, Wait)
CLKOUT (output)
<41>
(output), Note
<16> <45> <42> <46>
AD15 (I/O)
Address <43> <14> <13>
Hi-Z
Data
<43> <19>
ASTB (output)
<24> <44> <18> <15> <17> <44> <21> <20> <22> <23> <48>
DSTB (output), (output)
<32> <48> <34> <33> <35> <49> <49>
WAIT (input)
<28> <30> <29> <31>
Note (output), UBEN (output), LBEN (output) Remark high level.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Write Cycle (CLKOUT Synchronous/Asynchronous, Wait)
CLKOUT (output)
<41>
(output), Note
<47>
AD15 (I/O)
Address
Data <43>
<43> <13> <14>
ASTB (output)
<24>
<21> <44>
<18> <25> <44> <26>
<27>
DSTB (output), (output), (output)
<32> <48> <34> <33> <35> <49> <23> <48> <49>
WAIT (input)
<28> <30> <29> <31>
Note (output), UBEN (output), LBEN (output) Remark high level.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Hold
CLKOUT (output) <50> <51>
<50> <36>
HLDRQ (input)
<53> <39> <40>
<53>
HLDAK (output) <52> <37> (output), Note Hi-Z <38>
AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), (output), (output), (output)
Hi-Z
Note (output), UBEN (output), LBEN (output)
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Reset/Interrupt Timing +85°C, AVDD BVDD AVSS BVSS
Parameter RESET high-level width RESET low-level width high-level width low-level width INTPn high-level width Symbol tWRSH tWRSL tWNIH tWNIL tWITH <54> <55> <56> <57> <58> analog noise elimination digital noise elimination digital noise elimination INTPn low-level width tWITL <59> analog noise elimination digital noise elimination digital noise elimination Conditions MIN. 3Tsmp 3Tsmp MAX. Unit
Remarks 1/fXX Tsmp Noise elimination sampling clock frequency Reset
<54>
<55>
RESET (input)
Interrupt
<56>
<57>
(input)
<58>
<59>
INTPn (input)
Remark
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Input Timing +85°C, AVDD =BVDD AVSS BVSS
Parameter Tl0n0, Tl0n1 High-level width High-level width Tl0n0, Tl0n1 Low-level width Low-level width tTIL <61> 2Tsam
Note
Symbol tTIIH <60>
Conditions
MIN. 2Tsam
Note
MAX.
Unit
Note Tsam selected setting PRMn2 PRMn0 bits prescaler mode registers (PRMn0, PRMn1) (PRM00, PRM01 registers): Tsam 16T, 64T, 256T, 1/INTWTN period (PRM10, PRM11 registers): Tsam 16T, 32T, 128T, 256T However, when TIn0 valid edge selected count clock, Tsam Remark I/fXX
<60>
<61>
Remark 000, 001, 010, 011,
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
3-Wire Timing Master mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCKn cycle time SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <62> <63> <64> <65> <66> <67> Conditions MIN. MAX. Unit
Remark Slave mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCKn cycle time SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <62> <63> <64> <65> <66> <67> Conditions MIN. MAX. Unit
Remark
<62> <63> <64>
SCKn (I/O)
<65> <66>
(input)
<67>
(output)
Remark
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
3-Wire Variable-Length Timing Master mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width setup time SCK4) hold time (from SCK4) Delay time from SCK4 output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <68> <69> <70> <71> <72> <73> Conditions MIN. MAX. Unit
Slave mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width setup time SCK4) hold time (from SCK4) Delay time from SCK4 output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <68> <69> <70> <71> <72> <73> Conditions MIN. MAX. Unit
<68> <69> <70>
SCK4 (I/O)
<71> <72>
(input)
<73>
(output)
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
UART Timing +85°C, AVDD BVDD AVSS BVSS
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol tKCY13 tKH13 tKL13 <74> <75> <76> Conditions MIN. MAX. Unit
Remark
<74> <75> <76>
ASCKn (input)
Remark
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Mode (Only µPD70F3038Y 70F3040Y) +85°C, AVDD BVDD AVSS BVSS
Parameter Symbol Standard Mode MIN. SCLn clock frequency free time (between stop/start conditions) Hold time
Note
High-Speed Mode MIN. MAX.
Unit
MAX.
fCLK tBUF tLOW tHIGH <77> <78> <79> <80> <81> <82>
Note
SCLn clock low-level width SCLn clock high-level width Setup time start/restart conditions Data hold time Data setup time Rising time SDAn SCLn signals Falling time SDAn SCLn signals Setup time stop condition Pulse width spike suppressed input filter Load capacitance line
CBUS-compatible master mode
Note Note Note Note
Note
<83> <84> <85> <86> <87>
1000
0.1Cb 0.1Cb
Notes first clock pulse start condition generated after hold time. system must internally provide least hold time SDAn signal VIHmin. SCLn signal) order fill undefined period that appears SCLn falling edge. system does extend low-state hold time (tLOW), only maximum data hold time (tHD: satisfied. high-speed available standard mode system. this case, following conditions should satisfied. When system does extend low-state hold time SCLn signal tSU: When system extends low-state hold time SCLn signal Send next data SDAn line before SCLn line released (tRmax. tSU: 1250 Standard mode specification). Total capacitance line (Unit: Remarks maximum operating frequency MHz. However, when MHz, system with
DAT)
1000
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Mode (Only µPD70F3038Y 70F3040Y)
<79>
<80>
SCLn
<84> <85> <78> <82> <83> <81> <78> <87> <86>
SDAn
<77> <85> <84>
Stop condition
Start condition
Restart condition
Stop condition
Remark
Converter +85°C, AVDD AVREF AVSS
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN.
TYP.
MAX. ±0.8
Unit %FSR
Conversion time Zero-scale error Full-scale error
Note
tCONV
±0.4 ±0.4
%FSR %FSR
Note Note Note
Integral linearity error
±4.0 ±4.0 AVREF VIAN AIREF AIDD AIDDS During normal operation During STOP mode AVREF AVDD AVSS AVREF
Differential linearity error
Analog reference voltage Analog input voltage AVREF current converter supply current
Notes Excluding quantization error (±0.05%FSR) Excluding quantization error (±0.5LSB) Remark LSB: Least Significant FSR: Full Scale Range
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Flash Memory Programming Mode Basic Characteristics AVDD BVDD AVSS BVSS
Parameter supply voltage supply current Symbol VPP2 flash mode Conditions memory programming MIN. TYP. MAX. Note When step write time word bytes), Note Number rewrites area CERWR erase write after erase rewrite, Note Unit s/area Times/ Writeback command CERWB tWRW Time
PD70F3038, PD70F3038Y VPP2 PD70F3040, PD70F3040Y VPP2
MHz, MHz, MHz, MHz,
supply voltage Step erase time Total erase time area Writeback time Number writebacks writeback command Number erases writebacks Step write time Total write time word
tERA
VPP2 Note Step erase time Note Note Writeback time Note
word Times/ area
Notes recommended value step erase time value does include prewrite erase verify (writeback) time prior erase. recommended value writeback time Issuing writeback command performs writeback. Therefore, subtract number times command issued from this value number retries. recommended value step write time actual write time word total this value does include internal verify time during after writing. When product written first time, both erase write write only considered rewrite. Example Write, Erase) Product rewrites Product rewrites Remarks operation clock range flash memory programming mode same that during normal operation. When PG-FP3 used, time parameters required write/erase automatically downloading parameter file. Unless otherwise specified, change values. Area 00000H 1FFFFH, area 20000H 3FFFFH, area 040000 05FFFFH PD70F3038, 70F3038Y) Area 00000H 1FFFFH, area 20000H 3FFFFH PD70F3040, 70F3040Y)
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
detail lead
NOTE Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 26.0±0.2 24.0±0.2
24.0±0.2
26.0±0.2
1.25
1.25 0.22±0.05
0.08 (T.P.) 1.0±0.2
0.17 +0.03 -0.07
0.08 0.1±0.05
1.5±0.1
0.25 0.60±0.15
S176GM-50-UEU-1
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
180-PIN PLASTIC FBGA (13x13)
INDEX MARK
ITEM MILLIMETERS 13.00±0.10 13.00±0.10 1.48±0.10 0.35±0.06 1.13 0.80 0.50±0.05 0.08 0.10 0.20 0.90 0.90 P180F1-80-EN2
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
RECOMMENDED SOLDERING CONDITIONS
PD70F3038, 70F3038Y, 70F3040, 70F3040Y should soldered mounted under following recommended conditions. soldering methods conditions other than those recommended below, consult Electronics sales representative. technical information, following website. Semiconductor Device Mount Manual Table 4-1. Surface Mounting Type Soldering Conditions (1/2)
µPD70F3040GM-UEU:
176-pin plastic LQFP (fine pitch)
µPD70F3040YGM-UEU: 176-pin plastic LQFP (fine pitch)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: Twice less, Exposure limit: days hours)
Note
(after that, prebake 125°C
Package peak temperature: 215°C, Time: seconds 200°C higher), Count: Twice less, Exposure limit: days hours)
Note
VP15-103-2
(after that, prebake 125°C
Partial heating
temperature: 300°C max., Time seconds max. (per row)
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating). 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA
Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: Twice less, Exposure limit: days hours) Package peak temperature: 215°C, Time: seconds 200°C higher), Count: Twice less, Exposure limit: days hours)
Note Note
µPD70F3038F1-EN2:
µPD70F3038YF1-EN2: µPD70F3040F1-EN2: µPD70F3040YF1-EN2:
Soldering Method
IR35-107-2
(after that, prebake 125°C
VP15-107-2
(after that, prebake 125°C
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Table 4-1. Surface Mounting Type Soldering Conditions (2/2) µPD70F3040GM-UEU-A: 176-pin plastic LQFP (fine pitch) 176-pin plastic LQFP (fine pitch)
Soldering Conditions Package peak temperature: 260°C, Time: seconds max. 220°C higher), Count: Three times less, Exposure limit: days Partial heating
Note
µPD70F3040YGM-UEU-A:
Soldering Method Infrared reflow
Recommended Condition Symbol IR60-207-3
(after that, prebake 125°C hours)
temperature: 350°C max., Time: seconds max. (per row)
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating). Remark Products with part number lead-free products. µPD70F3038F1-EN2-A: 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA 180-pin plastic FBGA
Soldering Conditions Package peak temperature: 260°C, Time: seconds max. 220°C higher), Count: Three times less, Exposure limit: days
Note
µPD70F3038YF1-EN2-A: µPD70F3040F1-EN2-A: µPD70F3040YF1-EN2-A:
Soldering Method Infrared reflow
Recommended Condition Symbol IR60-203-3
(after that, prebake 125°C hours)
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating). Remark Products with part number lead-free products.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
NOTES CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM INPUT Waveform distortion input noise reflected wave cause malfunction. input CMOS device stays area between (MAX) (MIN) noise, etc., device malfunction. Take care prevent chattering noise from entering device when input level fixed, also transition period when input level passes through area between (MAX) (MIN). HANDLING UNUSED INPUT PINS Unconnected CMOS device inputs cause malfunction. input unconnected, possible that internal input level generated noise, etc., causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected resistor there possibility that will output pin. handling related unused pins must judged separately each device according related specifications governing device. PRECAUTION AGAINST strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work benches floors should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does necessarily define initial status device. Immediately after power source turned devices with reset functions have been initialized. Hence, power-on does guarantee output levels, settings contents registers. device initialized until reset signal received. reset operation must executed immediately after power-on devices with reset functions. POWER ON/OFF SEQUENCE case device that uses different power supplies internal operation external interface, rule, switch external power supply after switching internal power supply. When switching power supply off, rule, switch external power supply then internal power supply. reverse power on/off sequences result application overvoltage internal elements device, causing malfunction degradation internal elements passage abnormal current. correct power on/off sequence must judged separately each device according related specifications governing device. INPUT SIGNAL DURING POWER STATE input signals pull-up power supply while device powered. current injection that results from input such signal pull-up power supply cause malfunction abnormal current that passes device this time cause degradation internal elements. Input signals during power state must judged separately each device according related specifications governing device.
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
Regional Information
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J05.6
Data Sheet U14622EJ2V1DS
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y
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Note
Reference document
Note This document number that Japanese version. documents indicated this publication include preliminary versions. versions marked such. However, preliminary
information this document current August, 2005. information subject change without notice. actual design-in, refer latest publications Electronics data sheets data books, etc., most up-to-date specifications Electronics products. products and/or types available every country. Please check with Electronics sales representative availability additional information. part this document copied reproduced form means without prior written consent Electronics. Electronics assumes responsibility errors that appear this document. Electronics does assume liability infringement patents, copyrights other intellectual property rights third parties arising from Electronics products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Electronics others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Electronics assumes responsibility losses incurred customers third parties arising from these circuits, software information. While Electronics endeavors enhance quality, reliability safety Electronics products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects Electronics products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment anti-failure features. Electronics products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only Electronics products developed based customerdesignated "quality assurance program" specific application. recommended applications Electronics product depend quality grade, indicated below. Customers must check quality grade each Electronics product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade Electronics products "Standard" unless otherwise expressly specified Electronics data sheets data books, etc. customers wish Electronics products applications intended Electronics, they must contact Electronics sales representative advance determine Electronics' willingness support given application. (Note) "NEC Electronics" used this statement means Electronics Corporation also includes majority-owned subsidiaries. "NEC Electronics products" means product developed manufactured Electronics defined above).
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µPD70F3038, 70F3038Y, 70F3040, 70F3040Y V850/SV1 32-BIT SINGLE-CH

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