µPD78P078Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78P078Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78P078Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P078Y member µPD78078Y Subseries 78K/0 Series, which on-chip mask µPD78078Y replaced with one-time PROM EPROM. Because this device programmed users, ideally suited system evaluation, small-lot multipledevice production, early development time-to-market. µPD78P078Y also used system evaluation µPD78075BY Subseries device. Caution specifications µPD78075BY Subseries same those µPD78078Y Subseries. Therefore, µPD78P078Y used evaluate µPD78075BY Subseries product, refer µPD78075B, 78075BY Subseries User's Manual (U12560E). details functions described user's manuals. sure read following manuals before designing. µPD78078, 78078Y Subseries User's Manual U10641E 78K/0 Series User's Manual: Instructions U12326E
FEATURES
Pin-compatible with mask version (except pin) Internal PROM: Kbytes
Note
Internal high-speed RAM: 1024 bytes Internal expansion RAM: 1024 bytes Internal buffer RAM: bytes Operable same supply voltage mask version (VDD Corresponding QTOPMicrocontrollers
Note
Notes internal PROM capacity changed setting memory size switching register (IMS). internal expansion capacity changed internal expansion size switching register (IXS). Remarks Refer DIFFERENCES BETWEEN µPD78P078Y MASK VERSIONS differences between PROM version mask version. QTOP microcontroller general term microcontrollers which incorporate one-time PROM totally supported NEC's programming service (from programming marking, screening verification).
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Document U10606EJ3V1DS00 (3rd edition) Date Published August 2005 Printed Japan
mark
shows major revised points.
1996
µPD78P078Y
ORDERING INFORMATION
Part Number Package 100-pin plastic resin thickness: Internal One-Time PROM
µPD78P078YGF-3BA µPD78P078YGF-3BA-A µPD78P078YGC-8EU
100-pin plastic resin thickness: 100-pin plastic LQFP (fine pitch) resin thickness: 1.40
One-Time PROM
One-Time PROM
Remark Products that have part numbers suffixed "-A" lead-free products.
Data Sheet U10606EJ3V1DS
µPD78P078Y
78K/0 Series Development following shows 78K/0 Series products development. Subseries names shown inside frames.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
Inverter control
PD78075BY µPD78078Y µPD78070AY µPD780018AY µPD780058Y Note µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
noise reduction version PD78078 timer added PD78054 external interface function enhanced ROM-less versions PD78078 Serial PD78078 enhanced only selected functions provided Serial PD78054 enhanced. noise reduction version noise reduction version PD78054 UART converter were added µPD78014 enhanced converter PD780024 enhanced Serial PD78018F enhanced. noise reduction version noise reduction version µPD78018F Low-voltage (1.8 operation versions PD78014 with choice several capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operation voltage (1.8
64-pin 64-pin
µPD780964 µPD780924
FIPdrive
converter µPD780924 enhanced On-chip inverter control circuit UART. noise reduction version
78K/0 Series
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
PD78044F were enhanced. Display output total: PD78044H were enhanced. Display output total: N-ch open-drain added µPD78044F. Display output total: Basic subseries driving FIP. Display output total:
drive 100-pin 100-pin 100-pin
µPD780308 µPD78064B µPD78064
IEBussupported
µPD780308Y µPD78064Y
µPD78064 enhanced. were expanded noise reduction version PD78064 Basic subseries driving LCDs, On-chip UART
80-pin 80-pin
µPD78098B µPD78098
noise reduction version PD78098 IEBus controller added PD78054
Meter control 80-pin
µPD780973
On-chip controller/driver driving automobile meters
64-pin
µPD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning
Data Sheet U10606EJ3V1DS
µPD78P078Y
following table shows differences among subseries functions.
Function Part Number Control Capacity 8-Bit 10-Bit 8-Bit 8-Bit 16-Bit Watch Timer Serial Interface MIN. External Value Expansion Available
µPD78075B µPD78078 µPD78070A µPD780058
(UART:
(time division UART: (UART:
µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018H µPD78014 µPD780001 µPD78002 µPD78083
Inverter control
(UART: time division 3-wire:
Note (time division UART: (UART: (UART: (UART: Available Available
µPD780964 µPD780924 µPD780228 µPD78044H µPD78044F
drive µPD780208
drive
µPD780308
µPD78064B µPD78064
IEBus µPD78098B supported µPD78098 Meter control
(UART:
Available Available
µPD780973
(UART:
µPD78P0914
Note 10-bit timer: channel
Data Sheet U10606EJ3V1DS
µPD78P078Y
FUNCTION DESCRIPTION
Item Internal memory PROM: Kbytes High-speed RAM: 1024 bytes Expansion RAM: 1024 bytes Buffer RAM: bytes Memory space General register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc. ports Total CMOS input CMOS input/output 8-bit resolution channels 8-bit resolution channels 3-wire serial I/O/2-wire serial I/O/I mode selectable: channel
Note Note
Function
Kbytes bits registers bits registers banks) Minimum instruction execution time variable function integrated. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 MHz) 32.768 kHz)
N-ch open-drain input/output converter converter Serial interface
3-wire serial mode (with max. 32-byte on-chip automatic transmitting/ receiving function): channel 3-wire serial I/O/UART mode selectable: channel Timer 16-bit timer/event counter: channel 8-bit timer/event counter: channels Watch timer: channel Watchdog timer: channel Timer output Clock output pins (14-bit output enable: pin, 8-bit output enable: pins) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, with main system clock) 32.768 32.768 with subsystem clock) Buzzer output kHz, kHz, with main system clock)
Notes internal PROM capacity changed using memory size switching register (IMS). internal expansion capacity changed using internal expansion size switching register (IXS).
Data Sheet U10606EJ3V1DS
µPD78P078Y
Item Vectored interrupt sources Maskable Non-maskable Software Test input Supply voltage Package Internal: External: Internal: Internal: External:
Function
100-pin plastic resin thickness: 100-pin plastic LQFP (fine pitch) resin thickness: 1.40
Data Sheet U10606EJ3V1DS
µPD78P078Y
CONFIGURATION (TOP VIEW)
Normal operating mode 100-pin plastic resin thickness:
P101/TI6/TO6 P100/TI5/TO5 P67/ASTB
P36/BUZ
P32/TO2
P31/TO1
P30/TO0
P35/PCL
P34/TI2
P33/TI1
P103
P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDD AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5
P102
P66/WAIT P65/WR P64/RD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3 P82/A2
P71/SO2/TxD
P70/SI2/RxD
P17/ANI7 AVSS
AVREF1
P72/SCK2/ASCK
P16/ANI6
P130/ANO0
P131/ANO1
P26/SO0/SB1
P21/SO1
P22/SCK1
P23/STB P24/BUSY
P25/SI0/SB0
P27/SCK0
P20/SI1
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
P80/A0
P81/A1
Data Sheet U10606EJ3V1DS
µPD78P078Y
100-pin plastic LQFP (fine pitch) resin thickness: 1.40
P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDD P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT1/P07 P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P80/A0 P81/A1 P82/A2 P83/A3 P84/A4
P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB P66/WAIT P65/WR
P54/A12 P55/A13 P56/A14 P57/A15
P85/A5 P86/A6 P87/A7 P40/AD0
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11
Data Sheet U10606EJ3V1DS
P64/RD
µPD78P078Y
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0, AVREF1 AVSS BUSY INTP0 INTP6 P100 P103 P120 P127 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Interrupt from Peripherals Port Port Port Port Port Port Port Port Port Port Port Port P130, P131 RESET RTP0 RTP7 SB0, SCK0 SCK2 SDA0, SDA1 TI00, TI01 TI1, TI2, TI5, WAIT XT1, Port Programmable Clock Read Strobe Reset Real-Time Output Port Receive Data Transmit Data Serial Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
TO2, TO5, Timer Output
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM programming mode 100-pin plastic resin thickness:
Open Open
RESET
Cautions (L): VSS: Open:
Individually connect pull-down resistor. Connect GND. connection.
RESET: level.
Data Sheet U10606EJ3V1DS
µPD78P078Y
100-pin plastic LQFP (fine pitch) resin thickness: 1.40
RESET Open Open
Cautions (L): VSS: Open:
Individually connect pull-down resistor. Connect GND. connection. RESET Reset Power Supply Programming Power Supply Ground
RESET: level.
Address Chip Enable Data Output Enable Program
Data Sheet U10606EJ3V1DS
µPD78P078Y
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 PORT0
16-bit TIMER/ EVENT COUNTER
PORT1
8-bit TIMER/EVENT COUNTER
PORT2
8-bit TIMER/EVENT COUNTER
PORT3
TI5/TO5/P100
8-bit TIMER/EVENT COUNTER
PORT4
TI6/TO6/P101
8-bit TIMER/EVENT COUNTER
PORT5 PORT6
WATCHDOG TIMER
78K/0 CORE
PROM Kbytes)
PORT7
WATCH TIMER
PORT8
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00 INTP6/P06
SERIAL INTERFACE
PORT9
PORT10
SERIAL INTERFACE (2048 Bytes)
P100 P103
PORT12
P120 P127
SERIAL INTERFACE
PORT13
REAL-TIME OUTPUT PORT
P130, P131 RTP0/P12 RTP7/P127 AD0/P40 AD7/P47 A0/P80 A7/P87 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
CONVERTER
CONVERTER
EXTERNAL ACCESS
INTERRUPT CONTROL
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL
XT1/P07
PCL/P35
CLOCK OUTPUT CONTROL
Data Sheet U10606EJ3V1DS
µPD78P078Y
CONTENTS
DIFFERENCES BETWEEN µPD78P078Y MASK VERSIONS FUNCTIONS
Pins Normal Operating Mode.15 Pins PROM Programming Mode.19 Input/Output Circuits Recommended Connection Unused Pins.20
MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS). PROM PROGRAMMING
Operating Modes.26 PROM Write Procedure PROM Read Procedure
ONE-TIME PROM VERSION SCREENING ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUES). PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U10606EJ3V1DS
µPD78P078Y
DIFFERENCES BETWEEN µPD78P078Y MASK VERSIONS
µPD78P078Y single-chip microcontroller with on-chip one-time PROM with on-chip EPROM which program write, erasure rewrite capability. possible make functions, except PROM specification mask option pins, same those mask versions setting memory size switching register (IMS) internal expanded size switching register (IXS). Differences between PROM version (µPD78P078Y) mask versions (µPD78074BY, 78075BY, 78076Y, 78078Y) shown Table 1-1. Table 1-1. Differences between µPD78P078 Mask Versions
Parameter Internal type Internal capacity
µPD78P078
One-time PROM/EPROM Kbytes
Mask Versions Mask
µPD78074BY Kbytes µPD78075BY Kbytes µPD78076Y Kbytes µPD78078Y Kbytes
Internal expanded capacity
1024 bytes
µPD78074BY none µPD78075BY none µPD78076Y 1024 bytes µPD78078Y 1024 bytes
Internal capacity selection with memory size switching register (IMS) Internal expanded capacity selection with internal expanded size switching register (IXS) On-chip pull-up resistor mask option pins Electrical specifications
Possible
Note
possible
Possible
Note
possible
Refer Data Sheet each version.
Notes internal PROM becomes Kbytes internal high-speed becomes 1024 bytes RESET input. internal expansion becomes 1024 bytes RESET input. Caution There differences noise immunity noise radiation between PROM mask versions. When pre-producing application with PROM version then mass-producing with mask version, sure conduct sufficient evaluations using consumer samples (not engineering samples) mask version.
Data Sheet U10606EJ3V1DS
µPD78P078Y
FUNCTIONS
Pins Normal Operating Mode Port pins (1/3)
Name
Note
Input/Output Input Input/output Port 8-it input/output port
Function Input only Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software.
After Reset Input
Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6
Input Input/output Port 8-bit input/output port
Input only
Input Input
ANI0 ANI7
Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software Input/output Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Input Input/output Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software.
Note
Input SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Notes When P07/XT1 used input port, processor clock control register (PCC) (FRC) sure feedback resistor subsystem clock oscillator). When P10/ANI0 P17/ANI7 pins used analog inputs converter, pull-up resistor automatically disabled.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Port pins (2/3)
Name Input/Output Input/output Port 8-bit input/output port Input/output specifiable 8-bit units. When used input port, possible connect on-chip pull-up resistor software. test input flag (KRIF) falling edge detection. Input/output Port 8-bit input/output port possible directly drive LEDs. Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Input/output Input/output Port 3-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Input/output Port 7-bit input/output port Input/output specifiable bit-wise. N-ch open-drain input/output port possible directly drive LEDs. When used input port, possible connect onchip pull-up resistor software Input Input SO2/TxD SCK2/ASCK2 Input When used input port, possible connect onchip pull-up resistor software. Input WAIT ASTB SI2/RxD Input/output Port 8-bit input/output port Input/output specifiable bit-wise. N-ch open-drain input/output port possible directly drive LEDs. Input Input Function After Reset Input Alternate Function ANI0 ANI7
Data Sheet U10606EJ3V1DS
µPD78P078Y
Port pins (3/3)
Name P100 P101 P102, P103 P120 P127 Input/output Input/Output Input/output Port 4-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. P130 P131 Input/output Port 2-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect on-chip pull-up resistor software. Input ANO0, ANO1 Input TI6/TO6 RTP0 RTP7 Function After Reset Input Alternate Function TI5/TO5
Data Sheet U10606EJ3V1DS
µPD78P078Y
Non-port pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01 RTP0 RTP7 Output Output Output Input/Output Output Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial data input. External count clock input 16-bit timer (TM0). Capture trigger signal input capture register (CR00). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2). External count clock input 8-bit timer (TM5). External count clock input 8-bit timer (TM6). 16-bit timer (TM0) output (also used 14-bit output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. 8-bit timer (TM5) output (also used 8-bit output). 8-bit timer (TM6) output (also used 8-bit output). Clock output (for main system clock, subsystem clock trimming) Buzzer output Real-time output port which data output synchronization with trigger. Low-order address/data external memory expansion. Input Input Input Input Input Input Input Input Input Input Input Input/Output Serial interface serial data input/output. Input Input/Output Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Serial interface serial data input. Input Input/Output Input Function External interrupt request input which active edge (rising edge, falling edge, both rising falling edges) specified. After Reset Alternate Function Input P00/TI00 P01/TI01 P25/SB0/SDA0 P70/RxD P26/SB1/SDA1 P71/TxD P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P72/ASCK P27/SCK0 P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P100/TO5 P101/TO6 P100/TI5 P101/TI6 P120 P127
Data Sheet U10606EJ3V1DS
µPD78P078Y
Non-port pins (2/2)
Name WAIT ASTB ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET Input Output Input Output Input Input Input Input Input Positive power supply High-voltage applied during program write/verification. Connected directly normal operating mode. Ground potential. Subsystem clock oscillation crystal connection. Input/Output Output Output Output Function Low-order address external memory expansion. High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output. Wait insertion external memory access. Strobe output which latches address data output ports access external memory converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply. Connected VDD. converters ground potential. Connected VSS. System reset input. Main system clock oscillation crystal connection. Input Input Input P130, P131 After Reset Alternate Function Input Input Input Input Input Input
Pins PROM Programming Mode
Name RESET Input/Output Input PROM programming mode setting When +12.5 applied level signal applied RESET pin, this chip PROM programming mode. Input Input Input/output Input Input Input PROM programming mode setting high-voltage applied during program write/verification. Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programming mode. Positive power supply Ground potential Function
Data Sheet U10606EJ3V1DS
µPD78P078Y
Input/Output Circuits Recommended Connection Unused Pins Types input/output circuits pins recommended connection unused pins shown Table 2-1. configuration each type input/output circuit, Figure 2-1. Table 2-1. Type Input/Output Circuit Each (1/2)
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB 13-D Input/Output Input/Output Input/Output Input/Output Independently connect resistor. Independently connect resistor. Independently connect resistor. Independently connect resistor 10-A Input Input/Output Connect VDD. Independently connect resistor Input/Output Circuit Type Input Input/Output Connect VSS. Independently connect resistor. Input/Output Recommended Connection Unused Pins
Data Sheet U10606EJ3V1DS
µPD78P078Y
Table 2-1. Type Input/Output Circuit Each (2/2)
Name P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/A0 P87/A7 P100/TI5/TO5 P101/TI6/TO6 P102, P103 P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 RESET AVREF0 AVREF1 AVDD AVSS Connect VSS. Connect directly VSS. 12-A Input/Output Input Independently connect resistor. Leave open. Connect VSS. Connect VDD. Input/Output Circuit Type 13-D Input/Output Input/Output Independently connect resistor. Independently connect resistor. Input/Output Independently connect resistor. Input/Output Recommended Connection Unused Pins
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure 2-1. List Input/Output Circuits (1/2)
Type
Type
pullup enable data P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch
Type pullup enable data
Type 10-A
P-ch
pullup enable data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch
output disable
N-ch
input enable Type Type pullup enable data P-ch IN/OUT IN/OUT output disable N-ch output disable P-ch Comparator N-ch VREF (threshold voltage) input enable N-ch
pullup enable data P-ch
P-ch
P-ch
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure 2-1. List Input/Output Circuits (2/2)
Type 12-A pullup enable data
Type feedback cut-off P-ch
P-ch
P-ch IN/OUT
output disable input enable
N-ch
P-ch Analog Output Voltage N-ch
Type 13-D
IN/OUT data output disable N-ch
P-ch
Medium Voltage Input Buffer
Data Sheet U10606EJ3V1DS
µPD78P078Y
MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this memory size switching register (IMS), possible same memory mapping that mask versions with different internal memory (ROM). with 8-bit memory manipulation instruction. RESET input sets CFH. Figure 3-1. Memory Size Switching Register Format
Symbol RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 Address FFF0H After Reset
ROM3 ROM2 ROM1 ROM0
Selection internal Capacity Kbytes Kbytes Kbytes KbytesNote Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity
1024 bytes Setting prohibited
Other than above
Note When external device expansion function used, internal capacity should Kbytes less. Table shows setting values which make memory mapping same that mask version. Table 3-1. Memory Size Switching Register Setting Values
Target Mask Versions Setting Value
µPD78074BY µPD78075BY µPD78076Y µPD78078Y
Data Sheet U10606EJ3V1DS
µPD78P078Y
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS)
This register used internal expansion capacity software. setting this internal expansion size switching register (IXS), possible same memory mapping that mask versions with different internal expansion RAM. with 8-bit memory manipulation instruction. RESET input sets 0AH. Figure 4-1. Internal Expansion Size Switching Register Format
Symbol IXRAM3 IXRAM2 IXRAM1 IXRAM0 Address FFF4H After Reset
IXRAM3
IXRAM2
IXRAM1
IXRAM0
Internal expansion capacity selection bytes 1024 bytes Setting prohibited
Other than above
Table shows setting values which make memory mapping same that mask versions. Table 4-1. Internal Expansion Size Switching Register Setting Values
Target Mask Versions Setting Value
Note
µPD78074BY µPD78075BY µPD78076Y µPD78078Y
Note program µPD78P078 which "MOV IXS, #0CH" written executed µPD78074BY µPD78075BY, operations affected.
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM PROGRAMMING
µPD78P078Y on-chip 60-Kbyte PROM program memory. programming, PROM programming mode with RESET pins. CONFIGURATIONS PROM programming mode." Caution Programs must written addresses 0000H EFFFH (The last address EFFFH must specified). They cannot written PROM programmer which cannot specify write address. Operating Modes When +12.5 applied low-level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM. Table 5-1. Operating Modes PROM Programming
Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET
connection unused pins, refer "PIN
Data Sheet U10606EJ3V1DS
µPD78P078Y
Read mode Read mode setting Output disable mode Data output becomes high-impedance placed output disable mode setting Therefore, multiple µPD78P078Ys connected data bus, data read from device controlling pin. Standby mode Standby mode setting this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode setting beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying 0.1-ms program pulse (active low) with Then, program verification performed setting programming performed one-time program pulse, times write verification operations should executed repeatedly. Byte write mode Byte write executed when 0.1-ms program pulse (active low) applied with Then, program verification performed setting programming performed one-time program pulse, times write verification operations should executed repeatedly. Program verify mode Program verify mode setting this mode, check write operation performed correctly after write. Program inhibit mode Program inhibit mode used when pin, pins multiple µPD78P078Ys connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 0.1-ms program pulse
Verify bytes Pass Address
Fail
Pass
Verify bytes Pass Write
Fail
Defective product
Start address Program last address
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure 5-2. Page Program Mode Timing
Page Data Latch Page Program Program Verify
Data Input Data Output
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure 5-3. Byte Program Mode Flow Chart
Start Address 12.5
X=X+1 0.1-ms program pulse Address Address Fail Verify Pass Address
Pass
Verify bytes Pass Write
Fail
Defective product
Start address Program last address
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure 5-4. Byte Program Mode Timing
Program Program Verify
Data Input
Data Output
Cautions should applied before removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Read Procedure contents PROM readable external data according read procedure shown below. RESET level, supply pin, connect other unused pins shown "PIN CONFIGURATIONS PROM programming mode". Supply pins. Input address read data into pins. Read mode Output data pins. timings above steps shown Figure 5-5. Figure 5-5. PROM Read Timings
Address Input
(Input)
(Input)
Hi-Z
Data Output
Hi-Z
Data Sheet U10606EJ3V1DS
µPD78P078Y
ONE-TIME PROM VERSION SCREENING
one-time PROM version cannot tested completely Electronics before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing hightemperature storage under condition below.
Storage Temperature 125°C Storage Time hours
Electronics offers additional services from one-time PROM writing marking, screening, verify products designated "QTOP Microcontroller". details, contact Electronics sales representative.
Data Sheet U10606EJ3V1DS
µPD78P078Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131, XT2, RESET Output voltage Analog input voltage Output current, high Total P37, P56, P57, P67, P96, P100 P103, P120 P127 Total P06, P17, P27, P47, P55, P72, P87, P130, P131 Output current,
Note
Test Conditions
Ratings -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3
Unit
P63,
N-ch open-drain PROM programming mode
-0.3 -0.3 +13.5 -0.3
Analog input pins
AVSS AVREF0
Peak value r.m.s. value
+150
Total
Peak value r.m.s. value
Total P56, P57,
Peak value r.m.s. value
Total P37, P67, P96, P100 P103, P120 P127 Total P27, P47, Total P06, P17, P72, P130, P131 Operating ambient temperature Storage temperature Tstg
Peak value r.m.s. value Peak value r.m.s. value Peak value r.m.s. value
Note r.m.s. (root mean square) value should calculated follows: [r.m.s. value] [Peak value] Duty Caution Exposure Absolute Maximum Ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under Characteristics. Remark Unless otherwise specified, alternate-function characteristics same port characteristics.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Capacitance 25°C,
Parameter Input capacitance capacitance Symbol Test Conditions MHz, Unmeasured pins returned MHz, Unmeasured pins returned P07, P17, P27, P37, P47, P57, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131 P63, MIN. TYP. MAX. Unit
Remark Unless otherwise specified, dual-function characteristics same port characteristics. Main System Clock Oscillator Characteristics +85°C,
Resonator Recommended Circuit Ceramic resonator
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency (fX)
Note
Oscillation voltage range
After came MIN. oscillation voltage range
Oscillation stabilization time
Note
Crystal resonator
Oscillation frequency (fX)
Note
Oscillation stabilization time
Note
External clock
input frequency (fX)
Note
PD74HCU04
input high- lowlevel widths (tXH, tXL)
Notes Only oscillator characteristics shown. Characteristics.
instruction execution time, refer
Time required oscillation stabilize after reset STOP mode been released. Cautions When using oscillation circuit main system clock, wire portion enclosed broken lines figures follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. connect power source pattern through which high current flows. extract signals from oscillation circuit. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Recommended Circuit Crystal resonator
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency (fXT)
Note
32.768
Oscillation stabilization time
Note
External clock
input frequency (fXT)
Note
µPD74HCU04
input high-, low-level widths (tXTH, tXTL)
Notes Only oscillator characteristics shown. Characteristics.
instruction execution time, refer
Time required oscillation stabilize after reaches minimum value oscillation voltage range. Cautions When using oscillation circuit subsystem clock, wire portion enclosed broken lines figures follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. connect power source pattern through which high current flows. extract signals from oscillation circuit. amplification factor subsystem clock oscillator designed reduce current consumption therefore, subsystem clock oscillator influenced noise more easily than main system clock oscillator. When using subsystem clock, therefore, exercise utmost care wiring circuit.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Recommended Oscillator Constant Main System Clock: Ceramic Resonator +85°C)
Manufacturer Part number Frequency Recommended circuit constant (pF) CCR1000K2 CCR2.0MC3 1.00 2.00 On-chip (pF) On-chip Oscillation voltage range MIN. MAX. On-chip capacitor On-chip capacitor surface mount type CCR4.0MC3 4.00 On-chip On-chip On-chip capacitor surface mount type FCR4.0MC5 4.00 On-chip On-chip On-chip capacitor insertion type Murata Mfg. Corporation CSB1000J CSA2.00MG040 CST2.00MG040 1.00 2.00 2.00 On-chip On-chip Insertion type Insertion type On-chip capacitor insertion type CSA4.00MG CST4.00MGW 4.00 4.00 On-chip On-chip Insertion type On-chip capacitor insertion type CSA4.00MGU CST4.00MGWU 4.00 4.00 On-chip On-chip Insertion type On-chip capacitor insertion type Remarks
Main System Clock Ceramic Resonator +80°C)
Manufacturer Part number Frequency Recommended circuit constant (pF) Kyocera Corporation KFR-1000F PBR-1000Y KBR-2.0MS KBR-4.0MKC 1.00 1.00 2.00 4.00 On-chip (pF) On-chip Oscillation voltage range MIN. MAX. Insertion type Surface mount type Insertion type On-chip capacitor insertion type KBR-4.0MSB PBRC4.00B 4.00 4.00 On-chip On-chip Insertion type On-chip capacitor surface mount type PBRC4.00A 4.00 Surface mount type Remarks
Caution oscillator constant oscillation voltage range indicate conditions stable oscillation. oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P87, P96, P102, P103, P120 P127, P130, P131 VIH2 P06, P20, P22, P27, P33, P34, P70, P72, P100, P101, RESET VIH3 P63, (N-ch open-drain) VIH4 0.7VDD 0.8VDD VDD-0.5 VDD-0.2 VIH5 XT1/P07, Note Input voltage, VIL1 P17, P21, P23, P32, P37, P47, P57, P67, P71, P87, P96, P102, P103, P120 P127, P130, P131 VIL2 P06, P20, P22, P27, P33, P34, P70, P72, P100, P101, RESET VIL3 P63, (N-ch open-drain) VIL4 VIL5 XT1/P07, Note Output voltage, high -100 VDD-1.0 VDD-0.5 0.3VDD 0.2VDD 0.1VDD 0.2VDD 0.1VDD 0.1VDD 0.15VDD 0.2VDD 0.2VDD 0.8VDD 0.9VDD 0.9VDD 0.3VDD 0.85VDD 0.8VDD 0.8VDD MIN. 0.7VDD TYP. MAX. Unit
Note When used P07, reverse phase should input using inverter. Remark Unless otherwise specified, alternate-function characteristics same port characteristics.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Characteristics +85°C,
Parameter Output voltage, Symbol VOL1 P57, P63, P06, P17, P27, P37, P47, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 open-drain, pulled VOL3 Input leakage current, high ILIH1 P06, P17, P27, P37, P47, P57, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131, RESET ILIH2 ILIH3 Input leakage current, ILIL1 XT1/P07, P63, P06, P17, P27, P37, P47, P57, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131, RESET ILIL2 ILIL3 Output leakage current, high ILOH Output leakage current, ILOL VOUT VOUT XT1/P07, P63,
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
0.2VDD
Note value -200 (MAX.) only clock cycles wait) when read-out instruction executed port (P6), port mode register (PM6), port (P9) port mode register (PM9). cases other than clock cycles read-out instruction execution, value (MAX.). Remark Unless otherwise specified, alternate-function characteristics same port characteristics.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Characteristics +85°C,
Parameter Software pull-up resistor
Note
Symbol
Test Conditions P17, P27, P37, P47, P57, P67, P72, P87, P96, P100 P103, P120 P127, P130, P131
MIN.
TYP.
MAX.
Unit
Supply current
Note
IDD1
5.0-MHz crystal oscillation operating mode (fXX MHz)
Note
±10%
Note
0.45 0.65 0.05 0.05
16.2 1.35 28.5 1.95 12.5
Note
Note
5.0-MHz crystal oscillation operating mode (fXX MHz) IDD2
Note
Note
Note
crystal oscillation HALT mode (fXX MHz)
Note
crystal oscillation HALT mode (fXX MHz) IDD3
Note
32.768-kHz crystal oscillation operating mode
Note
IDD4
32.768-kHz crystal oscillation HALT mode
Note
IDD5
STOP mode Feedback resistor used
IDD6
STOP mode Feedback resistor used
Notes Software pull-up resistor used only within range Supply current flowing pin. excludes current flowing A/D, converters on-chip pull-up resistors. fX/2 operation (when oscillation mode selection register (OSMS) 00H). operation (when OSMS 01H). When main system clock stopped. High-speed mode operation (when processor clock control register (PCC) 00H). Low-speed mode operation (when 04H). Remarks Unless otherwise specified, alternate-function characteristics same port characteristics. fXX: Main system clock frequency fX/2) Main system clock oscillation frequency
Data Sheet U10606EJ3V1DS
µPD78P078Y
Characteristics Basic Operation +85°C,
Parameter Cycle time (minimum instruction execution time) Symbol Operating main system clock
Note
Test Conditions fX/2
Note
MIN.
TYP.
MAX.
Unit
2/fsam+0.1 2/fsam+0.2 2/fsam+0.5
Note
Operating subsystem clock T100 input high-/ lowlevel widths tTIH00, tTIL00
Note
Note
T101 input high-/ lowlevel widths TI1, TI2, TI5, input frequency TI1, TI2, TI5, input high-/ low-level widths Interrupt request input high-/low-level widths
tTIH01, tTIL01 tTI1
tTIH1, tTIL1 tINTH, tINTL
Note
INTP0
2/fsam+0.1 2/fsam+0.2 2/fsam+0.5
Note
Note
INTP1 INTP6, RESET low-level width tRSL
Notes When oscillation mode selection register (OSMS) 00H. When OSMS 01H. fsam selected fXX/2N, fXX/32, fXX/64 fXX/128 bits (SCS0, SCS1) sampling clock selection register (SCS). Remark fXX: Main system clock frequency fX/2) Main system clock oscillation frequency
Data Sheet U10606EJ3V1DS
µPD78P078Y
(Main System Clock fX/2 Operation) (Main System Clock Operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
Data Sheet U10606EJ3V1DS
µPD78P078Y
Read/Write Operation When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level with Address setup time Address hold time Address Data input time Symbol tASTH tADS tADH tADD1 tADD2 Data input time tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time tRDWT1 tRDWT2 WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time write data output time address hold time WAIT delay time WAIT delay time tRDWD tWRWD tWRADH tWTRD tWTWR 0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY tRDADH 0.85tCY 1.15tCY tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST load resistance (1.15 (2.85 (2.85 0.85tCY 0.85tCY 1.15tCY (2.85 0.85tCY 2tCY 2tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 (2.85 MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Except When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level with Address setup time Address hold time Address Data input time Symbol tASTH tADS tADH tADD1 tADD2 Data input time tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time tRDWT1 tRDWT2 WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time write data output time address hold time WAIT delay time WAIT delay time tRDWD tWRWD tWRADH tWTRD tWTWR 0.4tCY 0.6tCY 0.6tCY 2.6tCY +180 2.6tCY tRDADH tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST load resistance (2.4 (2.4 0.4tCY 1.4tCY (1.4 (2.4 2tCY 2tCY Test Conditions 0.4tCY (1.4 (2.4 MIN. MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Serial Interface +85°C, Serial Interface Channel 3-wire serial mode (SCK0 .internal clock output)
Symbol tKCY1 Test Conditions MIN. 1600 3200 4800 SCK0 high-/low-level width tKH1, tKL1 setup time SCK0 tSIK1 tKCY1/2-50 tKCY1/2-100 hold time (from SCK0 SCK0 output delay time tKSI1
Note
Parameter SCK0 cycle time
TYP.
MAX.
Unit
tKSO1
Note output line load capacitance. (ii) 3-wire serial mode (SCK0 .external clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 4800 SCK0 high-/low-level width tKH2, tKL2 1600 2400 setup time SCK0 hold time (from SCK0 SCK0 output delay time SCK0 rise, fall time tR2, When using external device expansion function When using external device expansion function 1000 tSIK2 tKSI2
Note
TYP.
MAX.
Unit
tKSO2
Note output line load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
(iii) 2-wire serial mode (SCK0 .internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions MIN. 1600 3200 4800 SCK0 high-level width tKH3 tKCY3/2-160 tKCY3/2-190 SCK0 low-level width tKL3 tKCY3/2-50 tKCY3/2-100 SB0, setup time SCK0 tSIK3 SB0, hold time (from SCK0 SCK0 SB0, output delay time tKSI3 TYP. MAX. Unit
tKSO3
Note SCK0, SB0, output line load resistance load capacitance. (iv) 2-wire serial mode (SCK0 .external clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions MIN. 1600 3200 4800 SCK0 high-level width tKH4 1300 2100 SCK0 low-level width tKL4 1600 2400 SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time SCK0 rise, fall time tR4, tSIK4 tKSI4
Note
TYP.
MAX.
Unit
tKCY4/2
tKSO4
When using external device expansion function When using external device expansion function
1000
Note SB0, output line load resistance load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
mode (SCL .internal clock output)
Parameter cycle time Symbol tKCY5
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
high-level width
tKH5
tKCY5/2-160 tKCY5/2-190
low-level width
tKL5
tKCY5/2-50 tKCY5/2-100
SDA0, SDA1 setup time
tKSI5
SDA0, SDA1 hold time (from SDA0, SDA1 output delay time
tKSI5
tKSO5
SDA0, SDA1 SDA0, SDA1 SCA0, SDA1
tKSB
tSBK
SDA0, SDA1 high level width
tSBH
Note SCL, SDA0, SDA1 output line load resistance load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
(vi) mode (SCL external clock input)
Parameter cycle time high-/low-level width Symbol tKCY6 tKH6, tKL6 SDA0, SDA1 setup time SDA0, SDA1 hold time (from SDA0, SDA1 output delay time tSIK6 Test Conditions MIN. 1000 tKSI6
Note
TYP.
MAX.
Unit
tKSO6
SDA0, SDA1 SDA0, SDA1 SDA0, SDA1
tKSB
tSBK
SDA0, SDA1 high-level width
tSBH
rise, fall time
tR6,
When using external device expansion function When using external device expansion function
1000
Note SDA0, SDA1 output line load resistance load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Serial Interface Channel 3-wire serial mode (SCK1 .internal clock output)
Symbol tKCY7 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH7, tKL7 setup time SCK1 tSIK7 tKCY7/2-50 tKCY7/2-100 hold time (from SCK1 SCK1 output delay time tKS7
Note
Parameter SCK1 cycle time
TYP.
MAX.
Unit
tKSO7
Note output line load capacitance. (ii) 3-wire serial mode (SCK1 .external clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH8, tKL8 1600 2400 setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time tR8, When using external device expansion function When using external device expansion function 1000 tSIK8 tKSI8
Note
TYP.
MAX.
Unit
tKSO8
Note output line load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
(iii) 3-wire serial mode with automatic transmission/reception function (SCK1 .internal clock output)
Parameter SCK1 cycle time Symbol tKCY97 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH9, tKL9 setup time SCK1 tSIK9 tKCY9/2-50 tKCY9/2-100 hold time (from SCK1 SCK1 output delay time SCK1 Strobe signal high-level width tSBD tSBW tKCY9/2-100 tKCY9/2-30 tKCY9/2-60 tKCY9/2-90 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH Busy inactive SCK1 tSPS 2tKCY9 tBYS tKCY9/2+100 tKCY9/2+30 tKCY9/2+60 tKCY9/2+90 tKS9
Note
TYP.
MAX.
Unit
tKSO9
Note output line load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
(iv) 3-wire serial mode with automatic transmission/reception function (SCK1 .external clock output)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH10, tKL10 1600 2400 setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time tR10, tF10 When using external device expansion function When using external device expansion function 1000 tSIK10 tKSI10
Note
TYP.
MAX.
Unit
tKSO10
Note output line load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Serial Interface Channel 3-wire serial mode (SCK2 .internal clock output)
Symbol tKCY11 Test Conditions MIN. 1600 3200 4800 SCK2 high-/low-level width tKH11, tKL11 setup time SCK2 tSIK11 tKCY11/2-50 tKCY11/2-100 hold time (from SCK2 SCK2 output delay time tKSI11
Note
Parameter SCK2 cycle time
TYP.
MAX.
Unit
tKSO11
Note output line load capacitance. (ii) 3-wire serial mode (SCK2 .external clock input)
Parameter SCK2 cycle time Symbol tKCY12 Test Conditions MIN. 1600 3200 4800 SCK2 high-/low-level width tKH12, tKL12 1600 2400 setup time SCK2 hold time (from SCK2 SCK2 output delay time SCK2 rise, fall time tR12, tF12 When using external device expansion function tSIK12 tKSI12
Note
TYP.
MAX.
Unit
tKSO12
1000
Note output line load capacitance.
Data Sheet U10606EJ3V1DS
µPD78P078Y
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rage Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 9766 Unit
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY13 Test Conditions MIN. 1600 3200 4800 ASCK high-/low-level width tKH13, tKL13 1600 2400 Transfer rate 39063 19531 9766 6510 ASCK rise, fall time tR13, tF13 When using external device expansion function 1000 TYP. MAX. Unit
Data Sheet U10606EJ3V1DS
µPD78P078Y
Timing Test point (Excluding Input)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test Points
Clock Timing
1/fx VIH4 (MIN.) VIL4 (MAX.)
Input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
Input
Timing
tTIL00 ,tTIL01 tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2, TI5,
Data Sheet U10606EJ3V1DS
µPD78P078Y
Read/Write Operation External fetch wait):
High-order (low-order) 8-bit address tADD1 Hi-Z
tADS ASTB
Low-order 8-bit address
Instruction code
tASTH
tADH
tRDD1
tRDADH tRDAST
tASTRD tRDL1 tRDH
Remark effective only separate mode. External fetch (wait insertion):
High-order (low-order) 8-bit address tADD1 tADS tASTH ASTB
Low-order 8-bit address
Hi-Z tRDD1
Instruction code
tADH
tRDADH tRDAST
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
Remark effective only separate mode.
Data Sheet U10606EJ3V1DS
µPD78P078Y
External data access wait):
tADS tASTH ASTB tADD2 Low-order Hi-Z
8-bit address
High-order (low-order) 8-bit address Hi-Z Hi-Z
Read Data tRDD2 tRDH
Write Data
tADH
tASTRD tASTWR tWRL tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
Remark effective only separate mode. External data access (wait insertion):
tADS tASTH ASTB tASTRD tRDL2 tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL tWRADH tRDWD tWRWD tWDS
Low-order 8-bit address
High-order (low-order) 8-bit address tADD2 Hi-Z Hi-Z Hi-Z
Read Data tRDH
Write Data
tADH tRDD2
tWDH
Remark effective only separate mode.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm SCK0 SCK2 tKHm
tSIKm
tKSIm
tKSOm
Input Data
Output Data
Remark 2-wire serial mode:
tKCY5, tKL5, SCK0 tKH5,
tKSO5,
tSIK5,
tKSI5,
SB0,
mode
tKL5, SDA0, SDA1 tSBH tSBK tKH5, tKSI5, tSIK5, tKSO5, tKCY5, tKSB tSBK tKSB
Data Sheet U10606EJ3V1DS
µPD78P078Y
3-wire serial mode with automatic transmission/reception function:
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tKL9, tKCY9, tR10 tSBD tSBW
3-wire serial mode with automatic transmission/reception function (busy processing):
SCK1
9Note
10Note tBYS
10+nNote tBYH tSPS
BUSY (Active high)
Note signal actually here, represented this show timing.
UART mode (external clock input):
tKCY13 tKL13 tR13 ASCK tKH13 tF13
Data Sheet U10606EJ3V1DS
µPD78P078Y
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Total error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
AVREF0 AVDD tCONV tSAMP vIAN AVREF0 RAIREF0 19.1 12/fXX AVSS
Conversion time Sampling time Analog input voltage Reference voltage AVREF0 AVSS resistance
AVREF0 AVDD
Note Excluding quantization error (±1/2 LSB). Shown percentage full scale value. Remark fXX: Main system clock frequency fX/2) Main system clock oscillation frequency Converter Characteristics +85°C, AVSS
Parameter Resolution Total error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Note
Setting time
Note
Note
AVREF1 AVREF1 AVREF1
Output resistor Analog reference voltage AVREF1 AVSS resistance
AVREF1 RAIREF1
Note
DACS0, DACS1
Note
Notes converter output load resistance load capacitance. Value converter channel. Remark DACS0, DACS1: conversion value setting register
Data Sheet U10606EJ3V1DS
µPD78P078Y
Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR When subsystem clock stopped feedback resistor disconnected Release signal setup time Oscillation stabilization wait time tSREL tWAIT Release RESET Release interrupt Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Note 212/fXX 214/fXX 217/fXX selected (OSTS0 OSTS2) oscillation stabilization time selection register. Remark fXX: Main system clock frequency fX/2) Main system clock oscillation frequency
Data Retention Timing (STOP mode released RESET)
Internal reset operation HALT mode STOP mode Data retention mode VDDDR STOP instruction execution RESET tSREL Operating mode
tWAIT
Data Retention Timing (Standby release signal: STOP mode released interrupt signal)
HALT mode STOP mode Data retention mode VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT tSREL Operating mode
Data Sheet U10606EJ3V1DS
µPD78P078Y
Interrupt Input Timing
tINTL INTP0 INTP6 tINTH
RESET Input Timing
tRSL
RESET
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Programming Characteristics Characteristics PROM Write Mode ±5°C, ±0.25 12.5 ±0.3
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol Symbol 12.2 6.25 12.5
Note
Test Conditions
MIN. 0.7VDD
TYP.
MAX. 0.3VDD
Unit
12.8 6.75
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Input voltage, high Input voltage, Output voltage, high Symbol VOH1 VOH2 Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current Symbol VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD,
Note
Test Conditions
MIN. 0.7VDD
TYP.
MAX. 0.3VDD
Unit
Note Corresponding µPD27C1001A symbol.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Characteristics PROM Write Mode Page program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time setup time setup time Input data setup time Address hold time (from Symbol tOES tCES tAHL tAHV Input data hold time (from Data output float delay time setup time setup time Program pulse width Valid data delay time pulse width during data latching setup time hold time hold time tPGMS tCEH tOEH tPGMS tCEH tOEH tVPS tVDS tVPS tVCS 0.095 0.105 Symbol tOES tCES tAHL tAHV
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Byte program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time setup time setup time Symbol tOES tCES Symbol tOES tCES
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Input data setup time Address hold time (from Input data hold time (from PGM) Data output float delay time setup time setup time Program pulse width Valid data delay time hold time tVPS tVDS tOEH
tVPS tVCS
0.095 0.105
Note Corresponding µPD27C1001A symbol.
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Address Data output delay time Data output delay time Data output delay time Data output float delay time Address Data hold time Symbol tACC Symbol tACC
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
PROM Programming Mode 25°C,
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Write Mode Timing (page program mode)
Page Data Latch Hi-Z tVPS tVDS VDD+1.5 tCES tOES tCEH tOEH Data Input Hi-Z tPGMS Output
Data
Page Program
Program Verify
tAHL
tAHV
Hi-Z
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Write Mode Timing (byte program mode)
Program VDD+1.5 tOES tCES tVPS Hi-Z Data Input Hi-Z Data Output Hi-Z Program Verify
tVDS
tOEH
Cautions should applied before VPP, removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP. PROM Read Mode Timing
Effective Address
tACCNote Hi-Z tOENote Data Output Hi-Z tDFNote
Notes want read within range tACC, make input delay time from fall maximum tACC-tOE. time from when either first reaches VIH.
Data Sheet U10606EJ3V1DS
µPD78P078Y
PROM Programming Mode Setting Timing
RESET
tSMA Effective Address
Data Sheet U10606EJ3V1DS
µPD78P078Y
CHARACTERISTIC CURVES (REFERENCE VALUES)
MHz)
10.0
25C)
HALT oscillation, oscillation)
Supply Current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001 Supply Voltage
Data Sheet U10606EJ3V1DS
µPD78P078Y
MHz, MHz)
10.0
25C)
HALT oscillation, oscillation)
Supply Current [mA]
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply Voltage
Data Sheet U10606EJ3V1DS
µPD78P078Y
PACKAGE DRAWINGS
100-PIN PLASTIC (14x20)
detail lead
NOTE Each lead centerline located within 0.15 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 23.6±0.4 20.0±0.2
14.0±0.2
17.6±0.4
0.30±0.10
0.15
0.65 (T.P.) 1.8±0.2 0.8±0.2
0.15+0.10 -0.05
0.10 2.7±0.1 0.1±0.1 5°±5°
MAX.
P100GF-65-3BA1-4
Remark shape material versions same those mass-produced versions.
Data Sheet U10606EJ3V1DS
µPD78P078Y
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
detail lead
NOTE Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark shape material versions same those mass-produced versions.
Data Sheet U10606EJ3V1DS
µPD78P078Y
RECOMMENDED SOLDERING CONDITIONS
recommended that µPD78P078Y soldered under following conditions. soldering methods conditions other than those recommended, please contact your sales representative. technical information, following website. Semiconductor Device Mount Manual Table 10-1. Soldering Conditions Surface Mount Devices (1/2) µPD78P078YGF-3BA: 100-pin plastic resin thickness:
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less Wave soldering Solder temperature: 260°C below, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) Partial heating temperature: 350°C below, Flow time: seconds less (per row) WS60-00-1 VP15-00-3 Symbol IR35-00-3
Caution
different soldering methods together (except partial heating method).
µPD78P078YGC-8EU: 100-pin plastic LQFP (fine pitch) resin thickness: 1.40
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less, Exposure limit: days hours pre-baking required 125°C afterwards)
Note
Symbol IR35-107-2
Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less, Exposure limit: days hours pre-baking required 125°C afterwards)
Note
VP15-107-2
Partial heating
temperature: 350°C below, Flow time: seconds less (per row)
Note
Exposure limit before soldering after pack package opened. Storage conditions: 25°C relative humidity less.
Caution different soldering methods together (except partial heating method).
Data Sheet U10606EJ3V1DS
µPD78P078Y
Table 10-1. Soldering Conditions Surface Mount Devices (2/2) µPD78P078YGF-3BA-A: 100-pin plastic resin thickness:
Soldering Method Soldering Conditions Recommended Condition Symbol IR60-203-3
Note
Infrared reflow
Package peak temperature: 260°C, Time: seconds max. 220°C higher), Count: Three times less, Exposure limit: days prebake 125°C hours) (after that,
Wave soldering Partial heating
details, contact Electronics sales representative. temperature: 350°C max., Time: seconds max. (per row)
Note
After opening pack, store 25°C less less allowable storage period.
Caution different soldering methods together (except partial heating). Remark Products that have part numbers suffixed "-A" lead-free products.
Data Sheet U10606EJ3V1DS
µPD78P078Y
APPENDIX DEVELOPMENT TOOLS following dvelopment tools available support development systems using µPD78P078Y. Language Processing Software
RA78K/0
Notes
Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file common µPD78078 Subseries compiler library source file common 78K/0 Series
CC78K/0
Notes
DF78078
Notes
CC78K/0-L
Notes
PROM Writing Tools
PG-1500 PA-78P078GC PA-78P078GF PA-78P078KL-T PG-1500 Controller
Notes
PROM programmer Programmer adapter connected PG-1500
Control program PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78064GC-R EP-78064GF-R EV-9200GF-100 TGC-100SDW Socket mounted target system board prepared 100-pin plastic (GF-3BA type) Adapter mounted target system board prepared 100-pin plastic LQFP (GC-8EU type) This product TOKYO ELETECH Corporation (Tokyo (03) 5295-1661). Consult sales representative purchase. EV-9900 SM78K0 ID78K0
Notes
In-circuit emulator common 78K/0 Series In-circuit emulator common 78K/0 Series (for integrated debugger) Break board common 78K/0 Series Emulation board evaluation µPD78078 Subseries Emulation probe common µPD78064 Subseries
Tool used removing µPD78P078YKL-T from EV-9200GF-100. System simulator common 78K/0 Series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file common µPD78078 Subseries
Notes
SD78K/0
Notes
DF78078
Notes
Real-Time
RX78K/0 MX78K0
Notes
Real-time used 78K/0 Series used 78K/0 Series
Notes
Data Sheet U10606EJ3V1DS
µPD78P078Y
Fuzzy Inference Development Support System
FE9000 FT9080 FI78K0
Note
/FE9200
Note
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Note
/FT9085
Note
Notes
FD78K0
Notes
Notes PC-9800 Series (MS-DOSTM) based PC/ATand compatibles DOSTM/IBM DOSTM/MS-DOS) based HP9000 Series 300(HP-UXTM) based HP9000 Series 700(HP-UX), SPARCstation(SunOSTM), EWS4800 Series (EWS-UX/V) based PC-9800 Series (MS-DOS WindowsTM) based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Remarks Refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, RX78K/0 combination with DF78078.
Data Sheet U10606EJ3V1DS
µPD78P078Y
DRAWINGS CONVERSION SOCKET (EV-9200GF-100) RECOMMENDED FOOTPRINT
Figure A-1. Drawing EV-9200GF-100 (for reference only)
EV-9200GF-100
No.1 index
EV-9200GF-100-G0E ITEM MILLIMETERS 24.6 18.6 12.0 22.6 25.3 16.6 19.3 0.35 INCHES 0.969 0.827 0.591 0.732 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014
0.091 0.059
Data Sheet U10606EJ3V1DS
µPD78P078Y
Figure A-2. Recommended Footprint EV-9200GF-100 (for reference only)
EV-9200GF-100-P1E ITEM Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.65±0.02 29=18.85±0.05 0.026 +0.001 1.142=0.742 +0.002 -0.002 -0.002 0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 0.05 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
Data Sheet U10606EJ3V1DS
µPD78P078Y
DRAWINGS CONVERSION ADAPTER (TGC-100SDW)
Figure A-3. Drawings TGC-100SDW (for reference only) (Unit:
Protrusion height
ITEM MILLIMETERS 21.55 0.5x24=12 0.5x24=12 15.0 21.55 INCHES 0.848 0.020x0.945=0.472 0.020 0.020x0.945=0.472 0.591 0.848 ITEM MILLIMETERS 14.45 1.85±0.25 0.25 INCHES 0.569 0.073±0.010 0.138 0.079 0.154 0.010
3.55
10.9 13.3 15.7 18.1 13.75 0.5x24=12.0 1.125±0.3 1.125±0.2 10.0 11.3 18.1
0.140
0.429 0.524 0.618 0.713 0.541 0.020x0.945=0.472 0.044±0.012 0.044±0.008 0.295 0.394 0.445 0.713
16.0 1.125±0.3 0~5°
0.177
0.630 0.044±0.012 0.000~0.197° 0.232 0.031 0.094 0.106 TGC-100SDW-G0E
0.197
0.197 0.051 0.071 0.079
0.035 0.012
Note
Product TOKYO ELETECH CORPORATION.
Data Sheet U10606EJ3V1DS
µPD78P078Y
APPENDIX RELATED DOCUMENTS
related documents indicated this publication include preliminary versions. However, preliminary versions marked such. Documents Related Devices
Document Name Document Japanese English U10641E U10605E This document Planned Planned U12326E U10182E
µPD78078, 78078Y Subseries User's Manual µPD78076Y, 78078Y Data Sheet µPD78P078Y Data Sheet µPD78074BY, 78075BY Data Sheet µPD78075B, 78075BY Subseries User's Manual
78K/0 Series User's Manual-Instructions 78K/0 Series Instruction Table 78K/0 Series Instruction
U10641J U10605J U10606J Planned U12560J U12326J U10903J U10904J IEM-5601 IEA-767
µPD78078Y Subseries Special Function Register Table
78K/0 Series Application Note-Basics (III)
Documents Related Development Tools (User's Manual) (1/2)
Document Name Document Japanese RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly language Structured assembly language CC78K Series Compiler Operation Language CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-78000-R IE-78000-R-BK IE-78000-R-A IE-78078-R-EM EP-78064 Programming know-how EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J EEU-867 U10057J U10775J EEU-934 English EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E EEU-1427 U10057E U10775E EEU-1522
Caution contents documents listed above subject change without prior notice. Make sure latest edition when starting design.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Documents Related Development Tools (User's Manual) (2/2)
Document Name Document Japanese SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External parts user open interface specification ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based Reference Reference Guides Introduction Reference Introduction Reference U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J U11539E U11649E U10539E EEU-1414 U11279E U10181J U10092J English U10181E U10092E
Documents Related Embedded Software (User's Manual)
Document Name Document Japanese 78K/0 Series Real-time Basics Installation 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basics U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921 English EEU-1438 EEU-1444 EEU-1441 EEU-1458
Other Documents
Document Name Document Japanese SEMICONDUCTOR SELECTION GUIDE Products Packages Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcomputer Product Series Guide Third Party Products X13769X Note C11531J C10983J MEM-539 C11893J U11416J C11531E C10983E MEI-1202 English
Note "Semiconductor Device Mount Manual" website Caution contents documents listed above subject change without prior notice. sure latest edition when starting design.
Data Sheet U10606EJ3V1DS
µPD78P078Y
NOTES CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM INPUT Waveform distortion input noise reflected wave cause malfunction. input CMOS device stays area between (MAX) (MIN) noise, etc., device malfunction. Take care prevent chattering noise from entering device when input level fixed, also transition period when input level passes through area between (MAX) (MIN).
HANDLING UNUSED INPUT PINS Unconnected CMOS device inputs cause malfunction. input unconnected, possible that internal input level generated noise, etc., causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected resistor there possibility that will output pin. handling related unused pins must judged separately each device according related specifications governing device.
PRECAUTION AGAINST strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work benches floors should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION Power-on does necessarily define initial status device. Immediately after power source turned devices with reset functions have been initialized. Hence, power-on does guarantee output levels, settings contents registers. device initialized until reset signal received. reset operation must executed immediately after power-on devices with reset functions.
POWER ON/OFF SEQUENCE case device that uses different power supplies internal operation external interface, rule, switch external power supply after switching internal power supply. When switching power supply off, rule, switch external power supply then internal power supply. reverse power on/off sequences result application overvoltage internal elements device, causing malfunction degradation internal elements passage abnormal current. correct power on/off sequence must judged separately each device according related specifications governing device.
INPUT SIGNAL DURING POWER STATE input signals pull-up power supply while device powered. current injection that results from input such signal pull-up power supply cause malfunction abnormal current that passes device this time cause degradation internal elements. Input signals during power state must judged separately each device according related specifications governing device.
Data Sheet U10606EJ3V1DS
µPD78P078Y
Regional Information
Some information contained this document vary from country country. Before using Electronics product your application, pIease contact Electronics office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country. [GLOBAL SUPPORT]
Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782
Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65030
Sucursal
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-558-3737
Madrid, Spain Tel: 091-504
Succursale
France Tel: 01-30-67
Filiale Italiana
Electronics Shanghai Ltd.
Shanghai, P.R. China Tel: 021-5888-5400
Milano, Italy Tel: 02-66
Branch Netherlands
Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377
Eindhoven, Netherlands Tel: 040-265
Tyskland Filial
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311
Taeby, Sweden Tel: 08-63
United Kingdom Branch
Milton Keynes, Tel: 01908-691-133
J05.6
Data Sheet U10606EJ3V1DS
µPD78P078Y
FIP, IEBus, QTOP trademarks Electronics Corporation. MS-DOS Windows registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems Corporation. NEWS NEWS-OS trademarks Sony Corporation.
These commodities, technology software, must exported accordance with export administration regulations exporting country. Diversion contrary that country prohibited.
information this document current August, 2005. information subject change without notice. actual design-in, refer latest publications Electronics data sheets data books, etc., most up-to-date specifications Electronics products. products and/or types available every country. Please check with Electronics sales representative availability additional information. part this document copied reproduced form means without prior written consent Electronics. Electronics assumes responsibility errors that appear this document. Electronics does assume liability infringement patents, copyrights other intellectual property rights third parties arising from Electronics products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Electronics others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Electronics assumes responsibility losses incurred customers third parties arising from these circuits, software information. While Electronics endeavors enhance quality, reliability safety Electronics products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects Electronics products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment anti-failure features. Electronics products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only Electronics products developed based customerdesignated "quality assurance program" specific application. recommended applications Electronics product depend quality grade, indicated below. Customers must check quality grade each Electronics product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade Electronics products "Standard" unless otherwise expressly specified Electronics data sheets data books, etc. customers wish Electronics products applications intended Electronics, they must contact Electronics sales representative advance determine Electronics' willingness support given application. (Note) "NEC Electronics" used this statement means Electronics Corporation also includes majority-owned subsidiaries. "NEC Electronics products" means product developed manufactured Electronics defined above).
11-1

µPD78P078Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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