August 2009 IRS2609DSPbF HALF-BRIDGE DRIVER Features

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August 2009 IRS2609DSPbF HALF-BRIDGE DRIVER Features

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IRS2609DSPbF
August 2009
IRS2609DSPbF
HALF-BRIDGE DRIVER
Features
Floating channel designed bootstrap operation Fully operational +600 Tolerant negative transient voltage dV/dt immune Gate drive supply range from Undervoltage lockout both channels input logic compatible Cross-conduction prevention logic Matched propagation delay both channels High side output phase with input Internal dead-time Lower di/dt gate driver better noise immunity Shut down input turns both channels Integrated bootstrap diode RoHS compliant
Packages
8-Lead SOIC
Product Summary
VOFFSET IO+/VOUT ton/off (typ.) Dead Time max.
Description
IRS2609D high voltage, high speed power MOSFET IGBT drivers with dependent high side referenced output channels. Proprietary HVIC latch immune CMOS technologies enable ruggedized monolithic construction. logic input compatible with Standard CMOS LSTTL output, down logic. output drivers feature high pulse current buffer stage designed minimum driver cross-conduction. floating channel used drive N-channel power MOSFET IGBT high side configuration which operates
Applications:
*Air Conditioner *Micro/Mini Inverter Drives *General Purpose Inverters *Motor Control
Typical Connection
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IRS2609DSPbF Qualification Information
Qualification Level
Industrial Comments: This passed JEDEC's Industrial qualification. IR's Consumer qualification level granted extension higher Industrial level. MSL2, 260°C (per IPC/JEDEC J-STD-020) Class (per JEDEC standard JESD22-A114) Class (per EIA/JEDEC standard EIA/JESD22-A115) Class Level (per JESD78)
Moisture Sensitivity Level Human Body Model Machine Model Latch-Up Test RoHS Compliant
Qualification standards found International Rectifier's site http://www.irf.com/ Higher qualification ratings available should user have such requirements. Please contact your International Rectifier sales representative further information.
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IRS2609DSPbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced COM. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
dVS/dt RthJA
Definition
High side floating absolute voltage High side floating supply offset voltage High side floating output voltage side logic fixed supply voltage side output voltage Logic input voltage Logic ground Allowable offset supply voltage transient Package power dissipation Thermal resistance, junction ambient Junction temperature Storage temperature Lead temperature (soldering, seconds)
Min.
-0.3 -0.3 -0.3 -0.3
Max.
0.625
Units
V/ns
Recommended Operating Conditions
proper operation device should used within recommended conditions. offset rating tested with supplies biased differential.
Symbol
Definition
High side floating supply absolute voltage Static High side floating supply offset voltage Transient High side floating supply offset voltage High side floating output voltage side logic fixed supply voltage side output voltage Logic input voltage
Min.
COM- 8(Note (Note2)
Max.
Units
Ambient temperature Note Logic operational +600 Logic state held VBS. Note Operational transient negative with pulse width. Guaranteed design. Refer Application Information section this datasheet more details.
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IRS2609DSPbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) VCC, 1000 unless otherwise specified.
Symbol
toff
Definition
Turn-on propagation delay Turn-off propagation delay Shut-down propagation delay Delay matching, turn-on/off Turn-on rise time Turn-off fall time Deadtime: turn-off turn-on(DTLO-HO) turn-off turn-on (DTHO-LO) Delay matching time OFF) Deadtime matching DTLO-HO DTHO-LO
Units Test Conditions
1100
Without external deadtime
Static Electrical Characteristics
VBIAS (VCC, VBS) COM, unless otherwise specified. VIL, parameters referenced VCC/COM applicable respective input leads: parameters referenced applicable respective output leads:
Symbol
IQBS IQCC IIN+ IINISD, ISD, THVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH IORbs
Definition
logic input voltage logic logic input voltage logic High level output voltage, VBIAS level output voltage, Offset supply leakage current Quiescent supply current Quiescent supply current Logic input bias current Logic input bias current input positive going threshold input negative going threshold supply undervoltage positive going Threshold supply undervoltage negative going Threshold Hysteresis Output high short circuit pulsed current Output short circuit pulsed current Bootstrap resistance
Units Test Conditions
1000 2000 3000
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IRS2609DSPbF
Functional Block Diagrams
Lead Definitions
Symbol
Description
Logic input high side gate driver outputs LO), phase Logic input shutdown High side floating supply High side gate drive output High side floating supply return side logic fixed supply side gate drive output side return
Lead Assignments
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IRS2609DSPbF Application Information Additional Details
Informations regarding following topics included subsections within this section datasheet.
IGBT/MOSFET Gate Drive Switching Timing Relationships Deadtime Matched Propagation Delays Shut down Input Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Integrated Bootstrap Functionality Negative Transient Layout Tips Additional Documentation
IGBT/MOSFET Gate Drive IRS2609D HVICs designed drive MOSFET IGBT power devices. Figures illustrate several parameters associated with gate drive functionality HVIC. output current HVIC, used drive gate power switch, defined voltage that drives gate external power switch defined high-side power switch low-side power switch; this parameter sometimes generically called VOUT this case does differentiate between high-side low-side output voltage.
VCC)
VCC)
VLO)
COM) COM)
Figure HVIC sourcing current
Figure HVIC sinking current
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IRS2609DSPbF
Switching Timing Relationships relationships between input output signals IRS2609D illustrated below Figures From these figures, definitions several timing parameters (i.e. tON, tOFF, associated with this device.
Figure Switching time waveforms
Figure Input/output timing diagram Deadtime This family HVICs features integrated deadtime protection circuitry. deadtime these fixed; other within IR's HVIC portfolio feature programmable deadtime greater design flexibility. deadtime feature inserts time period minimum deadtime) which both high- low-side power switches held off; this done ensure that power switch being turned fully turned before second power switch turned This minimum deadtime automatically inserter whenever external deadtime shorter than external deadtimes larger than modified gate driver. Figure illustrates deadtime period relationship between output gate signals. deadtime circuitry IRS2609D matched with respect high- low-side outputs. Figure defines deadtime parameters (i.e., DTLO-HO DTHO-LO); deadtime matching parameter (MDT) associated with IRS2609D specifies maximum difference between DTLO-HO DTHO-LO. Matched Propagation Delays IRS2609D family HVICs designed with propagation delay matching circuitry. With this feature, IC's response output signal input requires approximately same time duration (i.e., tON, tOFF) both low-side channels high-side channels; maximum difference specified delay matching parameter (MT). propagation turn-on delay (tON) IRS2609D matched propagation turn-on delay (tOFF).
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IRS2609DSPbF
Shut down Input IRS2609D family HVICs equipped with shut down (/SD) input that used shutdown enable HVIC. When high state HVIC able operate normally. When state HVIC tristated.
DTLO-HO
DTHO-LO
DTLO-HO
DTHO-LO
Figure Shut down
Figure Dead time Definition
Figure Delay Matching waveform Definition Input Logic Compatibility inputs this compatible with standard CMOS outputs. IRS2609D been designed compatible with logic-level signals. IRS2609D features integrated Zener clamp /SD. Figure illustrates input signal IRS2609D, input threshold values, logic state result input signal.
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IRS2609DSPbF
Input Signal (IRS23364D)
Input Logic Level
High
Figure input thresholds Undervoltage Lockout Protection This family provides undervoltage lockout protection both (logic low-side circuitry) power supply (high-side circuitry) power supply. Figure used illustrate this concept; VBS) plotted over time waveform crosses UVLO threshold (VCCUV+/- VBSUV+/-) undervoltage protection enabled disabled. Upon power-up, should voltage fail reach VCCUV+ threshold, will turn-on. Additionally, voltage decreases below VCCUV- threshold during operation, undervoltage lockout circuitry will recognize fault condition shutdown high- low-side gate drive outputs, FAULT will transition state inform controller fault condition. Upon power-up, should voltage fail reach VBSUV threshold, will turn-on. Additionally, voltage decreases below VBSUV threshold during operation, undervoltage lockout circuitry will recognize fault condition, shutdown high-side gate drive outputs UVLO protection ensures that drives external power devices only when gate supply voltage sufficient fully enhance power devices. Without this feature, gates external power switch could driven with voltage, resulting power switch conducting current while channel impedance high; this could result very high conduction losses within power device could lead power device failure.
Figure UVLO protection
Shoot-Through Protection IRS2609D high-voltage equipped with shoot-through protection circuitry (also known cross-conduction prevention circuitry).
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IRS2609DSPbF
Integrated Bootstrap Functionality IRS2609D embeds integrated bootstrap that allows alternative drive bootstrap supply wide range applications. bootstrap connected between floating supply (see Fig. 10).
BootFet
Figure Semplified BootFET connection integrated bootstrap feature used either parallel with external bootstrap network (diode resistor) replacement integrated bootstrap replacement external bootstrap network have some limitations very high duty cycle, corresponding very short pulses, bootstrap equivalent resistance RBS. summary bootstrap state follows: Bootstrap turns-off (immediately) stays when least following conditions met: high, high 1.1*VCC) high, high period excluded) high, high high 1.1*VCC) (during period) Bootstrap turns-on when: high, 1.1(VCC)) high, high 1.1(VCC)) (during period). Please refer BootFET timing diagram more details.
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IRS2609DSPbF
BootStrap
1.1*Vcc
Figure BootFET timing diagram
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IRS2609DSPbF
Negative Transient common problem today's high-power switching converters transient response switch node's voltage power switches transition quickly while carrying large current. typical 3-phase inverter circuit shown Figure here define power switches diodes inverter. high-side switch (e.g., IGBT Figures switches off, while phase current flowing inductive load, current commutation occurs from high-side switch (Q1) diode (D2) parallel with low-side switch same inverter leg. same instance, voltage node VS1, swings from positive voltage negative voltage.
Figure Three phase inverter
Figure conducting
Figure conducting
Also when phase current flows from inductive load back inverter (see Figures 16), IGBT switches current commutation occurs from same instance, voltage node, VS2, swings from positive voltage negative voltage.
Figure conducting
Figure conducting
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IRS2609DSPbF
However, real inverter circuit, voltage swing does stop level negative bus, rather swings below level negative bus. This undershoot voltage called "negative transient". circuit shown Figure depicts three phase inverter; Figures show simplified illustration commutation current between parasitic inductances power circuit from bonding tracks lumped together each IGBT. When high-side switch below voltage voltage drops associated with power switch parasitic elements circuit. When high-side power switch turns off, load current momentarily flows low-side freewheeling diode inductive load connected (the load shown these figures). This current flows from (which connected HVIC) load negative voltage between induced (i.e., HVIC higher potential than pin).
Figure Parasitic Elements
Figure positive
Figure negative
typical motor drive system, dV/dt typically designed range V/ns. negative transient voltage exceed this range during some events such short circuit over-current shutdown, when di/dt greater than normal operation. International Rectifier's HVICs have been designed robustness required many today's demanding applications. indication IRS2609D's robustness seen Figure where there represented IRS2609D Safe Operating Area VBS=15V based repetitive negative spikes. negative transient voltage falling grey area (outside SOA) lead permanent damage; viceversa unwanted functional anomalies permanent damage appear negative transients fall inside SOA. VBS=15V case transients greater than -16.5 period time greater than HVIC will hold design high-side outputs state
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IRS2609DSPbF
Figure Negative transient IRS2608D VBS=15V Even though IRS2609D been shown able handle these large negative transient conditions, highly recommended that circuit designer always limit negative transients much possible careful layout component use. Layout Tips Distance between high voltage components: It's strongly recommended place components tied floating voltage pins near respective high voltage portions device. Please Case Outline information this datasheet details.
Ground Plane: order minimize noise coupling, ground plane should placed under near high voltage floating side.
Gate Drive Loops: Current loops behave like antennas able receive transmit noise (see Figure 21). order reduce coupling improve power switch turn on/off performance, gate drive loops must reduced much possible. Moreover, current injected inside gate drive loop IGBT collector-to-gate parasitic capacitance. parasitic auto-inductance gate loop contributes developing voltage across gate-emitter, thus increasing possibility self turn-on effect.
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IRS2609DSPbF
Figure Antenna Loops
Supply Capacitor: recommended place bypass capacitor (CIN) between pins. ceramic ceramic capacitor suitable most applications. This component should placed close possible pins order reduce parasitic elements. Routing Placement: Power stage parasitic elements contribute large negative voltage transients switch node; recommended limit phase voltage negative transients. order avoid such conditions, recommended minimize high-side emitter low-side collector distance, minimize low-side emitter negative rail stray inductance. However, where negative spikes remain excessive, further steps taken reduce spike. This includes placing resistor less) between switch node (see Figure 22), some cases using clamping diode between (see Figure 23). DT04-4 www.irf.com more detailed information.
Figure resistor Additional Documentation
Figure clamping diode
Several technical documents related HVICs available www.irf.com; Site Search function document number quickly locate them. Below short list some these documents. DT97-3: Managing Transients Control Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: Floating MOS-Gate Driver
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IRS2609DSPbF
Figures 24-47 provide information experimental performance IRS2609D(S) HVIC. line plotted each figure generated from actual data. large number individual samples from multiple wafer lots were tested three temperatures (-40 order generate experimental (Exp.) curve. line labeled Exp. consist three data points (one data point each tested temperatures) that have been connected together illustrate understood trend. individual data points curve were determined calculating averaged experimental value parameter (for given temperature).
Turn-On Propagation Delay (ns)
Turn-Off Propagation Delay (ns)
1500 1200
Exp.
Exp.
Temperature
Temperature
Fig. Turn-on Propagation Delay Temperature
Turn-On Rise Time (ns)
Turn-Off fall Time (ns)
Fig. Turn-off Propagation Delay Temperature
Exp.
Exp.
Temperature (oC)
Temperature (oC)
Fig. Turn-on Rise Time Temperature
Fig. Turn-off Rise Time Temperature
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IRS2609DSPbF
VCCUV hysteresis
Temperature (oC)
VBSUV hysteresis
Exp.
Exp.
Temperature (oC)
Fig. Supply Hysteresis Temperature
Quiescent Current (mA)
Quiescent Current (µA)
Fig. Supply Hysteresis Temperature
Temperature (oC)
Exp.
Exp.
Temperature
Fig. Quiescent Supply Current Temperature
Exp.
Fig. Quiescent Supply Current Temperature
VCCUV+ Threshold
VCCUV- Threshold
Exp.
Temperature
Temperature
Fig. VCCUV+ Threshold Temperature
Fig. VCCUV- Threshold Temperature
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IRS2609DSPbF
Exp.
VBSUV+ Threshold
Temperature (oC)
VBSUV- Threshold
Exp.
Temperature
Fig. VBSUV+ Threshold Temperature
Fig. VBSUV- Threshold Temperature
High Level Output Voltage (mV)
Level Output Voltage (mV)
EXP.
Exp.
Temperature
Temperature
Fig. Level Output Voltage Temperature
Fig. High Level Output Voltage Temperature
Bootstrap Resistance
Exp.
VTH+
Exp.
Temperature (oC)
Temperature (oC)
Fig. Bootstrap Resistance Temperature
Fig. VTH+ Temperature
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IRS2609DSPbF
VTH-
VTH+
Exp.
Exp.
Temperature
Temperature
Fig. VTH- Temperature
Fig. VTH+ Temperature
VTH-
Exp.
Tbson_VccTYP(ns)
Exp.
Temperature (oC)
Temperature
Fig. VTH- Temperature
Shut-down propagation delay (ns)
Fig. Tbson_VCCTYP Temperature
1000
Temperature (oC)
Exp.
Deadtime (ns)
Exp.
Temperature
Fig. Shut-down Propagation Delay Temperature
Fig. Deadtime Temperature
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IRS2609DSPbF
(ns) (ns)
Exp.
Exp.
Temperature
Temperature (oC)
Fig. Delay Matching Temperature
Fig. Deadtime Matching Temperature
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IRS2609DSPbF
Case Outlines
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IRS2609DSPbF
Tape Reel Details: 8L-SOIC
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 7.90 8.10 3.90 4.10 11.70 12.30 5.45 5.55 6.30 6.50 5.10 5.30 1.50 1.50 1.60
8SOICN Imperial 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 0.059 0.062
REEL DIMENSIONS 8SOICN Metric Code 329.60 330.25 20.95 21.45 12.80 13.20 1.95 2.45 98.00 102.00 18.40 14.50 17.10 12.40 14.40
Imperial 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 0.724 0.570 0.673 0.488 0.566
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IRS2609DSPbF
ORDER INFORMATION
8-Lead SOIC IRS2609DSPbF 8-Lead SOIC Tape Reel IRS2609DSTRPbF
information provided this document believed accurate reliable. However, International Rectifier assumes responsibility consequences this information. International Rectifier assumes responsibility infringement patents other rights third parties which result from this information. license granted implication otherwise under patent patent rights International Rectifier. specifications mentioned this document subject change without notice. This document supersedes replaces information previously supplied.
technical support, please contact IR's Technical Assistance Center
WORLD HEADQUARTERS: Kansas St., Segundo, California 90245 Tel: (310) 252-7105
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August 2009 IRS2609DSPbF HALF-BRIDGE DRIVER Features

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