Document Number: AN3614 Rev. 05/2008 Designing Code MPC5510 Core

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Document Number: AN3614 Rev. 05/2008 Designing Code MPC5510 Core

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Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Document Number: AN3614 Rev. 05/2008
Designing Code MPC5510 Core
Daniel McKenna Applications Engineering,
Introduction
Contents
Introduction Requirements Acronyms Abbreviations. Overview MPC5510 Family Comparison Cores Dual Core Considerations Semaphores Principles Virtual Module Mathematics Signal Generation. Dual Core Aspects Code Compiling Dual Core Code Initializing Core. Configuring External Interrupts Sharing Data Between Cores Results.
powerful features MPC5510 family microcontrollers secondary core. This core, once reset, function independently primary core used range tasks, such running gateway functions between communications networks, managing processing, creating virtual peripherals, simply reducing load primary core carrying tasks required system. This application note describes features core, discusses aspects these features that should considered when creating code dual core device, demonstrates, through creation virtual peripheral, produce dual core code.
Requirements
make software, following hardware software components required: MPC5510 microcontroller
Freescale Semiconductor, Inc., 2008. rights reserved.
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Acronyms Abbreviations
evaluation board device platform device hardware interface between computer evaluation board. Tested interfaces: Lauterbach Datentechnik Power Debug Interface Microcomputer Systems Multilink compiler application code. Projects included for: Wind River Compiler V5.5.1.0 Freescale CodeWarrior MPC55xx V2.2 software tool debug. Tested software: Lauterbach Datentechnik Trace32 Build 11389 Microcomputer Systems ICDPPCNEXUS Debugger V1.13
CodeWarrior compiler integrated software debugger included with MPC5510 evaluation boards.
Acronyms Abbreviations
clock, reset power (control module) general purpose input/output interrupt controller (module) input/output processor interrupt service routine microcontroller unit memory management unit periodic interrupt timer pulse width modulation system integration unit variable length encoding (instruction set)
GPIO INTC
Overview MPC5510 Family
MPC5510 family 32-bit MCUs aimed next generation automotive body gateway applications. devices built proven Power Architecture, based successful, power-train targeted, MPC5500 family microcontrollers. These cost-efficient microcontrollers provide excellent performance whilst minimizing power consumption with introduction numerous power modes.
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Overview MPC5510 Family
members family come with Power Architecture Book compliant primary core e200z1, with majority also coming with secondary e200z0. This application note aimed only dual core devices.
Comparison Cores
When part brought reset, only active; remains reset until activated Once both cores running, they standalone operate independently each other; example, will continue operate disabled. Thus, both cores require their code, their main function code, have autonomous stacks.
4.1.1
Instruction Sets
main difference between cores instruction sets they execute; base Power Architecture Book extended Variable Length Encoded (VLE) set. compatible with instruction only. makes both 16-bit 32-bit instructions, giving greater code density with minimal loss performance. instructions recognized mnemonics their compulsory prefix. 16-bit instructions prefixed "se_"; example, se_addi 32-bit instructions prefixed "e_" ;for example, e_add16i Table compares different "add immediate" instructions. Notice format 16-bit instruction: there fewer bits available, source destination must same register, distance data must between this proves unsuitable, 32-bit instruction used instead.
Table Comparison Immediate between Instruction Sets
Type Book addi Mnemonic SIMM Description destination register source register SIMM signed 16-bit data source destination register OIM5 immediate offset (0-31) destination register source register signed 16-bit index
16-bit
se_addi
OIM5
32-bit
e_add16i
compiler switch decides Book code generated from source file. This generally changed file file basis. core contains memory management unit (MMU) that used define different sections memory. parameters sets whether memory section contains Book code. Hence, possible core alternate between Book code. This means that there requirement convert existing libraries code. core compatible with only, does require MMU.
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
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Overview MPC5510 Family
also responsible selecting endianness memory section. either endian little endian; endian only.
4.1.2
Access Shared Resources
Both cores have access memory peripherals along with other "bus masters" (FlexRay controller eDMA). crossbar switch used control access arbitration. core additional direct link flash memory, allowing gain instant access without first going through crossbar switch. This reduces access time allows both cores access different flash locations simultaneously. core based Harvard architecture, having individual instruction data buses, whereas core based Neumann architecture, having single, combined data/instruction bus. (Variations core exist MPC5510 family devices that based Harvard architecture. This application note focuses MPC5510's Z0.) Each core interrupts. Table shows which interrupts available each core:
Table Interrupts Available Each Core
Core Interrupt Type Critical Input Machine Check Instruction Storage External Input Alignment Program Interrupt Floating Point Unavailable System Call Decrementer Fixed-Interval Timer Core Watchdog Timer Data Error (MMU) Instruction Error (MMU) Debug IVOR IVOR0 IVOR1 IVOR3 IVOR4 IVOR5 IVOR6 IVOR7 IVOR8 IVOR10 IVOR11 IVOR12 IVOR13 IVOR14 IVOR15
External interrupts (IVOR4s) routed both cores, individual basis. IVOR12 corresponds watchdog timer, which present core only. However, envisaged that watchdog Miscellaneous Control Module (MCM) will used most customers, more features. Upon watchdog timeout, this either generate external interrupt IVOR4) perform system reset, resetting both cores. Both cores same speed, from same clock source, System Integration Unit (SIU).
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Overview MPC5510 Family
4.1.3
Core Registers
Figure Figure show registers core core, respectively.
SUPERVISOR Mode Program Model General Registers
Condition Register Count Register Link Register GPR31 General-Purpose Registers GPR0 GPR1
Exception Handling/Control Registers
General SPRG0 SPRG1 Save Restore SRR0 SRR1 CSRR0 CSRR1 DSRR0 DSRR1 Interrupt Vector Prefix IVPR
Exception Syndrome Machine Check Syndrome Register MCSR
Processor Control Registers
Machine State Processor Version Processor Hardware Implementation Dependent1 HID0 1008 HID1 1009
Data Exception Address DEAR
Memory Management Registers
Process
System Version1 1023 Debug Control DBCR0 DBCR1 DBCR2
Debug Registers2
Instruction Address Compare IAC1 IAC2 IAC3 IAC4 Debug Status DBSR
PID0
Configuration (Read-only MMUCFG 1015
Data Address Compare DAC1 DAC2
Cache Registers
Cache Configuration (Read-only) L1CFG0
These e200-specific registers supported other Power Architecture processors Optional registers defined Power Architecture Book
Figure Registers Core
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Overview MPC5510 Family
SUPERVISOR Mode Program Model SPRs General Registers
Condition Register Count Register Link Register GPR31 General-Purpose Registers GPR0 GPR1
Exception Handling/Control Registers
General SPRG0 SPRG1 SPRG2 SPRG3 SPRG4 SPRG5 SPRG6 SPRG7 User USPRG0 Save Restore SRR0 SRR1 CSRR0 CSRR1 DSRR0
Interrupt Vector Prefix IVPR
DSRR11
Exception Syndrome Machine Check Syndrome Register MCSR
Processor Control Registers
Machine State Processor Version Processor Hardware Implementation Dependent1 HID0 1008 HID1 1009
Data Exception Address DEAR
Register
Control1 BUCSR 1013
Timers
Time Base (write only) Decrementer DECAR
Context Control1 CTXCR ALTCTXCR
System Version1 1023
Control Status
Debug Registers
Debug Control DBCR0 DBCR1 DBCR2 DBCR3
Instruction Address Compare IAC1 IAC2 IAC3 IAC4 Assist MAS0 MAS1 MAS2 MAS3 MAS4 MAS6
Memory Management Registers
Process PID0 Control Configuration MMUCSR0 MMUCFG TLB0CFG TLB1CFG 1012 1015
Debug Status DBSR
Data Address Compare DAC1 DAC2
Debug Counter1 DBCNT
Cache Registers
Cache Configuration (Read-only)
These e200-specific registers supported other Power Architecture processors Optional registers defined Power Architecture Book-E architecture
L1CFG0
Figure Registers Core
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Dual Core Considerations
core does have timing registers present core, including time-of-day registers decrementer. General/User Special Purpose Registers (SPRG0:7/USPRG0) present core, core only SPRG0:1. core does have branch target buffer used core accelerate execution loops.
Dual Core Considerations
Writing code dual core requires different approach that required standard single core MCU. This section discusses approach problem, shows MPC5510 family features help simplify code development. both cores independent, separate startup files (crt0.s) required each core. These assign values global variables, both stacks both small data areas, then each program counter location main function each core. core must also write SRAM, initialize error correction syndrome. Designers have range options when splitting code between cores, vast amount literature available discussing variety scenarios. Examples include: Using secondary core solely deal with interrupts Using secondary core carry standalone function, example, gateway between networks virtual module, using software simulate another module (SCI, DSPI, etc.) Putting computationally intensive function (Manchester decoding, example) secondary core, having primary core call when necessary. Using secondary core error check processes being carried primary core. Carefully splitting code between cores ease load primary core. cores have access same peripheral/memory locations, vitally important avoid race conditions ensure data coherency. example, both cores have increment single variable (count), ideally following would happen: copies variable count from memory register (count increments count register (count copies count back memory (count copies variable count from memory register (count increments count register (count copies count back memory (count value stored memory would expected. However, should both cores access variable same time, following could happen: copies variable count from memory register (count copies variable count from memory register (count
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Dual Core Considerations
increments count register increments count register copies count back memory copies count back memory
(count (count (count (count
this instance, value would stored memory incorrectly Clearly, this causes errors code must avoided. prevent this from happening, MPC5510 family contains semaphore mechanism ,which used software control each core's access shared resources.
Semaphores
MPC5510 family, semaphores sixteen hardware enforced gates, each which take three states: Unlocked Locked Locked Semaphores represented state machine shown Figure
Semaphore locked Semaphore locked
GATEn GATEn
GATEn
GATEn
Semaphore Unlocked
Figure Semaphore State Machine
Semaphores software enforced, designer assign shared resource. When core requires access resource, should attempt lock appropriate gate. lock successful, core then sole access resource; not, resource currently other core. semaphore locked other core, designer either enter loop, continuously trying lock gate until successful, make notification interrupt, maximize performance. enabled, notification interrupt automatically generated when gate becomes unlocked, allowing core continue executing other code rather than continually polling semaphore.
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Principles Virtual Module
correct semaphores ensures data coherency memory ensures that peripherals work expected. generation dual core code demonstrated following sections setting virtual module core using Z1core alter parameters individual waveforms.
Principles Virtual Module
MPC5510 devices, usually achieved using easily configurable eMIOS module. However, sometimes desirable expand upon number available outputs. core ideal means creating additional unique signals with loading primary core (Z1). virtual module generates signals using core conjunction with Periodic Interrupt Timer (PIT) module System Integration Unit (SIU). module configured trigger periodic interrupt pre-defined period. This interrupt routed core Interrupt Controller, which then executes interrupt service routine (ISR) stored memory. configures output utilized pins, based user-supplied parameters each signal. Thus, resolution signal depends timeout period; that shorter timeout period leads more interrupts over period wave leading higher resolution. overview setup seen Figure
Initialized Generates interrupts predefined periods
Interrupt Controller Steers interrupts core
Core Executes Interrupt Service Routine stored memory
Contains algorithm generate PWMs
Signals Output GPIO pins connected LEDs/Lamps
Figure Overview Virtual Implementation
6.1.1
Mathematics Signal Generation
Periodic Interrupt Timer
create signal drive (period 6.25 with resolution 0.5% (that interrupts period), interrupt required every 6.25 ms/200 31.25
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
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Principles Virtual Module
interrupt timer should initialized 31.25 example, with system clock (period 15.625 ns), timer reset value must 31.25 s/15.625 2000.
6.1.2
Signal Parameters
Each channel used generate large number signals. Each these signals must have following parameters declared:
Period Duty Counter
number counts interrupts) contained period wave. count value which signal changes from high. Initially holds starting value count; from then holds current count value. starting value each waveform varied, prevent poor behavior resulting from many pins toggling once. GPIO port which signal generated.
6.1.3
Interrupt Service Routine
code every time interrupt occurs. compares count value period duty values, toggling relevant pin, necessary. then decrements count value. flow chart algorithm shown Figure
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Dual Core Aspects Code
Interrupt
Clear Interrupt Flag
channels True True count
False
False
output
True
count duty
False
Reset count (count period)
output
Decrement count
Next channel
Exit
Figure Flowchart Algorithm
Dual Core Aspects Code
This section considers dual core aspects code, discussing compilation, initialization core, configuration interrupts, semaphores
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC551x MPC5533 products MAPBGA packages; MPC5534 MPC5553 products MAPBGA packages; MPC5554, MPC5565, MPC5566 MPC5567 products MAPBGA packages
Dual Core Aspects Code
Compiling Dual Core Code
When compiling code both cores choice made whether have individual output files each core, combined output file that contains code both cores. some cases, linker dictates which method must used; other cases, decision left programmer. brief overview advantages each approach follows:. file: easier manage boundaries flash programming only linker file required Common code variables shared easily between cores, same they would shared across multiple files. Files: code each core completely separate entity. Thus, easy split cores between different programming groups even companies. Having separate linker files each core easier manage than single large linker file containing stacks small data areas. example, code compiled using WindRiver separate output files, whereas Codewarrior compiled code single output file. Both compilers instruction both cores.
Initializing Core
When device powers from reset, only core activated. core sets clock required then brings core reset, writing code start location Z0VEC register Clock, Reset Power Control (CRP) Module. When core brought reset, value Z0VEC register loaded program counter, execution begins immediately.
CRP.Z0VEC.R=0x4000A000; Bring reset Program Counter 0x4000A000
Figure Code Initialize Core
When both cores running, possible disable either core (but both) setting reset ZnVEC. This extremely useful power-saving feature, core need brought reset only long required. When only core running, attempt reset blocked.
Configuring External Interrupts
This section discusses interrupt possibilities core. Full details interrupts MPC5510 family, explanation software hardware based interrupt vectors, available 5510 Cookbook. word "external" denotes that interrupt occurred external core; that caused peripheral triggered software. discussed sections above, code requires interrupt that
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
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Dual Core Aspects Code
serviced core. case with interrupts requires prolog epilog code, vector table, IVOR table. code sets IVPR base address would loading value IVPR core register. Interrupt Controller (INTC) module then case, using registers (those ending PRC1), rather than those ending PRC0. example, configured software interrupts shown Figure
Initialize INTC software vector mode INTC.MCR.B.HVEN_PRC1 default vector table entry offsets bytes INTC.MCR.B.VTES_PRC1 INTC vector table base addr. INTC.IACKR_PRC1.R
Figure Code initialize interrupts
final step enable interrupts Machine State Register (MSR) core, thereby completing configuration core receive interrupts. Individual interrupts then directed both cores using Priority Select Register (PSR) INTC module.
Reset PRC_SEL
PRIO
PRC_SEL defines interrupt destination. Interrupt request sent processor (e200z1) Interrupt request sent both processors Reserved Interrupt request sent processor (e200z0) PRIO determines interrupt priority. lowest priority (effectively disabled); highest.
Figure Interrupt Priority Select Register
Sharing Data Between Cores
demonstrate maintain data coherency whilst sharing variables between cores, extra feature been added code give core ability periodically alter parameters signals. parameters each waveform stored structure that shared between both cores. core accesses this structure intermittently adjusts duty cycle first signal. core
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
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Results
makes structure only during ISR. avoid race conditions, semaphore must used designate which core control structure PWMs. interrupt occurs cannot obtain semaphore, there small chance that accuracy signal might deteriorate temporarily; however, parameters signal being altered this point signal will change anyway, this ignored. core requires control structure only while making alterations values. Figure shows flow chart semaphores locked.
Attempt lock gate
False
Read gate. ownership obtained?
True
Control resource obtained
Figure Flowchart Lock Semaphore Process
semaphore should released core which locked; however, reset mechanism available allow semaphore released either core, should need arise.
Results
Figure shows oscilloscope capture outputs with four different unique PWMs being generated.
Designing Code MPC5510 Core, Rev. Freescale Semiconductor
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Figure Scope Capture Four Outputs
Designing Code MPC5510 Core, Rev.
Results
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Document Number: AN3614
Rev. 05/2008

Document Number: AN3614 Rev. 05/2008 Designing Code MPC5510 Core

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