MPC5668x Microcontroller Data Sheet MPC5668x features: 32-bit cor
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MPC5668x
MPC5668x Microcontroller Data Sheet
MPC5668x features: 32-bit core complex (e200z650) Compliant with Power Architecture embedded category unified cache with line locking eight-entry store buffer Execution speed static 32-bit processor (e200z0) Execution speed static core speed MHz) on-chip flash Supports read during program erase operations, multiple blocks allowing EEPROM emulation (592 on-chip SRAM (MPC5668G) on-chip SRAM (MPC5668E) 16-entry Memory Protection Unit (MPC5668E only) Direct memory access controller 16-channel MPC5668G 32-channel MPC5668E Fast ethernet controller Supports 10-Mbps 100-Mbps IEEE 802.3 MII, 10-Mbps 7-wire interface IEEE 802.3 (compliant with IEEE 802.3 1998 edition) Media Local (MLB) interface (MPC5668G only) Supports logical channels, speed 1024 Interrupt controller (INTC) supports external interrupt vectors reserved) System clocks Frequency-modulated phase-locked loop (FMPLL) crystal oscillator (XTAL) crystal oscillator (XTAL) Dedicated internal oscillators Analog Digital Converter (ADC) module 10-bit resolution external channels internal channels (MPC5668G) internal channels (MPC5668E)
MAPBGA-208 MAPBGA-256
Cross-Triggering Unit (MPC5668E only) Internal conversion triggering Triggerable internal timers eMIOS200 Deserial Serial Peripheral Interface (DSPI) Four individual DSPI modules Full duplex, synchronous transfers Master slave operation Inter-IC communication (I2C) interface Four individual modules Multi-master operation Serial Communication Interface (eSCI) module Two-channel interface Configurable master eMIOS200 timed input/output channels, 16-bit timers (MPC5668G) channels, 16-bit timers (MPC5668E) Controller Area Network (FlexCAN) module Compliant with protocol specification, Version 2.0B active mailboxes, each configurable transmit receive Dual-channel FlexRay controller Full implementation FlexRay Protocol Specification 2.1, RevA message buffers JTAG controller (MPC5668G only) Compliant with IEEE 1149.1-2001 Nexus Development Interface (NDI) Available MAPBGA package only Compliant with IEEE-ISTO 5001-2003 Nexus class development support e200z650 Nexus class development support e200z0 Internal voltage regulator allows operation from single supply
This document contains information product under development. Freescale reserves right change discontinue this product without notice. Freescale Semiconductor, Inc., 2009. rights reserved. Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5668X Rev. 9/2009
Table Contents
Ordering Information. Orderable Parts. MPC5668x Block Diagrams Assignments 208-ball MAPBGA Assignments 256-ball MAPBGA Assignments Muxing Reset States 3.3.1 Power Ground Supply Summary Electrical Characteristics Maximum Ratings Thermal Characteristics 4.2.1 General Notes Specifications Maximum Junction Temperature Characteristics Electrical Specifications Electrical Specifications Operating Current Specifications Current Specifications 4.7.1 VDD33 Current Specifications 4.10 4.11 4.12 4.13 4.14 Voltage Characteristics Oscillators Electrical Characteristics FMPLL Electrical Characteristics. Electrical Characteristics. Flash Memory Electrical Characteristics Specifications Timing 4.14.1 Reset Boot Configuration Pins 4.14.2 External Interrupt (IRQ) Non-Maskable Interrupt (NMI) Pins 4.14.3 JTAG (IEEE 1149.1) Interface 4.14.4 Nexus Debug Interface. 4.14.5 Enhanced Modular Subsystem (eMIOS) 4.14.6 Deserial Serial Peripheral Interface (DSPI) 4.14.7 Interface 4.14.8 Fast Ethernet Interface Package Characteristics Package Mechanical Data Revision History
Table MPC5668G/MPC5668E Comparison
Feature Package with Ethernet (FEC) MediaLB (MLB-DIM) FlexRay (10-bit) Total Timer (eMIOS200) Cross Trigger Unit (CTU) (eSCI) (DSPI) (FlexCAN) Nexus3 Debug (e200Z6) Nexus2+ Debug (e200Z0) MPC5668G MAPBGA MAPBGA MPC5668E MAPBGA MAPBGA
16-channel (128 Message Buffers) internal channels Supports external channels channels, 16-bit Supported 256BGA emulation package
entry 32-channel internal channels Supports external channels channels, 16-bit Supported 256BGA emulation package
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Ordering Information
Ordering Information
Orderable Parts
5668G
Qualification status Core code Device number Fabrication Site Revision Temperature range Package identifier Tape reel status
Qualification Status Prototype Fully spec. qualified, general market flow Fully spec. qualified, automotive flow Core Code Power Architecture
Fabrication Site Freescale Temperature Range
Package Identifier MAPBGA Pb-free MAPBGA Pb-free Tape Reel Status Tape reel (blank) Trays
Note: options available devices. Refer Table
Table shows orderable part numbers MPC5668x. Table Orderable Part Numbers
Freescale Part Number1 SPC5668GF0AVMG SPC5668GF0AVMJ4
Speed (MHz) Package Description MPC5668G MAPBGA package Lead-free (PbFree) MPC5668G MAPBGA package Lead-free (PbFree) Max3 (fMAX)
Operating Temperature2 (TL) (TH)
packaged devices PPC5668x, rather than MPC5668x SPC5668x, until product qualifications complete. unpackaged device prefix PCC, rather than SCC, until product qualification complete. configurations available parts. lowest ambient operating temperature (TA) referenced highest ambient operating temperature referenced Maximum speed maximum frequency allowed including frequency modulation (FM). MAPBGA package MPC5668x intended full production qualification, supplied development only.
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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MPC5668x Block Diagrams
MPC5668x Block Diagrams
DEBUG JTAG Nexus3(Z6) Nexus2+(Z0)
Figure shows top-level block diagram MPC5668G device.
MPC5668G
MASTERS e200z650 Core MMU(32TLB)
XTAL
4-40 XTAL
VREG Controller
FMPLL
RTC/API S
Semaphores e200z0 Core FPU/SPE Cache 16ChDMA MLB-DIM FlexRay
INTC
Crossbar Switch (XBAR)
AIPS(0) Bridge eSCI eMIOS DSPI FlexCAN
AIPS(1) Bridge DSPI SRAM (ECC) ECSM LEGEND
INTC JTAG MLB-DIM SSWT VREG
Flash (ECC) ECSM
SRAM (ECC) Standby ECSM
Analog Digital Converter Boot Assist Module DSPI Serial Peripherals Interface Error Correction Code ECSM Error Correction Status Module eMIOS Timed Input Output eDMA Enhanced Direct Memory Access controller eSCI Serial Communications Interface Fast Ethernet Controller FlexCAN Controller Area Network controller FlexRay- FlexRay Controller FMPLL Frequency Modulated Phase Locked Loop
Inter Controller Interrupt Controller Joint Test Action Group interface Media Local Device Interface Module Nexus Debug Interface Periodic Interrupt Timer Real Time Clock System Integration System Timer Module Software Watchdog Timer Voltage Regulator
Figure MPC5668G Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
MPC5668x Block Diagrams
Figure shows level block diagram MPC5668E device.
DEBUG JTAG Nexus3(Z6) Nexus2+(Z0)
MPC5668E
MASTERS e200z650 Core MMU(32TLB)
XTAL
4-40 XTAL
VREG Controller
FMPLL
RTC/API S
e200z0 Core
FPU/SPE Cache
Semaphores 32ChDMA
INTC
Crossbar Switch (XBAR) Memory Protection Unit (MPU)
AIPS(0) Bridge Flash (ECC) ECSM LEGEND
DSPI ECSM eDMA eMIOS200 eSCI FlexCAN FMPLL Analog Digital Converter Boot Assist Module Cross Triggering Unit Serial Peripherals Interface controller Error Correction Code Error Correction Status Module Enhanced Direct Memory Access controller Timed Input Output Serial Communications Interface Controller Area Network controller Frequency Modulated Phase Locked Loop
AIPS(1) Bridge eSCI DSPI SRAM (ECC) Standby ECSM
FlexCAN DSPI
eMIOS eSCI
INTC JTAG SSWT VREG
Inter Controller Interrupt Controller Joint Test Action Group interface Memory Protection Unit Nexus Debug Interface Periodic Interrupt Timer Real Time Clock System Integration System Timer Module Software Watchdog Timer Voltage Regulator
Figure MPC5668E Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Assignments
Assignments
208-ball MAPBGA Assignments
PD11 PD13 PF10 PD10 PD12 PD14 PD15 PC12 PC11 PC14 PC10 PC13 PC15 VDDE1 PB13 PB14 PB10 PB11 PB15 PB12 PA14 PA15 PG11 PG12 PG13 PG14 PG15
Figure shows 208-ball MAPBGA assignments.
RESET VDDSYN XTAL EXTAL VSSSYN VRCCTL PA10 PA11 PA13 VRCSEL VDDE3 VDD33 TEST PJ10 PJ11 PJ12 PJ13 PF15 PJ14 PJ15 PA12
VDDA VSSA PG10
MAPBGA Ball
viewed from through package)
PF13 PF12 PF14
JCOMP VDDEMLB PE10 PF11 VDDE2 PE11 PE12 PE13
Note: This ballmap preliminary should used board design.
PE15 PK10 PE14 PH10 PH11 PH12 VDDE4 PH13 PH15 PH14
Figure MPC5668x 208-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Assignments
256-ball MAPBGA Assignments
MAPBGA Ball
viewed from through package)
PD11 PD13 PF10 PD10 PD12 PD14 PD15 PC12 PC11 PC14 PC10 PC13 PC15 VDDE1 VDDENEX PB13 PB14 PB10 PB11 PB15
Figure shows 256-ball MAPBGA assignments.
PB12
PA14 PA15 PG11 PG12 PG13 PG14 PG15
RESET VDDSYN XTAL VRCCTL EVTO PJ10 PJ11 PJ12 PJ13 PA10 PA11 PA13 VRCSEL VDDE3 VDD33 TEST PF15 PJ14 PJ15
EXTAL VSSSYN PA12
VDDA VSSA PG10
MDO0 VDDENEX MDO1 MDO2
MDO3 MDO4 MDO6 MDO5
PF13 PF12 PF14
JCOMP VDDEMLB MDO7 PE10 PF11 VDDE2 MDO8 PE11 PE12
VDDENEX EVTI PH15
MDO9 MDO10 MDO11 MSEO1 MSEO0 MCKO PE13 PE15 PE14 PH11 VDDE4
Note: This ballmap PH12 PH13 preliminary PK10 PH10 PH14 should used board design.
Figure MPC5668x 256-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Assignments
Muxing Reset States
Table shows signals properties each MPC5668x. port pins that have associated SIU_PCRn register control properties, supported functions column lists functions associated with programming SIU_PCRn[PA] order: general-purpose input/output (GPIO), function function function (see Figure When alternate function implemented value SIU_PCRn[PA], dash shown Description column respective value bitfield reserved.
GPIO Supported (PCR) Functions Num3 PA[0] AN[0] Description Port Analog Input GPIO Function Functions implemented
Figure Supported Functions Example
Table MPC5668x Signal Properties
GPIO Supported (PCR) Functions Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port (16) PA[0] AN[0] Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input VDDA
PA[1] AN[1]
VDDA
PA[2] AN[2]
VDDA
PA[3] AN[3]
VDDA
PA[4] AN[4]
VDDA
PA[5] AN[5]
VDDA
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PA[6] AN[6] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input Port Analog Input External Crystal Port Analog Input External Crystal
VDDA
PA[7] AN[7]
VDDA
PA[8] AN[8]
VDDA
PA[9] AN[9]
VDDA
PA10
PA[10] AN[10]
VDDA
PA11
PA[11] AN[11]
VDDA
PA12
PA[12] AN[12]
VDDA
PA13
PA[13] AN[13]
VDDA
PA14
PA[14] AN[14] EXTAL32 PA[15] AN[15] XTAL32
VDDA
PA15
VDDA
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port (16) PB[0] AN[16]/ANW Port GPIO Analog Input/Mux Port GPIO Analog Input/Mux Port GPIO Analog Input/Mux Port GPIO Analog Input/Mux Port GPIO Analog Input Port GPIO Analog Input Port GPIO Analog Input Port GPIO Analog Input Port GPIO Analog Input DSPI_A Peripheral Chip Select Port GPIO Analog Input DSPI_A Peripheral Chip Select VDDE1
PB[1] AN[17]/ANX
VDDE1
PB[2] AN[18]/ANY
VDDE1
PB[3] AN[19]/ANZ
VDDE1
PB[4] AN[20]
VDDE1
PB[5] AN[21]
VDDE1
PB[6] AN[22]
VDDE1
PB[7] AN[23]
VDDE1
PB[8] AN[24] PCS_A[2] PB[9] AN[25] PCS_A[3]
VDDE1
VDDE1
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PB[10] AN[26] PCS_B[4] PB[11] AN[27] PCS_B[5] PB[12] AN[28] PCS_C[1] PB[13] AN[29] PCS_C[2] PB[14] AN[30] PCS_D[3] PB[15] AN[31] PCS_D[4] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
PB10
Port GPIO Analog Input DSPI_B Peripheral Chip Select Port GPIO Analog Input DSPI_B Peripheral Chip Select Port GPIO Analog Input DSPI_C Peripheral Chip Select Port GPIO Analog Input DSPI_C Peripheral Chip Select Port GPIO Analog Input DSPI_D Peripheral Chip Select Port GPIO Analog Input DSPI_D Peripheral Chip Select Port (16)
VDDE1
PB11
VDDE1
PB12
VDDE1
PB13
VDDE1
PB14
VDDE1
PB15
VDDE1
PC[0] AN[32]
Port GPIO Analog Input Port GPIO Analog Input Port GPIO Analog Input Nexus Event Port GPIO Analog Input Nexus Event
VDDE1
PC[1] AN[33]
VDDE1
PC[2] AN[34] EVTI PC[3] AN[35] EVTO
VDDE1
VDDE1
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PC[4] AN[36] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO Analog Input Port GPIO Analog Input Core Non-Maskable Interrupt Port GPIO Analog Input Core Non-Maskable Interrupt Port GPIO Analog Input FlexRay Debug Port GPIO Analog Input FlexRay Debug Port GPIO Analog Input FlexRay Debug Port GPIO Analog Input FlexRay Debug Port GPIO Analog Input I2C_C Serial Clock Port GPIO Analog Input I2C_C Serial Data Port GPIO Analog Input Ext. Address Select Port GPIO Analog Input Ext. Address Select
VDDE1
PC[5] AN[37] Z6NMI PC[6] AN[38] Z0NMI PC[7] AN[39] FR_DBG3 PC[8] AN[40] FR_DBG2 PC[9] AN[41] FR_DBG1 PC[10] AN[42] FR_DBG0 PC[11] AN[43] SCL_C PC[12] AN[44] SDA_C PC[13] AN[45] MA[0] PC[14] AN[46] MA[1]
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
PC10
VDDE1
PC11
VDDE1
PC12
VDDE1
PC13
VDDE1
PC14
VDDE1
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PC[15] AN[47] MA[2] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
PC15
Port GPIO Analog Input Ext. Address Select Port (16)
VDDE1
PD[0] CNTX_A
Port GPIO FlexCAN_A Transmit Port GPIO FlexCAN_A Receive Port GPIO FlexCAN_B Transmit Port GPIO FlexCAN_B Receive Port GPIO FlexCAN_C Transmit Port GPIO FlexCAN_C Receive Port GPIO FlexCAN_D Transmit SCI_K Transmit I2C_B Serial Clock Port GPIO FlexCAN_D Receive SCI_K Receive I2C_B Serial Data Port GPIO FlexCAN_E Transmit SCI_L Transmit I2C_C Serial Clock
VDDE2
PD[1] CNRX_A
VDDE2
PD[2] CNTX_B
VDDE2
PD[3] CNRX_B
VDDE2
PD[4] CNTX_C
VDDE2
PD[5] CNRX_C
VDDE2
PD[6] CNTX_D TXD_K SCL_B PD[7] CNRX_D RXD_K SDA_B PD[8] CNTX_E TXD_L SCL_C
VDDE2
VDDE2
VDDE2
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PD[9] CNRX_E RXD_L SDA_C PD[10] CNTX_F TXD_M SCL_D PD[11] CNRX_F RXD_M SDA_D PD[12] TXD_A Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO FlexCAN_E Receive SCI_L Receive I2C_C Serial Data Port GPIO FlexCAN_F Transmit SCI_M Transmit I2C_D Serial Clock Port GPIO FlexCAN_F Receive SCI_M Receive I2C_D Serial Data Port GPIO eSCI_A Transmit Port GPIO eSCI_A Receive Port GPIO eSCI_B Transmit Port GPIO eSCI_B Receive Port (16)
VDDE2
PD10
VDDE2
PD11
VDDE2
PD12
VDDE2
PD13
PD[13] RXD_A
VDDE2
PD14
PD[14] TXD_B
VDDE2
PD15
PD[15] RXD_B
VDDE2
PE[0] TXD_C eMIOS[31] PE[1] RXD_C eMIOS[30] PE[2] TXD_D eMIOS[29]
Port GPIO eSCI_C Transmit eMIOS Channel Port GPIO eSCI_C Receive eMIOS Channel Port GPIO eSCI_D Transmit eMIOS Channel
VDDE2
VDDE2
VDDE2
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PE[3] RXD_D eMIOS[28] PE[4] TXD_E eMIOS[27] PE[5] RXD_E eMIOS[26] PE[6] TXD_F eMIOS[25] PE[7] RXD_F eMIOS[24] PE[8] TXD_G PCS_A[1] PE[9] RXD_G PCS_A[4] PE[10] TXD_H PCS_B[3] PE[11] RXD_H PCS_B[2] PE[12] TXD_J PCS_C[5] PE[13] RXD_J PCS_C[3] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO eSCI_D Receive eMIOS Channel Port GPIO eSCI_E Transmit eMIOS Channel Port GPIO eSCI_E Receive eMIOS Channel Port GPIO eSCI_F Transmit eMIOS Channel Port GPIO eSCI_F Receive eMIOS Channel Port GPIO eSCI_G Transmit DSPI_A Peripheral Chip Select Port GPIO eSCI_G Receive DSPI_A Peripheral Chip Select Port GPIO eSCI_H Transmit DSPI_B Peripheral Chip Select Port GPIO eSCI_H Receive DSPI_B Peripheral Chip Select Port GPIO eSCI_J Transmit DSPI_C Peripheral Chip Select Port GPIO eSCI_J Receive DSPI_C Peripheral Chip Select
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
PE10
VDDE2
PE11
VDDE2
PE12
VDDE2
PE13
VDDE2
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PE[14] SCL_A PCS_D[2] PE[15] SDA_A PCS_D[5] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
PE14
Port GPIO I2C_A Serial Clock DSPI_D Peripheral Chip Select Port GPIO I2C_A Serial Data DSPI_D Peripheral Chip Select Port (16)
VDDE2
PE15
VDDE2
PF[0] SCK_A
Port GPIO DSPI_A Serial Clock Port GPIO DSPI_A Serial Data Port GPIO DSPI_A Serial Data Port GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO DSPI_B Serial Clock DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO DSPI_B Serial Data DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO DSPI_B Serial Data DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select DSPI_D Peripheral Chip Select
VDDE2
PF[1] SOUT_A
VDDE2
PF[2] SIN_A
VDDE2
PF[3] PCS_A[0] PCS_B[5] PCS_C[4] PF[4] SCK_B PCS_A[1] PCS_C[2] PF[5] SOUT_B PCS_A[2] PCS_C[3] PF[6] SIN_B PCS_A[3] PCS_C[5] PF[7] PCS_B[0] PCS_C[5] PCS_D[4]
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PF[8] SCK_C Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO DSPI_C Serial Clock Port GPIO DSPI_C Serial Data Port GPIO DSPI_C Serial Data Port GPIO DSPI_C Peripheral Chip Select DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select Port GPIO DSPI_D Serial Clock Port GPIO DSPI_D Serial Data Port GPIO DSPI_D Serial Data Port GPIO DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select Port (16)
VDDE2
PF[9] SOUT_C
VDDE2
PF10
PF[10] SIN_C
VDDE2
PF11
PF[11] PCS_C[0] PCS_D[5] PCS_A[4] PF[12] SCK_D
VDDE2
PF12
VDDE3
PF13
PF[13] SOUT_D
VDDE3
PF14
PF[14] SIN_D
VDDE3
PF15
PF[15] PCS_D[0] PCS_A[5] PCS_B[4]
VDDE3
PG[0] PCS_A[4] PCS_B[3] AN[48] PG[1] PCS_A[5] PCS_B[4] AN[49]
Port GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select Analog Input Port GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select Analog Input
VDDE2
VDDE2
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PG[2] PCS_D[1] SCL_C AN[50] PG[3] PCS_D[2] SDA_C AN[51] PG[4] PCS_D[3] SCL_B AN[52] PG[5] PCS_D[4] SDA_B AN[53] PG[6] PCS_C[1] FEC_MDC AN[54] PG[7] PCS_C[2] FEC_MDIO AN[55] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO DSPI_D Peripheral Chip Select I2C_C Serial Clock Analog Input Port GPIO DSPI_D Peripheral Chip Select I2C_C Serial Data Analog Input Port GPIO DSPI_D Peripheral Chip Select I2C_B Serial Clock Analog Input Port GPIO DSPI_D Peripheral Chip Select I2C_C Serial Data Analog Input Port GPIO DSPI_C Peripheral Chip Select Ethernet Mgmt. Data Clock Analog Input Port GPIO DSPI_C Peripheral Chip Select Ethernet Mgmt. Data Analog Input Port GPIO eMIOS Channel Ethernet Transmit Clock Analog Input Port GPIO eMIOS Channel Ethernet Carrier Sense Analog Input Port GPIO eMIOS Channel Ethernet Transmit Error Analog Input Port GPIO eMIOS Channel Ethernet Receive Clock Analog Input Port GPIO eMIOS Channel Ethernet Transmit Data Analog Input
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
PG[8] eMIOS[7] FEC_TX_CLK AN[56] PG[9] eMIOS[6] FEC_CRS AN[57]
VDDE3
VDDE3
PG10
PG[10] eMIOS[5] FEC_TX_ER AN[58] PG[11] eMIOS[4] FEC_RX_CLK AN[59] PG[12] eMIOS[3] FEC_TXD[0] AN[60]
VDDE3
PG11
VDDE3
PG12
VDDE3
MPC5668x Microcontroller Data Sheet, Rev. Preliminary-Subject Change Without Notice Freescale Semiconductor
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PG[13] eMIOS[2] FEC_TXD[1] AN[61] PG[14] eMIOS[1] FEC_TXD[2] AN[62] PG[15] eMIOS[0] FEC_TXD[3] AN[63] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
PG13
Port GPIO eMIOS Channel Ethernet Transmit Data Analog Input Port GPIO eMIOS Channel Ethernet Transmit Data Analog Input Port GPIO eMIOS Channel Ethernet Transmit Data Analog Input Port (16)
VDDE3
PG14
VDDE3
PG15
VDDE3
PH[0] eMIOS[31] FEC_COL
Port GPIO eMIOS Channel Ethernet Collision Port GPIO eMIOS Channel Ethernet Receive Data Valid Port GPIO eMIOS Channel Ethernet Transmit Enable Port GPIO eMIOS Channel Ethernet Receive Error Port GPIO eMIOS Channel Ethernet Receive Data Port GPIO eMIOS Channel Ethernet Receive Data Port GPIO eMIOS Channel Ethernet Receive Data
VDDE3
PH[1] eMIOS[30] FEC_RX_DV PH[2] eMIOS[29] FEC_TX_EN PH[3] eMIOS[28] FEC_RX_ER PH[4] eMIOS[27] FEC_RXD[0] PH[5] eMIOS[26] FEC_RXD[1] PH[6] eMIOS[25] FEC_RXD[2]
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PH[7] eMIOS[24] FEC_RXD[3] PH[8] eMIOS[23] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO eMIOS Channel Ethernet Receive Data Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port (16)
VDDE3
VDDE4
PH[9] eMIOS[22]
VDDE4
PH10
PH[10] eMIOS[21]
VDDE4
PH11
PH[11] eMIOS[20]
VDDE4
PH12
PH[12] eMIOS[19]
VDDE4
PH13
PH[13] eMIOS[18]
VDDE4
PH14
PH[14] eMIOS[17]
VDDE4
PH15
PH[15] eMIOS[16]
VDDE4
PJ[0] eMIOS[15] PCS_A[4]
Port GPIO eMIOS Channel DSPI_A Peripheral Chip Select
VDDE4
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PJ[1] eMIOS[14] PCS_A[5] PJ[2] eMIOS[13] PCS_B[1] PJ[3] eMIOS[12] PCS_B[2] PJ[4] eMIOS[11] PCS_C[3] PJ[5] eMIOS[10] PCS_C[4] PJ[6] eMIOS[09] PCS_D[5] PJ[7] eMIOS[08] PCS_D[1] PJ[8] eMIOS[07] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO eMIOS Channel DSPI_A Peripheral Chip Select Port GPIO eMIOS Channel DSPI_B Peripheral Chip Select Port GPIO eMIOS Channel DSPI_B Peripheral Chip Select Port GPIO eMIOS Channel DSPI_C Peripheral Chip Select Port GPIO eMIOS Channel DSPI_C Peripheral Chip Select Port GPIO eMIOS Channel DSPI_D Peripheral Chip Select Port GPIO eMIOS Channel DSPI_D Peripheral Chip Select Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel
VDDE4
VDDE4
VDDE4
VDDE4
VDDE4
VDDE4
VDDE4
VDDE4
PJ[9] eMIOS[06]
VDDE4
PJ10
PJ[10] eMIOS[05]
VDDE4
PJ11
PJ[11] eMIOS[04]
VDDE4
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PJ[12] eMIOS[03] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
PJ12
Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port GPIO eMIOS Channel Port (11)
VDDE4
PJ13
PJ[13] eMIOS[02]
VDDE4
PJ14
PJ[14] eMIOS[01]
VDDE4
PJ15
PJ[15] eMIOS[00]
VDDE4
PK[0] MLBCLK SCK_B CLKOUT PK[1] MLBSIG SOUT_B PCS_D[4] PK[2] MLBDAT SIN_B PCS_D[5] PK[3] FR_A_RX MA[0] PCS_C[1] PK[4] FR_A_TX MA[1] PCS_C[2]
Port GPIO Media Local Clock DSPI_B Serial Clock CLKOUT (Test Only) Port GPIO Media Local Signal DSPI_B Serial Data DSPI_D Peripheral Chip Select Port GPIO Media Local Data DSPI_B Serial Data DSPI_D Peripheral Chip Select Port GPIO FlexRay Receive Data Ext. Address Select DSPI_C Peripheral Chip Select Port GPIO FlexRay Transmit Data Ext. Address Select DSPI_C Peripheral Chip Select Port GPIO FlexRay Transmit Enable Ext. Address Select DSPI_C Peripheral Chip Select
VDDEMLB
VDDEMLB
VDDEMLB
VDDE2
VDDE2
PK[5] FR_A_TX_EN MA[2] PCS_C[3]
VDDE2
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 PK[6] FR_B_RX PCS_B[1] PCS_C[4] PK[7] FR_B_TX PCS_B[2] PCS_C[5] Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
Port GPIO FlexRay Receive Data DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO FlexRay Transmit Data DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port GPIO FlexRay Transmit Enable DSPI_B Peripheral Chip Select DSPI_A Peripheral Chip Select Port GPIO CLKOUT (User mode) DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select Boot Configuration Port GPIO DSPI_B Peripheral Chip Select DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select
VDDE2
VDDE2
PK[8] FR_B_TX_EN PCS_B[3] PCS_A[1] PK[9] CLKOUT PCS_D[1] PCS_A[2] BOOTCFG PK[10] PCS_B[5] PCS_D[2] PCS_A[3]
VDDE2
VDDE2
BOOT GPIO (Pulldown)
PK10
VDDE2
Nexus Pins (17) EVTI EVTO EVTI EVTO Nexus Event Nexus Event Nexus Message Start/End Nexus Message Start/End Nexus Message Clock Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data Nexus Message Data VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX
MSEO0 MSEO[0] MSEO1 MSEO[1] MCKO MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MDO8 MDO9 MCKO MDO[0] MDO[1] MDO[2] MDO[3] MDO[4] MDO[5] MDO[6] MDO[7] MDO[8] MDO[9]
MDO10 MDO[10]
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Assignments
Table MPC5668x Signal Properties (continued)
GPIO Supported (PCR) Functions Num3 Status Description Type Voltage Type5 During Reset6 After Reset7 Package Locations
Name1
MDO11 MDO[11]
Nexus Message Data
VDDENEX
Miscellaneous Pins EXTAL XTAL EXTAL EXTCLK XTAL Main Crystal Oscillator Input External Clock Input Main Crystal Oscillator Output JTAG Test Data Input JTAG Test Data Output JTAG Test Mode Select Input JTAG Test Clock Input JTAG Compliancy Test Mode Select External Reset VDDSYN VDDSYN VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE3 VDDE1 EXTAL XTAL (Pull (Pull Up8) (Pull (Pull Down)
JCOMP (Pull Down)
JCOMP JCOMP TEST TEST
TEST9 RESET (Pull
RESET RESET
primary signal name used label identification purposes. Each line Signal Name column corresponds separate signal function pin. device pins, primary, alternate, GPIO signal functions designated field System Integration Unit (SIU) registers except where explicitly noted. GPIO number same corresponding configuration register (SIU_PCRn) number. bitfield SIU_PCRn register selects signal function pin. dash Description field this table indicates that this value reserved this pin, should used. type indicated more following abbreviations: A-analog, F-fast speed, H-high voltage, I-input-only, M-medium speed, S-slow speed. example, type designates slow high-voltage pad. Status During Reset sampled after internal negated. Prior exiting POR, signal high impedance. terminology used this column output, input, weak pull enabled, Down weak pulldown enabled, output driven low, High output driven high. dash left side slash denotes that both input output buffers off. dash right side slash denotes that there weak pull up/down enabled pin. signal name left right slash indicates enabled. Function After Reset function general purpose input. dash left side slash denotes that both input output buffers off. dash right side slash denotes that there weak pull up/down enabled pin. Pullup enabled only when JCOMP negated. normal operation.
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Assignments
3.3.1
Power Ground Supply Summary
Table MPC5668x Power/Ground
Package Locations Internal Logic Power External Power 3.3-5.0 D10, G13, K13, Analog Power Power Media Local Power Nexus Power Voltage Regulator Select Voltage Regulator Control Voltage Voltage Regulator Control Output Clock Synthesizer Power Analog High Voltage Reference Analog Voltage Reference Ground 3.3-5.0 VSSA VDDA 3.3-5.0
Name VDDE1 VDDE2 VDDE3 VDDE4 VDDA VDD33 VDDEMLB VDDENEX2 VRCSEL VRCCTL VDDSYN
Function Description
Voltage1
D10, G13, K13, K11,
3.3-5.0
A16, G[7:10], A16, E[7:12], F[7:12], H[7:10], J[7:10], K[7:10], N13, G[6:12], H[7:12], J[7:12], K[6:10], K12, L[8:10], L12, N13,
VSSA VSSSYN
Analog Ground Clock Synthesizer Ground
Nominal voltages. Dedicated Nexus power 256-pin package only. 208-pin package, VDDENEX tied internal package substrate available externally. Base current external power transistor. Voltage vary.
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Electrical Characteristics
Electrical Characteristics
NOTE
electrical specifications preliminary from previous designs design simulations. These specifications fully tested guaranteed this early stage product life cycle, however production silicon finalized specifications will met. Finalized specifications will published after complete characterization device qualifications have been completed.
This section contains detailed information power considerations, DC/AC electrical characteristics, timing specifications MPC5668x.
Spec
Maximum Ratings
Table Absolute Maximum Ratings1
Characteristic Core Supply Voltage Clock Synthesizer Voltage Buffer Voltage 3.3-5.0 Voltage Regulator Control Voltage 3.3-5.0 Analog Supply Voltage (reference VSSA) 3.3-5.0 External Supply Voltage4 VDDE15 VDDE25 VDDE35 VDDE45 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.07 -1.06 -0.3 VDDEx VDDEx Minimum VDDA 150.0 235.0 Symbol VDDSYN VDD33 VDDA -0.3 -0.3 -0.3 -0.3 -0.3 Max2 1.323 Unit
2.5-3.3 External Supply Voltage (MLB) External Supply Voltage (Nexus) Input VDDE1, VDDE2, VDDE3, VDDE4 VDDEMLB, VDDENEX Analog Reference High Voltage Voltage6
VDDEMLB5 VDDENEX5
Analog Reference Voltage VSSA Differential Voltage VSSSYN Differential Voltage Maximum Digital Input digital pins) Current9 (per pin, applies
VSSA VSSSYN IMAXD IMAXA TSTG
-0.3 -100 -100 -55.0
Maximum Analog Input Current10 (per pin, applies analog pins) Storage Temperature Range Maximum Solder Temperature Moisture Sensitivity Level12
TSDR
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Electrical Characteristics
Functional operating conditions given electrical specifications. Absolute maximum ratings stress ratings only, functional operation maxima guaranteed. Stress beyond listed maxima affect device reliability cause permanent damage device. Absolute maximum specifications device stress have been determined. hours cumulative time, +10% time remaining. functional non-supply pins clamped VDDEx. VDDEx separate power segments powered independently with differential voltage constraints between power segments. signal over undershoot input voltages ±2.0 permitted cumulative duration hours over complete lifetime device (injection current does need limited this duration). Internal structures will hold input voltage above -1.0 injection current limit met. Internal structures hold input voltage below this maximum voltage pads powered VDDE supplies, maximum injection current specification pins) VDDE within Operating Voltage specifications. Total injection current pins (including both digital analog) must exceed Total injection current analog input pins must exceed Solder profile CDF-AEC-Q100. Moisture sensitivity JEDEC test method A112.
Thermal Characteristics
Table Thermal Characteristics
Value
Spec
Characteristic Junction Ambient Natural Convection (Single layer board)
Symbol
Unit MAPBGA °C/W MAPBGA
Junction Ambient1, Natural Convection (Four layer board 2s2p) Junction Ambient1, (@200 ft./min., Single layer board) Junction Ambient1, (@200 ft./min., Four layer board 2s2p) Junction Board4 Junction Case
°C/W
RJMA RJMA
°C/W °C/W °C/W °C/W °C/W
Junction Package Natural Convection
Top6
Junction temperature function on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance. SEMI G38-87 JEDEC JESD51-2 with single layer board horizontal. JEDEC JESD51-6 with board horizontal. Thermal resistance between printed circuit board JEDEC JESD51-8. Board temperature measured surface board near package. Indicates average thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1) with cold plate temperature used case temperature. Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2. MPC5668x Microcontroller Data Sheet, Rev.
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Electrical Characteristics
4.2.1
General Notes Specifications Maximum Junction Temperature
(RJA Eqn.
estimation chip junction temperature, obtained from equation:
where: ambient temperature package (oC) junction ambient thermal resistance (oC/W) power dissipation package supplied thermal resistances provided based JEDEC JESD51 series standards provide consistent values estimations comparisons. difference between values determined single-layer (1s) board four-layer board with signal layers power ground plane (2s2p) clearly demonstrate that effective thermal resistance component constant. depends construction application board (number planes), effective size board which cools component, well component thermally electrically connected planes, power being dissipated adjacent components. Connect ground power balls respective planes with ball. Using fewer vias connect package planes reduces thermal performance. Thinner planes also reduce thermal performance. When clearance between through vias leave planes virtually disconnected, thermal performance also greatly reduced. general rule, value obtained single layer board appropriate tightly packed printed circuit board. value obtained board with internal planes usually appropriate application board micron nominal thickness) internal planes, components well separated, overall power dissipation board less than 0.02 W/cm2. thermal performance component depends strongly power dissipation surrounding components. addition, ambient temperature varies widely within application. many natural convection especially closed applications, board temperature perimeter (edge) package approximately same local temperature near device. Specifying local ambient conditions explicitly board temperature provides more precise description local ambient conditions that determine temperature device. known board temperature, junction temperature estimated using following equation: (RJB where: junction temperature (oC) board temperature package perimeter (oC/W) junction board thermal resistance (oC/W) JESD51-8 power dissipation package When heat loss from package case ignored, acceptable predictions junction temperature made. application board should similar thermal test condition, with component soldered board with internal planes. Historically, thermal resistance frequently been expressed junction case thermal resistance case ambient thermal resistance: where: junction ambient thermal resistance (oC/W)
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Eqn.
Eqn.
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Electrical Characteristics
junction case thermal resistance (oC/W) case ambient thermal resistance (oC/W) device related cannot influenced user. user controls thermal environment change case ambient thermal resistance, RCA. instance, user change flow around device, heat sink, change mounting arrangement printed circuit board, change thermal dissipation printed circuit board surrounding device. This description most useful packages with heat sinks where some heat flow through case heat sink ambient. most packages, better model required. more accurate two-resistor thermal model constructed from junction board thermal resistance junction case thermal resistance. junction case covers situation where heat sink will used where substantial amount heat dissipated from package. junction board thermal resistance describes thermal performance when most heat conducted printed circuit board. This model used either hand estimations computational fluid dynamics (CFD) thermal model. determine junction temperature device application after prototypes available, Thermal Characterization Parameter (JT) used determine junction temperature with measurement temperature center package case using following equation: where: thermocouple temperature package (oC) thermal characterization parameter (oC/W) power dissipation package thermal characterization parameter measured JESD51-2 specification using 40-gauge type thermocouple epoxied center package case. thermocouple should positioned that thermocouple junction rests package. small amount epoxy placed over thermocouple junction over about wire extending from junction. thermocouple wire placed flat against package case avoid measurement errors caused cooling effects thermocouple wire. Eqn.
References:
Semiconductor Equipment Materials International 3081 Zanker Road Jose, 95134 (408) 943-6900 MIL-SPEC EIA/JESD (JEDEC) specifications available from Global Engineering Documents 800-854-7179 303-397-7956. JEDEC specifications available http://www.jedec.org. C.E. Triplett Joiner, Experimental Characterization PBGA Within Automotive Engine Controller Module," Proceedings SemiTherm, Diego, 1998, 47-54. Kromann, Shidore, Addison, "Thermal Modeling PBGA Air-Cooled Applications," Electronic Packaging Production, 53-58, March 1998. Joiner Adams, "Measurement Simulation Junction Board Thermal Resistance Application Thermal Modeling," Proceedings SemiTherm, Diego, 1999, 212-220.
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Electrical Characteristics
Characteristics
Table Ratings1,
Characteristic Symbol Value 2000 1500 (corner pins) (all other pins) Unit
Human Body Model (HBM) Circuit Description
Field Induced Charge Model (FDCM)
Number Pulses pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval Pulses
second
testing conformity with CDF-AEC-Q100 Stress Test Qualification Automotive Grade Integrated Circuits. device will defined failure after exposure pulses device longer meets device specification requirements. Complete parametric functional testing shall performed applicable device specification room temperature followed temperature, unless specified otherwise device specification.
Spec
Electrical Specifications
Table Electrical Specifications Characteristic
Current which sourced VRCCTL Minimum Required Gain from external circuit: I_VRCCTL (@VDD 1.32 -40°C 25°C 150°C
Symbol
I_VRCCTL
6.25
Units
BETA
Assumes "typical usage" currents which will vary with application.
Spec
Electrical Specifications
Table Electrical Specifications
Characteristic Maximum Operating Temperature Range Junction Temperature Clock Synthesizer Voltage1 Buffer Voltage1 Symbol VDDSYN VDD33 VVRC VDDA maximum VVRC 5.52, -40.0 150.0 3.62, 3.62, Unit
3.3-5.0 Voltage Regulator Reference Voltage1 VRCSEL VSSA VRCSEL VDDA 3.3-5.0 Analog Supply Voltage
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Electrical Characteristics
Table Electrical Specifications
Spec Characteristic 3.3-5.0 External Supply Voltage5 VDDE1 VDDE22 VDDE32 VDDE42 External Supply Voltage (MLB) External Supply Voltage (Nexus) Input High Voltage Hysteresis enabled Hysteresis disabled (IHA/SH/SHA/MH/MHA)6, Hysteresis disabled Input Voltage Hysteresis enabled Hysteresis disabled (IHA/SH/SHA/MH/MHA)6, Hysteresis disabled Input Hysteresis Analog (IHA) Input Voltage Output High Voltage8, Output Voltage1, Input Capacitance (Digital Pins: type SH)6 Input Capacitance (Analog Pins: type IHA)6, Input Capacitance (Shared digital/analog pins: MHA, SHA)6 Weak Pull Up/Down Absolute Current6, 2.375 SH/MH/IHA: SH/MH/IHA: Input Leakage Current12 Injection Current (per pin) Analog Input Current, Channel Off13 (Analog pins IHA)6, Analog Reference High Voltage Analog Reference Voltage VSSA Differential Voltage VSSSYN Differential Voltage Slew rate VDDA, VDDEx, VDDR power supply pins Capacitive Supply Load (VDD) Capacitive Supply Load (VDD33, VDDSYN) VDDEMLB2 VDDENEX2 2.375 0.65 VDDE 0.55 VDDE 0.55 VDDE 5.52, 5.52,5 5.52, 5.52, 3.61, 3.61, VDDE Symbol Unit
0.35 VDDE 0.40 VDDE 0.40 VDDE
VHYS VINDC CIN_A CIN_M IACT
VDDE VSSA VDDE VDDA VDDE VDDA VSSA
IINACT_D IINACT_A VSSA VSSSYN VRamp VLoad VLoad
-2.5 -1.0 -150 VDDA VSSA -100 -100
V/ms
When VRCSEL VSSA (low), VDDSYN VDD33 externally supplied. When VRCSEL VDDA (high), VDDSYN VDD33 generated internal voltage regulators. When VRCSEL VSSA (low), VDDSYN VDD33 cannot higher than VRC.
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Electrical Characteristics
Voltage overshoots during high-to-low low-to-high transition must exceed seconds instance. hours cumulative time, +10% time remaining. hours cumulative time, +10% time remaining. VDDE1 VDDE4 separate power segments powered independently with differential voltage constraints between power segments. VDDE1 VDDE3 power segments contain analog input channels thus input analog signal level clamped VDDE level, resulting inaccurate results VDDE voltage level less than VDDA. type indicated more following abbreviations: A-analog, F-fast speed, H-high voltage, I-input-only, M-medium speed, S-slow speed. example, type designates slow high-voltage pad. pads related VDDA. Characterization Based Capability: IOH_F {12, IOL_F {24, {00, 01,10, drive mode with VDDE IOH_F IOL_F {18, {00, drive mode with VDDE 2.25 IOH_F IOL_F {12, {00, drive mode with VDDE 1.62 Characterization Based Capability: IOH_S 11.6} IOL_S {9.2, 17.7} {slow, medium} with VDDEH IOH_S {2.8, 5.4} IOL_S {4.2, 8.1} {slow, medium} with VDDEH values 100% tested with load. Absolute value current, measured Weak pull up/down inactive. Measured 5.25 Applies types: pad_sh, pad_mh. Maximum leakage occurs maximum operating temperature. Leakage current decreases approximately one-half each ambient temperature range Applies types: pad_a pad_ae.
Operating Current Specifications
Table Operating Currents
Typ1 Ambient
Spec
Characteristic
Symbol
Max1 -40-150 Junction
Unit
Equations ITOTAL IDDE IDDA IDD33 IDDSYN IDDE IDDE1 IDDE2 IDDE3 IDDE4 IDDEMLB VDDE Current VDDE(1,2,3,4) VDDEMLB 2.375 Static2 Dynamic3 VDDA Current VDDA mode Sleep mode Optional enabled Current mode Sleep mode VDD33 Current VDD33 mode Sleep mode
IDDE
Note IDDA IDD33
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Electrical Characteristics
Table Operating Currents (continued)
Spec Characteristic VDDSYN Current VDD33 mode Sleep mode Optional4 4-40 enabled clock Optional4 4-40 enabled clock Current 3.135 mode Sleep mode Optional4 16MIRC enabled Current 1.08 1.32 mode (Maximum MHz) Sleep mode Optional4 128KIRC enabled Optional4 16MIRC enabled Optional4 enabled Optional4 4-40 enabled clock Optional4 4-40 enabled clock Optional4 Optional4 Optional4 Typ1 Symbol Ambient IDDSYN +150 +300 +200 +150 +220 +200 +150 +300 +600 +350 +400 Max1 -40-150 Junction Unit
Nominal voltage levels functional activity. Maximum voltage levels functional activity. Static state pins when input pins disabled being toggled driven valid input level, output pins toggling driving against current loads, internal pull devices disabled pulling against current loads. Dynamic current from pins application-specific depends active pull devices, switching outputs, output capacitive current loads, switching inputs. Refer Table more information. Optional currents values that should added their respective current specifications obtain actual value that specification when optional function active. plus sign columns indicates these optional currents. example, VDDSYN Sleep mode draws (typ). With optional 4-40 enabled clock, total (typ).
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Electrical Characteristics
Current Specifications
power consumption segment depends usage pins particular segment. power consumption output currents particular segment. output current calculated from Table based voltage, frequency, load pin. linear scaling calculate currents voltage, frequency, load parameters that fall outside values given Table Table Average IDDE Specifications1
Spec Fast
Type2
Symbol
Period (ns)
Load3 (pF)
VDDE 2.75 2.75 2.75 2.75
Drive/Slew Rate Select
IDDE (mA) 50.4 14.2 16.4 22.9
IDDE (mA) 101.6 57.3 43.6 15.9 45.3 25.3 17.3
Slow
IDRV_SSR_HV
Medium
IDRV_MSR_HV
IDRV_FC
Input
IDRV_I_HV
These typical values that estimated from simulation tested. Currents apply output pins only. Slow SHA; Medium MHA; Fast Input IHA. Table loads lumped.
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Electrical Characteristics
4.7.1
VDD33 Current Specifications
power consumption VDD33 supply dependent usage pins segments. power consumption input output VDD33 currents segments. output VDD33 current calculated from Table based voltage, frequency, load pins. input VDD33 current calculated from Table based voltage, frequency, load pins. linear scaling calculate currents voltage, frequency, load parameters that fall outside values given Table Table Average IDD33 Specifications1
Spec Slow Medium
Type2
Symbol
Period (ns)
Load3 (pF)
Drive Select
IDD33 (µA) 0.04 0.06 0.009 0.11 0.02 0.01
IDD33 (µA) 235.7 87.4 47.4 76.5 56.2 56.2
IDRV_SSR_HV
IDRV_MSR_HV
Input
IDRV_I_HV
These typical values that estimated from simulation tested. Currents apply output pins only. Slow SHA; Medium MHA; Fast Input IHA. Table loads lumped.
Table IDD33 Average Current1
Spec Fast
Type2
Symbol
Period (ns)
Load3 (pF)
VDD33
VDDE 2.75 2.75 2.75 2.75
Drive Select
IDD33 (µA) 3.32 2.28 1.73 1.39 1.64 1.37 1.06
IDD33 (µA) 11.77 7.07 5.75 4.77 7.81 4.96 4.31 4.09
IDRV_FC
These typical values that estimated from simulation tested. Currents apply output pins only. Slow SHA; Medium MHA; Fast Input IHA. Table loads lumped.
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Electrical Characteristics
Spec
Voltage Characteristics
Table Voltage Monitors
Characteristic Power-on-Reset Assert Level1 Voltage Monitor Assert Level De-assert Level Voltage Monitor Synthesizer3 Assert Level De-assert Level Voltage Monitor Threshold1 VRCSEL VSSA Assert Level De-assert Level VRCSEL VDDA Assert Level De-assert Level Voltage Monitor Assert Level De-assert Level Voltage Monitor High Threshold1, Assert Level De-assert Level Symbol VPOR VLVI33A VLVI33D VLVISYNA VLVISYND 3.00 3.04 3.00 3.04 Typical 3.05 3.12 3.05 3.12 3.10 3.19 3.10 3.19 VLVI_VDDA_LOA VLVI_VDDA_LOD VLVI_VDDA_LOA VLVI_VDDA_LOD VLVI_VDDA_A VLVI_VDDA_D VLVI_VDDA_HA VLVI_VDDA_HD 3.00 3.04 3.25 3.35 4.40 4.50 4.55 4.55 3.05 3.12 3.35 3.45 4.475 4.575 4.65 4.65 3.10 3.19 3.48 3.55 4.55 4.65 4.75 4.75 Unit
Monitors VDDA. Monitors VDD33. Monitors DDSYN. Disabled when RCSEL VSSA.
Spec
Oscillators Electrical Characteristics
Table High Frequency External Oscillator
Characteristic Frequency Range Duty Cycle reference EXTAL Input High Voltage External crystal mode2 External clock mode EXTAL Input Voltage External crystal mode3 External clock mode XTAL Current4 Total On-chip stray capacitance XTAL Total On-chip stray capacitance EXTAL Symbol fref VIHEXT VXTAL 0.65 VDDSYN VILEXT VDDSYN VDDSYN IXTAL CS_XTAL CS_EXTAL VXTAL 0.35 VDDSYN VDDSYN VDDSYN Unit
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Electrical Characteristics
Table High Frequency External Oscillator (continued)
Spec
Characteristic Crystal manufacturer's recommended capacitive load Discrete load capacitance connected EXTAL Discrete load capacitance connected XTAL Startup Time
Symbol CL_EXTAL CL_XTAL tstartup
crystal specification
crystal specification CS_EXTAL CPCB_EXTAL5 CS_XTAL
PCB_XTAL
Unit
When frequency modulation active, reference frequencies less than will distort modulated waveform effects this emissions characterized. This parameter meant those quartz crystals resonators, instead oscillators crystal mode. that case, Vextal Vxtal criteria oscillator's comparator produce output clock. This parameter meant those quartz crystals resonators, instead oscillators crystal mode. that case, Vxtal Vextal criteria oscillator's comparator produce output clock. Ixtal oscillator bias current XTAL with both EXTAL XTAL pins grounded. CPCB_EXTAL CPCB_XTAL measured stray capacitances EXTAL XTAL, respectively.
Table Frequency kHz) External Oscillator
Spec
Characteristic Frequency Range Duty Cycle reference XTAL32 Current1
Symbol fref32 tdc32 IXTAL32 CL32 tStartup
Min. crystal specification
crystal specification
Unit
Crystal manufacturer's recommended capacitive load Startup Time
Ixtal32 oscillator bias current XTAL32 with both EXTAL32 XTAL32 pins grounded.
Table High Frequency MHz) Internal Oscillator
Spec
Characteristic Frequency before trim1 Frequency after loading factory Application trim resolution3 step3 trim2
Symbol tStartup
Range
10.4 15.2
21.6 16.8 ±0.5
Unit
Application frequency trim Startup Time
Across process, voltage, temperature. Across voltage temperature. Fixed voltage temperature.
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Electrical Characteristics
Table Frequency (128 kHz) Internal Oscillator
Spec
Characteristic Frequency before trim
Symbol Fut128 trim2 Ft128 Ts128
Range
83.2 121.6
172.8 134.4
Unit
Frequency after loading factory Application trim resolution3
Application frequency trim step Startup Time
Fs128 St128
Across process, voltage, temperature. Across voltage temperature. Fixed voltage temperature.
4.10
Spec
FMPLL Electrical Characteristics
Table FMPLL Electrical Specifications1
Characteristic System Frequency2 Reference Frequency Range Frequency Symbol fSYS fREF fPLL ERFD -4.0 -2.0 2000 Unit
Loss Reference Frequency Self Clocked Mode Frequency Lock Time4 Duty Cycle Reference Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter,5 Measured fSYS Cycle-to-cycle Jitter CLKOUT Jitter period Peak-to-Peak Frequency Modulation Range Limit (fSYSMax must exceeded) Depth Tolerance8 Frequency9 Modulation Rate Limits10
fLOR fSCM tLPLL fLCK CJitter CJitter Cmod Cmod_err fVCO fMOD
fSYS fSYS %fSYS %fCLKOUT %fSYS %fSYS
-0.5 -0.50 0.400
0.50
VDDSYN VSSSYN
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Electrical Characteristics
maximum frequency value with frequency modulation disabled. frequency modulation enabled, maximuum frequency value should de-rated percentage modulation enabled that maximum frequency exceeded. "Loss Reference Frequency" reference frequency detected internally, which transitions into self clocked mode. This specification applies period required re-lock after changing frequency control bits synthesizer control register (SYNCR). From power with crystal oscillator reference, lock time will additive with crystal startup time. Values with frequency modulation disabled. frequency modulation enabled, jitter Cjitter Cmod. Modulation depth selected must result fPLL value greater than fPLL maximum specified value. Maximum minimum variations from programmed modulation depth peak-to-peak. only these settings. Depth tolerance programmed modulation depth ±0.25% fSYS. Initial design target pending silicon evaluation. Block Guide frequency synthesis equations. Modulation rates less than will result exceedingly long calibration durations. Modulation rates greater than will result reduced calibration accuracy.
4.11
Spec
Electrical Characteristics
Table Conversion Specifications (Operating)
Characteristic Analog High Reference Voltage Analog Reference Voltage Analog Input Voltage Sampling Frequency Maximum Clock Frequency Sampling Time VDDA VDDA Differential Linearity Integral Linearity Offset Error Gain Error Total Unadjusted Error
Symbol AVIN FMAX
VDDA
VDDA 1.53
Unit
-1.0 -1.5 -1.0 -2.0 -2.0
assumes activity pins adjacent analog channel output driver activity corresponding VDDE segment.
4.12
Spec
Flash Memory Electrical Characteristics
Table Flash Program Erase Specifications1
Characteristic Symbol tdwprogram Time4 tpprogram t16kpperase t64kpperase Initial Max2 1000 1800 2600 Max3 5000 5000 7500 Unit
Double Word bits) Program Time4 Page (128 bits bits) Program
Block Pre-program Erase Time Block Pre-program Erase Time Block Pre-program Erase Time
t128kpperase
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Electrical Characteristics
Table Flash Program Erase Specifications1 (continued)
Spec Characteristic Block Pre-program Erase Time Wait States Relative System PFCRPn[RWSC] PFCRPn[APC] 0b000; PFCRPn[WWSC] 0b01 PFCRPn[RWSC] PFCRPn[APC] 0b001; PFCRPn[WWSC] 0b01 PFCRPn[RWSC] PFCRPn[APC] 0b010; PFCRPn[WWSC] 0b01 PFCRPn[RWSC] PFCRPn[APC] 0b011 0b111; PFCRPn[WWSC] 0b01 Recovery Time Frequency5 Symbol Initial Max2 5200 Max3 15,000 fSYS Unit tRecover
t256kpperase trwsc
Typical program erase times assume nominal supply values operation Initial factory condition: program/erase cycles, nominal supply values operation maximum time worst case conditions after specified number program/erase cycles. This maximum value characterized guaranteed. Actual hardware programming time. This does include software overhead. Wait state timing based system clock frequency thus same masters.
Table Flash EEPROM Module Life (Full Temperature Range)
Spec Characteristic Number Program/Erase cycles block blocks over operating temperature range (TJ) Number Program/Erase cycles block blocks over operating temperature range (TJ) Minimum Data Retention ambient temperature2 Blocks with 0-1,000 cycles Blocks with 1,001-10,000 cycles Blocks with 10,001-100,000 cycles Symbol Retention 100,000 1,000 Typical1 Unit cycles
100,000 cycles years
Typical endurance evaluated Product qualification performed minimum specification. additional information Freescale definition Typical Endurance, please refer Engineering Bulletin EB619, Typical Endurance Nonvolatile Memory. Ambient temperature averaged over duration application, exceed product operating temperature range.
4.13
Spec
Specifications
Table Specifications (5.0
Type2 SRC/DSC3 Output Delay4,4 (ns) 318/343 408/431 61/67 80/90 18/18 27/28 Rise/Fall5,6 (ns) 155/173 188/204 30/34 38/44 10/11 15/17 Load Drive (pF)
Slow7
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Electrical Characteristics
Table Specifications (5.0 (continued)
Spec Type2 SRC/DSC3 Medium Fast8
Output Delay4,4 (ns) 142/186 195/253 20/35 41/64 12/11 32/34
Rise/Fall5,6 (ns) 65/89 91/122 8.7/16.6 24/35 5.3/5.9 21/23
Load Drive (pF)
Input
1.9/1.9
1.5/1.5
These worst case values that estimated from simulation tested. values table simulated FSYS MHz, 1.08 1.32 VDDE 1.62 1.98 VDDEH VRC33 VDDPLL Slow SHA; Medium MHA; Fast Input IHA. Table SRC/DSC bitfields Configuration Registers. SRC-Slew Rate Control (slow medium types only), DSC-Drive Strength Control (fast type only). This parameter supplied reference guaranteed design tested. This parameter guaranteed characterization before qualification rather than 100% tested. Delay rise/fall measured respective signal. maximum system clock output delay delay with respect system clock. Output delay shown Figure maximum system clock output delay delay with respect system clock.
Table De-rated Specifications (3.3
Spec Type2 SRC/DSC3 Delay4,5 (ns) 408/431 533/592 Slow7 80/90 146/167 27/28 81/92 184/240 253/330 28/47 Medium 58/88 18/17 46/51 30/35 34/49 7.6/8.9 114/153 11.8/21.8 57/67 79/107 82/96 15/17 250/288 38/44 Rise/Fall6, (ns) 188/204 Load Drive (pF)
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Electrical Characteristics
Table De-rated Specifications (3.3 (continued)
Spec Type2 SRC/DSC3 Fast8
Delay4,5 (ns)
Rise/Fall6, (ns)
Load Drive (pF)
Input
1.5/1.5
These worst case values that estimated from simulation tested. values table simulated FSYS MHz, 1.08 1.32 VDDE VDDEH VRC33 VDDPLL Slow SHA; Medium MHA; Fast Input IHA. Table SRC/DSC bitfields Configuration Registers. SRC-Slew Rate Control (slow medium types only), DSC-Drive Strength Control (fast type only). This parameter supplied reference guaranteed design tested. Delay rise/fall measured respective signal. This parameter guaranteed characterization before qualification rather than 100% tested. maximum system clock output delay delay with respect system clock. Output delay shown Figure maximum system clock output delay delay with respect system clock.
VDD/2 Internal Data Input Signal Rising Edge Delay Falling Edge Delay
Output
Figure Output Delay
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Electrical Characteristics
4.14
4.14.1
Spec
Timing
Reset Boot Configuration Pins
Table Reset Boot Configuration Timing
Characteristic RESET Pulse Width BOOTCFG Setup Time after RESET Valid BOOTCFG Hold Time from RESET Valid Symbol tRPW tRCSU tRCH Unit
RESET
BOOTCFG
Figure Reset Boot Configuration Timing
4.14.2
Spec
External Interrupt (IRQ) Non-Maskable Interrupt (NMI) Pins
Table IRQ/NMI Timing
Characteristic Symbol tIPWL TIPWH tICYC Unit tSYS tSYS tSYS
IRQ/NMI Pulse Width IRQ/NMI Pulse Width High IRQ/NMI Edge Edge Time1
Applies when IRQ/NMI pins configured rising edge falling edge events, both.
IRQ/NMI
Figure Timing
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Electrical Characteristics
4.14.3
Spec
JTAG (IEEE 1149.1) Interface
Table JTAG Interface Timing1
Characteristic Cycle Time Clock Pulse Width (Measured VDDE/2) Rise Fall Times (40% 70%) TMS, Data Setup Time TMS, Data Hold Time Data Valid Data Invalid High Impedance JCOMP Assertion Time JCOMP Setup Time Falling Edge Output Valid Falling Edge Output Valid High Impedance Falling Edge Output High Impedance Boundary Scan Input Valid Rising Edge Rising Edge Boundary Scan Input Invalid Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Unit
These specifications apply JTAG boundary scan only. JTAG timing specified VDDE with 0b11.
Figure JTAG Test Clock Input Timing
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TMS,
JCOMP
Freescale Semiconductor
Figure JTAG JCOMP Timing
Figure JTAG Test Access Port Timing
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Electrical Characteristics
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Electrical Characteristics
Output Signals Output Signals Input Signals
Figure JTAG Boundary Scan Timing
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Electrical Characteristics
4.14.4
Spec
Nexus Debug Interface
Table Nexus Debug Port Timing1
Characteristic Symbol tMCYC tMDC
15.6 -0.1
0.25
Unit tMCYC tTCYC tMCYC
MCKO Cycle Time MCKO Duty Cycle MCKO MDO, MSEO, EVTO Data Valid EVTI Pulse Width EVTO Pulse Width Cycle Time Duty Cycle TDI, Data Setup Time TDI, Data Hold Time Data Valid
tMDOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV
JTAG specifications this table apply when used debug functionality. Nexus timing relative MCKO measured from MCKO respective signal. Nexus timing specified VDDE with 0b11. MDO, MSEO, EVTO data held valid until next MCKO cycle. system clock frequency needs three times faster than frequency.
MCKO
MSEO EVTO Output Data Valid
EVTI
Figure Nexus Output Timing
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Electrical Characteristics
TMS,
Figure Nexus TDI, TMS, Timing
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Electrical Characteristics
4.14.5
Spec
Enhanced Modular Subsystem (eMIOS)
Table eMIOS Timing1
Characteristic eMIOS Input Pulse Width eMIOS Output Pulse Width Symbol tMIPW tMOPW Unit tCYC tCYC
eMIOS timing specified VDDE with 0b11. This specification does include rise fall times. When calculating minimum eMIOS pulse width, include rise fall times defined slew rate control fields (SRC) configuration registers (PCR).
Figure eMIOS Timing
D_CLKOUT
eMIOS output
eMIOS input
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Electrical Characteristics
4.14.6
Deserial Serial Peripheral Interface (DSPI)
Table DSPI Timing
MHz1
Spec
Characteristic
Symbol Min. Value Max. Value
Unit
DSPI Cycle Time Master (MTFE Slave (MTFE Master (MTFE Slave (MTFE Delay2 After Delay3 Duty Cycle Slave Access Time active SOUT valid) Slave SOUT Disable Time inactive SOUT High-Z invalid) PCSx PCSS time PCSS PCSx time Data Setup Time Inputs Master (MTFE Slave Master (MTFE CPHA Master (MTFE CPHA Data Hold Time Inputs Master (MTFE Slave Master (MTFE CPHA Master (MTFE CPHA Data Valid (after edge) Master (MTFE Slave Master (MTFE CPHA Master (MTFE CPHA Data Hold Time Outputs Master (MTFE Slave Master (MTFE CPHA Master (MTFE CPHA
tSCK tCSC tASC tSDC tDIS tPCSC tPASC tSUI tSUO tSCK tSCK
timing specified with 0b11. maximum value programmable DSPI_CTARn[PSSCK] DSPI_CTARn[CSSCK]. maximum value programmable DSPI_CTARn[PASC] DSPI_CTARn[ASC]. This number calculated assuming SMPL_PT bitfield DSPI_MCR 0b10.
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PCSx Output (CPOL
Output (CPOL Data SOUT First Data Data Last Data Last Data
First Data
Figure DSPI Classic Timing Master, CPHA
PCSx
Output (CPOL Output (CPOL First Data SOUT First Data Data Data Last Data Last Data
Figure DSPI Classic Timing Master, CPHA
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Input (CPOL Input (CPOL SOUT First Data Data Data
Last Data
First Data
Last Data
Figure DSPI Classic Timing Slave, CPHA
Input (CPOL
Input (CPOL SOUT
First Data Data Last Data Data Last Data
First Data
Figure DSPI Classic Timing Slave, CPHA
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PCSx Output (CPOL Output (CPOL First Data SOUT First Data Data Data Last Data Last Data
Figure DSPI Modified Transfer Format Timing Master, CPHA
PCSx
Output (CPOL
Output (CPOL First Data Data SOUT First Data Data
Last Data Last Data
Figure DSPI Modified Transfer Format Timing Master, CPHA
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Input (CPOL Input (CPOL SOUT First Data First Data Data Data Last Data Last Data
Figure DSPI Modified Transfer Format Timing Slave, CPHA
Input (CPOL
Input (CPOL SOUT
First Data Data Last Data Data Last Data
First Data
Figure DSPI Modified Transfer Format Timing Slave, CPHA
PCSS PCSx
Figure DSPI Strobe (PCSS) Timing
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Electrical Characteristics
4.14.7
4.14.7.1
Interface
Media Local Electrical Characteristics
Table Media Local Electrical Characteristics
Parameter Symbol
Table provides electrical characteristics Media Local interface.
Unit
Comments
Maximum Input Voltage Level Input Threshold High Level Input Threshold Level Output Threshold High Level Output Threshold Input Leakage Current
VDDE4
Higher thresholds used; however, risks associated with less noise margin system must evaluated assumed customer.
4.14.7.2
Media Local (MLB) Electrical Characteristics
Table Timing Speed
Table Table provide electrical characteristics Media Local interface.
Spec
Parameter MLBCLK Operating Frequency
Symbol fmck
11.264 31.5 14.5
12.288 24.576 35.5 16.5 36.5 16.5
24.6272 25.600
Unit
Comments
44.0 48.0 48.0 48.1 unlocked unlocked unlocked 256xFs unlocked unlocked
MLBCLK rise time MLBCLK fall time MLBCLK cycle time MLBCLK time
tmckr tmckf tmckc tmckl
MLBCLK high time
tmckh
31.5 14.5
MLBCLK pulse width variation2 MLBSIG/MLBDAT input valid MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK
tmpwv tdsmcf tdhmcf
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Electrical Characteristics
Table Timing Speed (continued)
Spec Parameter MLBSIG/MLBDAT output high impedance from MLBCLK Hold time3 MLBSIG/MLBDAT output valid from MLBCLK rising Symbol tmcfdz tmdzh tmcrdv tmckl Unit Comments
Ground 0.0V Load Capacitance SIU_PCR144-SIU_PCR146[DSC] 0b11. speed kHz) Unless otherwise noted, timing parameters specified from valid voltage threshold Table
Controller shut MLBCLK place low-power state. Pulse width variation measured 1.25 triggering edge MLBCLK measuring spread other edge, measured peak-to-peak p-p). board must designed insure that high-impedance does leave logic state final driven this time period. Therefore, coupling must minimized while meeting maximum capacitive load listed.
Table Timing Speed 1024
Spec Parameter MLBCLK Operating Frequency1 Symbol fmck 45.056 49.152 20.3 10.6 10.2 49.2544 51.200 tmckl Unit Comments
1024 44.0 1024 48.0 1024 48.1 1024 unlocked 1024 unlocked 1024 unclocked
MLBCLK rise time MLBCLK fall time MLBCLK cycle time MLBCLK time MLBCLK high time MLBCLK pulse width variation2 MLBSIG/MLBDAT input valid MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK MLBSIG/MLBDAT output high impedance from MLBCLK Hold time3 MLBSIG/MLBDAT output valid from MLBCLK rising
tmckr tmckf tmckc tmckl tmckh tmpwv tdsmcf tdhmcf tmcfdz tmdzh tmcrdv
Ground 0.0V Load Capacitance SIU_PCR144-SIU_PCR146[DSC] 0b00. speed 1024Fs kHz) Unless otherwise noted, timing parameters specified from valid voltage threshold Table
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Electrical Characteristics
Controller shut MLBCLK place low-power state. Pulse width variation measured 1.25 triggering edge MLBCLK measuring spread other edge, measured peak-to-peak p-p). board must designed insure that high-impedance does leave logic state final driven this time period. Therefore, coupling must minimized while meeting maximum capacitive load listed.
MLBSIG/ MLBDAT (input)
valid data
MLBCLK MLBSIG/ MLBDAT (output)
valid data
Figure Media Local (MLB) Timing
4.14.8
Fast Ethernet Interface
signals CMOS signal levels compatible with devices operating either Signals compatible. They follow CMOS electrical characteristics.
4.14.8.1
Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, RX_CLK)
receiver functions correctly RX_CLK maximum frequency +1%. There minimum frequency requirement. addition, system clock frequency must exceed four times RX_CLK frequency. Table Receive Signal Timing
Spec Characteristic RXD[3:0], RX_DV, RX_ER RX_CLK setup RX_CLK RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width Unit RX_CLK period RX_CLK period
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RX_CLK (input)
RXD[3:0] (inputs) RX_DV RX_ER
Figure Receive Signal Timing Diagram
4.14.8.2
Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
transmitter functions correctly TX_CLK maximum frequency +1%. There minimum frequency requirement. addition, system clock frequency must exceed four times TX_CLK frequency. transmit outputs (TXD[3:0], TX_EN, TX_ER) programmed transition from either rising falling edge TX_CLK, timing same either case. This options allows non-compliant PHYs. Refer Ethernet chapter details this option enable Table Transmit Signal Timing1
Spec
Characteristic TX_CLK TXD[3:0], TX_EN, TX_ER invalid TX_CLK TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width
Unit TX_CLK period TX_CLK period
Output pads configured with 0b11.
TX_CLK (input) TXD[3:0] (outputs) TX_EN TX_ER
Figure Transmit Signal Timing Diagram
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Electrical Characteristics
4.14.8.3
Async Inputs Signal Timing (CRS COL)
Table Async Inputs Signal Timing1
Spec
Characteristic CRS, minimum pulse width
Unit TX_CLK period
Output pads configured with 0b11.
CRS,
Figure Async Inputs Timing Diagram
4.14.8.4
Serial Management Channel Timing (MDIO MDC)
Table Serial Management Channel Timing1
functions correctly with maximum frequency MHz.
Spec
Characteristic falling edge MDIO output invalid (minimum propagation delay) falling edge MDIO output valid (max prop delay) MDIO (input) rising edge setup MDIO (input) rising edge hold pulse width high pulse width
Unit period period
Output pads configured with 0b11.
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Electrical Characteristics
(output) MDIO (output) MDIO (input)
MPC5668x Microcontroller Data Sheet, Rev.
Figure Serial Management Channel Timing Diagram
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Freescale Semiconductor
Package Characteristics
Package Mechanical Data
MPC5668x Microcontroller Data Sheet, Rev.
Figure MAPBGA Package Mechanical Drawing
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Package Characteristics
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Package Characteristics
Figure MAPBGA Package Detail
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Freescale Semiconductor Package Characteristics
MPC5668x Microcontroller Data Sheet, Rev.
Figure MAPBGA Package Mechanical Drawing
Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Package Characteristics
Figure MAPBGA Package Detail
MPC5668x Microcontroller Data Sheet, Rev.
Preliminary-Subject Change Without Notice
Freescale Semiconductor
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
Revision History
Revision History
Table Revision History
Revision Date April 2008 June 2008 2009 Preliminary release. Initial release: Advance Information. Release: Advance Information. Description
Table describes changes made this document between revisions.
September 2009 Release: Advance Information, interim updates.
MPC5668x Microcontroller Data Sheet, Rev. Freescale Semiconductor Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
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Document Number: MPC5668X
Rev. 9/2009
Preliminary-Subject Change Without Notice
Because order from United States International Trade Commission, BGA-packaged product lines part numbers indicated here currently available from Freescale import sale United States prior September 2010: MPC5668x products MAPBGA packages
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