JPEG-D Baseline JPEG Decoder Core Implements high-performanc

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JPEG-D Baseline JPEG Decoder Core Implements high-performanc

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Baseline ISO/IEC 10918-1 JPEG Compliance
JPEG-D
Baseline JPEG Decoder Core
Implements high-performance image video decoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG cores, JPEG-D provides high-performance solution variety image video decompression applications. can, example, decode 16:9 HDTV, 1920x1152, 4:2:0, even FPGA devices. typical 0.09µ process ASIC, core requires just 61,000 gates operates MHz. addition processing baseline JPEG streams, core decompress nonstandard motion JPEG streams. also enhanced with optional IDCT block that enables down-scaling frequency domain, feature that allows decompression various resolutions from same compressed stream. core includes FIFO-like pixel stream input/output interfaces, other standard interfaces (e.g. AMBA) also available. core designed reliability ease integration, been proven number ASIC FPGA designs. deliverables include software bit-accurate model that facilitates system chip verification.
Programmable Huffman Tables
(two
Programmable quantization
tables (four)
four color components
(optionally extendable components)
Supports possible scan confi-
gurations JPEG formats input/output data
Supports image size
Supports restart mark-
Additional Image Processing Capabilities
Motion JPEG decoding Decompressing various reso-
lutions downscaling frequency domain (optional)
Designed Easy Integration
Stand alone operation Automatic self-programming
JPEG stream headers parsing
Header errors catching Broadcasting decoded image
Applications
high-performance JPEG-D, standard-compliant core suitable implementing variety multimedia applications, including: Digital cameras camcorders Office automation equipment (multifunction printers, scanners, digital copiers etc) Medical imaging systems Video production suites Video conference display-projection systems Surveillance systems
parameters controlling peripherals such raster block converter
Designed High Quality
Robust verification environment
includes bit-accurate software model
ASIC FPGA proven mul-
tiple designs
Scan-ready design architecture
Block Diagram
Register File Frame, Scan, Parameters JPEG Stream Stream Parser Huffman Decoder
Control Unit Image Data
UnStuff
FIFO
Expand DIFF decode
ZZ-1
IDCT
Huffman Tables
Quant. Tables
IDCT Buffer
JPEG-D
January 2008
Functional Description
decoding path highly autonomous, since JPEG-D self-configured (with table, image format encoding options) parsing incoming JPEG stream's headers. core parses checks JPEG marker segments signals case detects error. Decoded image parameters made available controlling peripherals such block-to-raster converter. Designed continuous data flow, JPEG-D address most demanding frame-based video decompression applications. Optional decoding various resolutions from same JPEG data-stream without need extra buffering enabled when IDCT block configured during synthesis support downscaling frequency domain.
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Verification
core been verified through extensive simulation rigorous code coverage measurements. also been embedded several products, proven both ASIC FPGA technologies.
Deliverables
core available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. ASIC version includes: source code. Sophisticated self-checking Testbench (Verilog versions Verilog 2001). Simulation script, vectors, expected results, comparison utility. Software (C++) Bit-Accurate Model Synthesis script. Comprehensive user documentation, including detailed specifications system integration guide.
Implementation Results
JPEG-D reference designs have been evaluated variety technologies. following sample pre-layout ASIC results reported synthesis tool silicon vendor design under typical conditions) optimized speed.
ASIC Technology 0.18µ process TSMC 0.09µ process Logic Gates 68,459 61,061 Frequency Memory 14,400 bits 14,400 bits
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
This core developed multimedia experts Alma Technologies S.A.

JPEG-D Baseline JPEG Decoder Core Implements high-performanc

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