core implements serial interface that meets Philips specification supp

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

core implements serial interface that meets Philips specification supp

Datasheet Thumbnail

Top Searches for this datasheet

Master/Slave Controller Core
core implements serial interface that meets Philips specification supports transfer modes from bus. logic handles bytes transfer autonomously. also keeps track serial transfers, status register (i2csta) reflects status Controller bus. microcode-free design developed reuse ASIC FPGA implementations. design strictly synchronous with positive-edge clocking, internal tristates synchronous reset; therefore scan insertion straightforward.
Master Transmitter Mode Serial data output through while outputs serial clock. Master Receiver Mode Serial data received while outputs serial clock. Slave Receiver Mode Serial data serial clock received through SCL. Slave Transmitter Mode Serial data transmitted while serial clock input through SCL. Data transfers Kbps standard mode Kbps fast-mode. Bi-directional data transfer. address General Call address detection. 7-bit addressing format. Fixed data width bits. Data transfer multiples bytes. One-byte write read buffer.
Applications
utilized variety serial interface applications including: Embedded microcontroller systems Communication systems
Benefits
provides convenient interface facto world standard broad range applications uses only wires connect virtually unlimited number devices, therefore minimizing interconnections usage pins user application standard implements simple efficient which does require additional logic such address decoders arbiters
Block Diagram
January 2009
Functional Description
core partitioned into modules shown figure described below.
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Arbitration synchronization logic
master mode, arbitration logic checks that every transmitted logic actually appears logic bus. another device overrules logic pulls line low, arbitration lost immediately changes from master transmitter slave receiver. synchronization logic will synchronize serial clock generator with clock pulses line from another device.
Verification
core's functionality verified means proprietary hardware modeler. same stimulus applied hardware model that contained original Philips 80C552 chip, results compared with core's simulation outputs.
Serial clock generator
This programmable clock pulse generator provides clock pulses when master mode. clock generator switched when slave mode.
Deliverables
core available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. ASIC version includes: source code Testbench Simulation script, vectors, expected results, comparison utility Synthesis script Comprehensive user documentation, including detailed specifications system integration guide
Control logic
control logic generates control signals serial byte handling.
Input filter
Input signals synchronized with internal clock (clk), spikes shorter than three oscillator periods filtered out.
Address comparator
comparator compares received 7-bit slave address with slave address. also compares first received 8-bit byte with general call address (00H). equality found, appropriate status bits interrupt requested.
Configurability
Hardware configurability features: Glitch register: configurable glitch removal length from both clock data lines Runtime configuration features: address clock generation: From division system clock From external clock generator
Core Modifications
core modified change serial transmission rate. Please contact CAST, Inc. directly required modifications.
Implementation Results
reference designs have been evaluated variety technologies. following sample ASIC results with clock constraint MHz.
ASIC Technology TSMC 0.09 TSMC 0.13 TSMC 0.18 Cell Area 3,266 6,336 12,826 NAND2 Area 2.8224 5.0922 9.9792 Approx. Area (gate equiv.) 1,244 1,285 Frequency
Toggle general call address accept
Related Products
I2C-HS Controller which provides serial interface that meets Philips specification v.2.1, compliant with PVCI (Peripheral Virtual Component Interface) AMBA interfaces. I2CS Controller which provides slave serial interface that meets Philips specification supports slave transfer modes from bus.
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2009, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.

core implements serial interface that meets Philips specification supp

Top Searches for this datasheet

Other recent searches