LPC1311/13/42/43 Rev. 00.17 October 2009 32-bit Cortex-M3 mi

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LPC1311/13/42/43 Rev. 00.17 October 2009 32-bit Cortex-M3 mi

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LPC1311/13/42/43
Rev. 00.17 October 2009
32-bit Cortex-M3 microcontroller; flash SRAM; device
Preliminary data sheet
General description
LPC1311/13/42/43 Cortex-M3 based microcontrollers embedded applications featuring high level integration power consumption. Cortex-M3 next generation core that offers system enhancements such enhanced debug features higher level support block integration. LPC1311/13/42/43 operate frequencies MHz. Cortex-M3 incorporates 3-stage pipeline uses Harvard architecture with separate local instruction data buses well third peripherals. Cortex-M3 also includes internal prefetch unit that supports speculative branching. peripheral complement LPC1311/13/42/43 includes flash memory, data memory, Device (LPC1342/43 only), Fast-mode Plus I2C-bus interface, UART, four general-purpose timers, general-purpose pins.
Features
Cortex-M3 processor, running frequencies MHz. Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). (LPC1343/13)/16 (LPC1342)/8 (LPC1311) on-chip flash programming memory. (LPC1343/13)/4 (LPC1342/11) SRAM. In-System Programming (ISP) In-Application Programming (IAP) on-chip bootloader software. Selectable boot-up: UART (USB LPC134x only). Serial interfaces: full-speed device controller with on-chip device (LPC1342/43 only). UART with fractional baud rate generation, modem, internal FIFO, RS-485/EIA-485 support. controller with FIFO multi-protocol capabilities. I2C-bus interface supporting full I2C-bus specification Fast-mode Plus with data rate Mbit/s with multiple address recognition monitor mode. Other peripherals: General Purpose (GPIO) pins with configurable pull-up/pull-down resistors.
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Four general purpose timers/counters with total four capture inputs match outputs. Programmable WatchDog Timer (WDT). System tick timer. Serial Wire Debug Serial Wire Trace port. High-current output driver pin. High-current sink drivers I2C-bus pins Fast-mode Plus. Integrated (Power Management Unit) minimize power consumption during Sleep, Deep-sleep, Deep power-down modes. Three reduced power modes: Sleep, Deep-sleep, Deep power-down. Single power supply (2.0 10-bit with input multiplexing among pins. GPIO pins used edge level sensitive interrupt sources. Clock output function with divider that reflect system oscillator clock, clock, clock, watchdog clock. Processor wake-up from Deep-sleep mode dedicated start logic using functional pins. Brownout detect with four separate thresholds interrupt threshold forced reset. Power-On Reset (POR). Crystal oscillator with operating range MHz. internal oscillator trimmed accuracy that optionally used system clock. allows operation maximum rate without need high-frequency crystal. from main oscillator, internal oscillator, watchdog oscillator. Code Read Protection (CRP) with different security levels. Available 48-pin LQFP package 33-pin HVQFN package.
Applications
eMetering Lighting Industrial networking Alarm systems White goods
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Ordering information
Table Ordering information Package Name LPC1311FHN33 HVQFN33 LPC1313FBD48 LQFP48 LPC1313FHN33 HVQFN33 LPC1342FHN33 HVQFN33 LPC1343FBD48 LQFP48 LPC1343FHN33 HVQFN33 Description Type number
HVQFN: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 HVQFN: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 HVQFN: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 HVQFN: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
LQFP48: plastic profile quad flat package; leads; body sot313-2
LQFP48: plastic profile quad flat package; leads; body sot313-2
Version
Ordering options
Table Ordering options LPC1311/13/42/43 Flash Total SRAM Device Device Device UART RS-485 I2C/ Fast+ channels Pins Package HVQFN33 LQFP48 HVQFN33 HVQFN33 LQFP48 HVQFN33 Type number LPC1311FHN33 LPC1313FBD48 LPC1313FHN33 LPC1342FHN33 LPC1343FBD48 LPC1343FHN33
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Block diagram
XTALIN XTALOUT RESET
pins
LPC1311/13/42/43
PHY(1) CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks controls slave AHB-LITE CLKOUT
TEST/DEBUG INTERFACE
CORTEX-M3
I-code D-code system
DEVICE CONTROLLER(1)
slave
slave
SRAM
GPIO ports PIO0/1/2/3
HIGH-SPEED GPIO
slave
slave BRIDGE
slave FLASH 8/16/32
DTR, DSR(2), CTS, DCD(2), RI(2), CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0
UART
10-bit
AD[7:0] SSEL MISO MOSI
32-bit COUNTER/TIMER 32-bit COUNTER/TIMER 16-bit COUNTER/TIMER 16-bit COUNTER/TIMER I2C-BUS
IOCONFIG SYSTEM CONTROL
002aae722
LPC1342/43 only. LQFP48 package only.
Block diagram
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Pinning information
Pinning
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
PIO1_11/AD7
PIO2_3/RI
VDD(3V3)
PIO3_3
PIO3_2
PIO2_6 PIO2_0/DTR RESET/PIO0_0 VSSIO XTALIN XTALOUT VDD(IO) PIO1_8/CT16B1_CAP0
PIO3_1 PIO3_0 TRST/PIO1_2/AD3/CT32B1_MAT1 TDO/PIO1_1/AD2/CT32B1_MAT0 TMS/PIO1_0/AD1/CT32B1_CAP0 TDI/PIO0_11/AD0/CT32B0_MAT3 PIO2_11/SCK PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0 PIO2_2/DCD PIO2_10 PIO2_9
002aae505
LPC1343FBD48
PIO0_2/SSEL/CT16B0_CAP0 PIO2_7 PIO2_8 PIO2_1/DSR PIO0_3/USB_VBUS PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0 PIO2_4 USB_DM USB_DP PIO2_5 PIO0_6/USB_CONNECT/SCK PIO0_7/CTS
LPC1343 LQFP48 package
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
terminal index area PIO2_0/DTR RESET/PIO0_0 XTALIN XTALOUT VDD(IO) PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0
PIO1_11/AD7
VDD(3V3)
PIO3_2
TRST/PIO1_2/AD3/CT32B1_MAT1 TDO/PIO1_1/AD2/CT32B1_MAT0 TMS/PIO1_0/AD1/CT32B1_CAP0 TDI/PIO0_11/AD0/CT32B0_MAT3 PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0
LPC1342FHN33 LPC1343FHN33
PIO0_6/USB_CONNECT/SCK PIO0_7/CTS
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0
USB_DM
USB_DP
002aae516
Transparent view
LPC1342/43 HVQFN33 package
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
PIO1_11/AD7
PIO2_3/RI
VDD(3V3)
PIO3_3
PIO3_2
PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 VSSIO XTALIN XTALOUT VDD(IO) PIO1_8/CT16B1_CAP0
PIO3_1 PIO3_0 TRST/PIO1_2/AD3/CT32B1_MAT1 TDO/PIO1_1/AD2/CT32B1_MAT0 TMS/PIO1_0/AD1/CT32B1_CAP0 TDI/PIO0_11/AD0/CT32B0_MAT3 PIO2_11/SCK PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0 PIO2_2/DCD PIO2_10 PIO2_9
002aae513
LPC1313FBD48
PIO0_2/SSEL/CT16B0_CAP0 PIO2_7 PIO2_8 PIO2_1/DSR PIO0_3 PIO0_4/SCL PIO0_5/SDA PIO1_9/CT16B1_MAT0 PIO3_4 PIO2_4 PIO2_5 PIO3_5 PIO0_6/SCK PIO0_7/CTS
LPC1313 LQFP48 package
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO1_6/RXD/CT32B0_MAT0
PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0
terminal index area PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT VDD(IO) PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0
PIO1_11/AD7
VDD(3V3)
PIO3_2
TRST/PIO1_2/AD3/CT32B1_MAT1 TDO/PIO1_1/AD2/CT32B1_MAT0 TMS/PIO1_0/AD1/CT32B1_CAP0 TDI/PIO0_11/AD0/CT32B0_MAT3 PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 PIO0_9/MOSI/CT16B0_MAT1/SWO PIO0_8/MISO/CT16B0_MAT0
LPC1311FHN33 LPC1313FHN33
PIO0_6/SCK PIO0_7/CTS
PIO0_4/SCL
PIO0_5/SDA
PIO0_3
PIO3_4
PIO1_9/CT16B1_MAT0
PIO3_5
002aae517
Transparent view
LPC1311/13 HVQFN33 package
description
Table Symbol RESET/PIO0_0 LPC1313/43 LQFP48 description table Type Description RESET External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address PIO0_0 General purpose digital input/output pin. PIO0_1 General purpose digital input/output pin. level this during reset starts command handler device enumeration (USB LPC1343 only, description PIO0_3). CLKOUT Clockout pin. CT32B0_MAT2 Match output 32-bit timer USB_FTOGGLE Start-of-Frame signal (LPC1343 only). PIO0_2 General purpose digital input/output pin. SSEL Slave select SSP. CT16B0_CAP0 Capture input 16-bit timer
B.V. 2009. rights reserved.
PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE 4[1]
PIO0_2/SSEL/ CT16B0_CAP0 10[1]
LPC1311_13_42_43_0
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol
LPC1313/43 LQFP48 description table .continued 14[1] Type Description
PIO0_3/USB_VBUS
PIO0_3 General purpose digital input/output pin. LPC1343 only: level this during reset starts command handler, HIGH level starts device enumeration.
PIO0_4/SCL 15[2] PIO0_5/SDA 16[2] PIO0_6/USB_CONNECT/ 22[1] PIO0_7/CTS 23[1] PIO0_8/MISO/ CT16B0_MAT0 27[1] PIO0_9/MOSI/ CT16B0_MAT1/ 28[1] SWCLK/PIO0_10/ SCK/CT16B0_MAT2 29[1] TDI/PIO0_11/ AD0/CT32B0_MAT3 32[3] TMS/PIO1_0/ AD1/CT32B1_CAP0 33[3] TDO/PIO1_1/ AD2/CT32B1_MAT0 34[3]
USB_VBUS Monitors presence power (LPC1343 only). PIO0_4 General purpose digital input/output pin. I2C-bus clock input/output. High-current sink only Fast-mode Plus selected configuration register. PIO0_5 General purpose digital input/output pin. I2C-bus data input/output. High-current sink only Fast-mode Plus selected configuration register. PIO0_6 General purpose digital input/output pin. USB_CONNECT Signal used switch external resistor under software control. Used with SoftConnect feature (LPC1343 only). Serial clock SSP. PIO0_7 General purpose digital input/output (high-current output driver). Clear Send input UART. PIO0_8 General purpose digital input/output pin. MISO Master Slave SSP. CT16B0_MAT0 Match output 16-bit timer PIO0_9 General purpose digital input/output pin. MOSI Master Slave SSP. CT16B0_MAT1 Match output 16-bit timer Serial wire trace output. SWCLK Serial wire clock test clock JTAG interface. PIO0_10 General purpose digital input/output pin. Serial clock SSP. CT16B0_MAT2 Match output 16-bit timer Test Data JTAG interface. PIO0_11 General purpose digital input/output pin. converter, input CT32B0_MAT3 Match output 32-bit timer Test Mode Select JTAG interface. PIO1_0 General purpose digital input/output pin. converter, input CT32B1_CAP0 Capture input 32-bit timer Test Data JTAG interface. PIO1_1 General purpose digital input/output pin. converter, input CT32B1_MAT0 Match output 32-bit timer
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol
LPC1313/43 LQFP48 description table .continued 35[3] Type Description TRST Test Reset JTAG interface. PIO1_2 General purpose digital input/output pin. converter, input CT32B1_MAT1 Match output 32-bit timer SWDIO Serial wire debug input/output. PIO1_3 General purpose digital input/output pin. converter, input CT32B1_MAT2 Match output 32-bit timer PIO1_4 General purpose digital input/output pin. converter, input CT32B1_MAT3 Match output 32-bit timer WAKEUP Deep power-down mode wake-up pin. PIO1_5 General purpose digital input/output pin. Request Send output UART. CT32B0_CAP0 Capture input 32-bit timer PIO1_6 General purpose digital input/output pin. Receiver input UART. CT32B0_MAT0 Match output 32-bit timer PIO1_7 General purpose digital input/output pin. Transmitter output UART. CT32B0_MAT1 Match output 32-bit timer PIO1_8 General purpose digital input/output pin. CT16B1_CAP0 Capture input 16-bit timer PIO1_9 General purpose digital input/output pin. CT16B1_MAT0 Match output 16-bit timer PIO1_10 General purpose digital input/output pin. converter, input CT16B1_MAT1 Match output 16-bit timer PIO1_11 General purpose digital input/output pin. converter, input PIO2_0 General purpose digital input/output pin. Data Terminal Ready output UART. PIO2_1 General purpose digital input/output pin. Data Ready input UART. PIO2_2 General purpose digital input/output pin. Data Carrier Detect input UART. PIO2_3 General purpose digital input/output pin. Ring Indicator input UART.
TRST/PIO1_2/ AD3/CT32B1_MAT1
SWDIO/PIO1_3/AD4/ CT32B1_MAT2
39[3]
PIO1_4/AD5/ CT32B1_MAT3/WAKEUP
40[3]
PIO1_5/RTS/ CT32B0_CAP0
45[1]
PIO1_6/RXD/ CT32B0_MAT0
46[1]
PIO1_7/TXD/ CT32B0_MAT1
47[1]
PIO1_8/CT16B1_CAP0 PIO1_9/CT16B1_MAT0 PIO1_10/AD6/ CT16B1_MAT1
9[1] 17[1] 30[3]
PIO1_11/AD7 PIO2_0/DTR PIO2_1/DSR PIO2_2/DCD PIO2_3/RI PIO2_4 PIO2_4 PIO2_5
LPC1311_13_42_43_0
42[3] 2[1] 13[1] 26[1] 38[1] 18[1] 19[1] 21[1]
PIO2_4 General purpose digital input/output (LPC1343 only). PIO2_4 General purpose digital input/output (LPC1313 only). PIO2_5 General purpose digital input/output (LPC1343 only).
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10
LPC1313/43 LQFP48 description table .continued 20[1] 1[1] 11[1] 12[1] 24[1] 25[1] 31[1] 36[1] 37[1] 43[1] 48[1] 18[1] 21[1] 19[4] 20[4] 8[5] 44[5] 6[6] 7[6] Type Description PIO2_6 General purpose digital input/output pin. PIO2_7 General purpose digital input/output pin. PIO2_8 General purpose digital input/output pin. PIO2_9 General purpose digital input/output pin. PIO2_10 General purpose digital input/output pin. PIO2_11 General purpose digital input/output pin. Serial clock SSP. PIO3_0 General purpose digital input/output pin. PIO3_1 General purpose digital input/output pin. PIO3_2 General purpose digital input/output pin. PIO3_3 General purpose digital input/output pin.
PIO2_5 General purpose digital input/output (LPC1313 only).
PIO2_11/SCK PIO3_0 PIO3_1 PIO3_2 PIO3_3 PIO3_4 PIO3_5 USB_DM USB_DP VDD(IO) VDD(3V3) VSSIO XTALIN XTALOUT
PIO3_4 General purpose digital input/output (LPC1313 only). PIO3_5 General purpose digital input/output (LPC1313 only). USB_DM bidirectional line (LPC1343 only). USB_DP bidirectional line (LPC1343 only). input/output supply voltage. supply voltage internal regulator ADC. Also used reference voltage. Ground. Input oscillator circuit internal clock generator circuits. Input voltage must exceed Output from oscillator amplifier. Ground.
tolerant providing digital functions with configurable pull-up/pull-down resistors configurable hysteresis. I2C-bus pads compliant with I2C-bus specification standard mode Fast-mode Plus. tolerant providing digital functions with configurable pull-up/pull-down resistors, configurable hysteresis, analog input. When configured input, digital section disabled tolerant. provides functions. designed accordance with specification, revision (Full-speed Low-speed mode only). together VDD(3V3) VDD(IO) externally. separate supplies used VDD(3V3) VDD(IO), ensure that voltage difference between both supplies smaller than equal When system oscillator used, connect XTALIN XTALOUT follows: XTALIN left floating grounded (grounding preferred reduce susceptibility noise). XTALOUT should left floating.
Table Symbol
LPC1311/13/42/43 HVQFN33 description table Type Description RESET External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address PIO0_0 General purpose digital input/output pin.
RESET/PIO0_0
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol
LPC1311/13/42/43 HVQFN33 description table .continued 3[1] Type Description
PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE
PIO0_1 General purpose digital input/output pin. level this during reset starts command handler device enumeration (USB LPC1342/43 only, description PIO0_3).
PIO0_2/SSEL/ CT16B0_CAP0 8[1] PIO0_3/USB_VBUS 9[1]
CLKOUT Clock pin. CT32B0_MAT2 Match output 32-bit timer USB_FTOGGLE Start-of-Frame signal (LPC1342/43 only). PIO0_2 General purpose digital input/output pin. SSEL Slave select SSP. CT16B0_CAP0 Capture input 16-bit timer PIO0_3 General purpose digital input/output pin. LPC1342/43 only: level this during reset starts command handler, HIGH level starts device enumeration. USB_VBUS Monitors presence power (LPC1342/43 only). PIO0_4 General purpose digital input/output pin. I2C-bus clock input/output. High-current sink only Fast-mode Plus selected configuration register. PIO0_5 General purpose digital input/output pin. I2C-bus data input/output. High-current sink only Fast-mode Plus selected configuration register. PIO0_6 General purpose digital input/output pin. USB_CONNECT Signal used switch external resistor under software control. Used with SoftConnect feature (LPC1342/43 only). Serial clock SSP. PIO0_7 General purpose digital input/output (high-current output driver). Clear Send input UART. PIO0_8 General purpose digital input/output pin. MISO Master Slave SSP. CT16B0_MAT0 Match output 16-bit timer PIO0_9 General purpose digital input/output pin. MOSI Master Slave SSP. CT16B0_MAT1 Match output 16-bit timer Serial wire trace output. SWCLK Serial wire clock test clock JTAG interface. PIO0_10 General purpose digital input/output pin. Serial clock SSP. CT16B0_MAT2 Match output 16-bit timer Test Data JTAG interface. PIO0_11 General purpose digital input/output pin. converter, input CT32B0_MAT3 Match output 32-bit timer
PIO0_4/SCL 10[2] PIO0_5/SDA 11[2] PIO0_6/USB_CONNECT/ 15[1]
PIO0_7/CTS 16[1] PIO0_8/MISO/ CT16B0_MAT0 17[1] PIO0_9/MOSI/ CT16B0_MAT1/ 18[1] SWCLK/PIO0_10/SCK/ CT16B0_MAT2 19[1] TDI/PIO0_11/AD0/ CT32B0_MAT3 21[3]
LPC1311_13_42_43_0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol
LPC1311/13/42/43 HVQFN33 description table .continued 22[3] Type Description Test Mode Select JTAG interface. PIO1_0 General purpose digital input/output pin. converter, input CT32B1_CAP0 Capture input 32-bit timer Test Data JTAG interface. PIO1_1 General purpose digital input/output pin. converter, input CT32B1_MAT0 Match output 32-bit timer TRST Test Reset JTAG interface. PIO1_2 General purpose digital input/output pin. converter, input CT32B1_MAT1 Match output 32-bit timer SWDIO Serial wire debug input/output. PIO1_3 General purpose digital input/output pin. converter, input CT32B1_MAT2 Match output 32-bit timer PIO1_4 General purpose digital input/output pin. converter, input CT32B1_MAT3 Match output 32-bit timer WAKEUP Deep power-down mode wake-up pin. PIO1_5 General purpose digital input/output pin. Request Send output UART. CT32B0_CAP0 Capture input 32-bit timer PIO1_6 General purpose digital input/output pin. Receiver input UART. CT32B0_MAT0 Match output 32-bit timer PIO1_7 General purpose digital input/output pin. Transmitter output UART. CT32B0_MAT1 Match output 32-bit timer PIO1_8 General purpose digital input/output pin. CT16B1_CAP0 Capture input 16-bit timer PIO1_9 General purpose digital input/output pin. CT16B1_MAT0 Match output 16-bit timer PIO1_10 General purpose digital input/output pin. converter, input CT16B1_MAT1 Match output 16-bit timer PIO1_11 General purpose digital input/output pin. converter, input PIO2_0 General purpose digital input/output pin. Data Terminal Ready output UART. PIO3_2 General purpose digital input/output pin.
TMS/PIO1_0/AD1/ CT32B1_CAP0
TDO/PIO1_1/AD2/ CT32B1_MAT0
23[3]
TRST/PIO1_2/AD3/ CT32B1_MAT1
24[3]
SWDIO/PIO1_3/AD4/ CT32B1_MAT2
25[3]
PIO1_4/AD5/ CT32B1_MAT3/WAKEUP
26[3]
PIO1_5/RTS/ CT32B0_CAP0
30[1]
PIO1_6/RXD/ CT32B0_MAT0
31[1]
PIO1_7/TXD/ CT32B0_MAT1
32[1]
PIO1_8/CT16B1_CAP0 PIO1_9/CT16B1_MAT0 PIO1_10/AD6/ CT16B1_MAT1
7[1] 12[1] 20[3]
PIO1_11/AD7 PIO2_0/DTR PIO3_2
LPC1311_13_42_43_0
27[3] 1[1] 28[1]
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. 00.17 October 2009
Semiconductors
LPC1311/13/42/43
32-bit Cortex-M3 microcontroller
Table Symbol PIO3_4 PIO3_5 USB_DM USB_DP VDD(IO) VDD(3V3) XTALIN XTALOUT
LPC1311/13/42/43 HVQFN33 description table .continued 13[1] 14[1] 13[4] 14[4] 6[5] 29[5] 4[6] 5[6] Type Description
PIO3_4 General purpose digital input/output (LPC1311/13 only). PIO3_5 General purpose digital input/output (LPC1311/13 only). USB_DM bidirectional line (LPC1342/43 only). USB_DP bidirectional line (LPC1342/43 only). input/output supply voltage.
supply voltage internal DC-DC converter ADC. Also used reference voltage. Input oscillator circuit internal clock generator circuits. Input voltage must exceed Output from oscillator amplifier. Thermal pad. Connect ground.
tolerant providing digital functions with configurable pull-up/pull-down resistors configurable hysteresis. I2C-bus pads compliant with I2C-bus specification standard mode Fast-mode Plus. tolerant providing digital functions with configurable pull-up/pull-down resistors, configurable hysteresis, analog input. When configured input, digital section disabled, tolerant. provides functions. designed accordance with specification, revision (Full-speed Low-speed mode only). together VDD(3V3) VDD(IO) externally. separate supplies used VDD(3V3) VDD(IO), ensure that voltage difference between both supplies smaller than equal When system oscillator used, connect XTALIN XTALOUT follows: XTALIN left floating grounded (grounding preferred reduce susceptibility noise). XTALOUT should left floating.
Functional description
Architectural overview
Cortex-M3 includes three AHB-Lite buses: system bus, I-code bus, D-code (see Figure I-code D-code core buses faster than system used similarly interfaces: dedicated instruction fetch (I-code) data access (D-code). core buses allows simultaneous operations concurrent operations target different devices.
Cortex-M3 processor
Cortex-M3 general purpose, 32-bit microprocessor, which offers high performance very power consumption. Cortex-M3 offers many features, including Thumb-2 instruction set, interrupt latency, hardware divide, interruptable/continuable multiple load store instructions, automatic state save restore interrupts, tightly integrated interrupt controller, multiple core buses capable simultaneous accesses. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. Cortex-M3 processor described detail Cortex-M3 Technical Reference Manual which available official website.
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32-bit Cortex-M3 microcontroller
On-chip flash program memory
LPC1311/13/42/43 contain (LPC1313 LPC1343), (LPC1342), (LPC1311) on-chip flash memory.
On-chip SRAM
LPC1311/13/42/43 contain total (LPC1343 LPC1313) (LPC1342 LPC1311) on-chip static memory.
Memory
LPC134x incorporates several distinct memory regions, shown following figures. Figure shows overall entire address space from user program viewpoint following reset. interrupt vector area supports address remapping. peripheral area size divided allow peripherals. peripheral area size divided allow peripherals. Each peripheral either type allocated space. This allows simplifying address decoding each peripheral.
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32-bit Cortex-M3 microcontroller
LPC1311/13/42/43
0xFFFF FFFF
peripherals
127- reserved reserved 0x5004 0000 0x5020 0000 peripherals 0x5000 0000 reserved peripherals 0x4008 0000 GPIO PIO3 GPIO PIO2 GPIO PIO1 GPIO PIO0 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000
0x5020 0000
0x4008 0000 peripherals reserved 0x2400 0000 SRAM bit-band alias addressing 0x2200 0000 0x4000 0000 0x2000 0000
reserved 0x4004 C000 system control IOCONFIG reserved reserved 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000
reserved reserved 0x1FFF 4000 boot 0x1FFF 0000
0x4002 8000 reserved (LPC1342/43 only) 32-bit counter/timer 32-bit counter/timer 16-bit counter/timer 16-bit counter/timer UART I2C-bus 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
reserved 0x1000 2000 I-code/D-code memory space SRAM (LPC1313/1343) SRAM (LPC1311/1342) 0x1000 1000 0x1000 0000
0x0000 8000
reserved
on-chip flash (LPC1313/43) on-chip flash (LPC1342) on-chip flash (LPC1311)
0x0000 4000 0x0000 2000 0x0000 0000
byte active interrupt vectors
0x0000 0200 0x0000 0000
002aae723
LPC1311/13/42/43 memory
Nested Vectored Interrupt Controller (NVIC)
Nested Vectored Interrupt Controller (NVIC) integral part Cortex-M3. tight coupling allows interrupt latency efficient processing late arriving interrupts.
7.6.1 Features
Controls system exceptions peripheral interrupts. LPC1311/13/42/43, NVIC supports vectored interrupts. addition,
individual GPIO inputs NVIC-vector capable.
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programmable interrupt priority levels, with hardware priority level masking Relocatable vector table. Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device interrupt line connected NVIC have several interrupt flags. Individual interrupt flags also represent more than interrupt source. GPIO (total pins) regardless selected function, programmed generate interrupt level, rising edge falling edge, both.
IOCONFIG block
IOCONFIG block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between on-chip peripherals. Peripherals should connected appropriate pins prior being activated prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back well current state port pins. LPC1311/13/42/43 accelerated GPIO functions:
GPIO registers dedicated peripheral accessed through
that fastest possible timing achieved.
Entire port value written instruction.
Additionally, GPIO (total pins) providing digital function programmed generate interrupt level, rising falling edge, both.
7.8.1 Features
Bit-level clear registers allow single instruction clear number
bits port.
Direction control individual bits. default inputs with pull-up resistors enabled after reset. Pull-up/pull-down resistor configuration programmed through IOCONFIG
block each GPIO pin.
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interface (LPC1342/43 only)
Universal Serial (USB) 4-wire that supports communication between host more 127) peripherals. host controller allocates bandwidth attached devices through token-based protocol. supports hot-plugging dynamic configuration devices. transactions initiated host controller. LPC1342/43 interface device controller with on-chip device functions.
7.9.1 Full-speed device controller
device controller enables Mbit/s data exchange with Host controller. consists register interface, serial interface engine, endpoint buffer memory. serial interface engine decodes data stream writes data appropriate endpoint buffer. status completed transfer error condition indicated status registers. interrupt also generated enabled. 7.9.1.1 Features
Fully compliant with specification (full speed). Supports physical logical) endpoints with bytes buffer
endpoint (see Table
Supports Control, Bulk, Isochronous, Interrupt endpoints. Supports SoftConnect feature. Double buffer implementation Bulk Isochronous endpoints.
Table Logical endpoint device endpoint configuration Physical endpoint Endpoint type Control Control Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Interrupt/Bulk Isochronous Isochronous Direction Packet size (byte) Double buffer
7.10 UART
LPC1311/13/42/43 contains UART. Support RS-485/9-bit mode allows both software address detection automatic address detection using 9-bit mode. UART includes fractional baud rate generator. Standard baud rates such 115200 achieved with crystal frequency above MHz.
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7.10.1 Features
16-byte receive transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points
Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values. mechanism that enables software flow control implementation.
Fractional divider baud rate control, auto baud capabilities FIFO control Support RS-485/9-bit mode. Support modem control. 7.11 serial controller
LPC1311/13/42/43 contain controller. controller capable operation SSP, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. practice, often only these data flows carries meaningful data.
7.11.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, National
Semiconductor Microwire buses
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive 4-bit 16-bit frame
7.12 I2C-bus serial controller
LPC1311/13/42/43 contain I2C-bus controller. I2C-bus bidirectional inter-IC control using only wires: serial clock line (SCL) serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master controlled more than master connected
7.12.1 Features
I2C-bus interface standard I2C-bus compliant interface with open-drain pins.
I2C-bus interface also supports Fast-mode Plus with rates Mbit/s.
Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves.
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Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial
data bus. serial bus. resume serial transfer.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend I2C-bus used test diagnostic purposes. I2C-bus controller supports multiple address recognition monitor mode. 7.13 10-bit
LPC1311/13/42/43 contains ADC. single 10-bit successive approximation with eight channels.
7.13.1 Features
10-bit successive approximation ADC. Input multiplexing among pins. Power-down mode. Measurement range VDD(3V3). 10-bit conversion time 2.44 Burst conversion mode single multiple inputs. Optional conversion transition input timer match signal. Individual result registers each channel reduce interrupt overhead.
7.14 General purpose external event counters/timers
LPC1311/13/42/43 includes 32-bit counter/timers 16-bit counter/timers. counter/timer designed count cycles system derived clock. optionally generate interrupts perform other actions specified timer values, based four match registers. Each counter/timer also includes capture input trap timer value when input signal transitions, optionally generating interrupt.
7.14.1 Features
32-bit/16-bit timer/counter with programmable 32-bit/16-bit prescaler. Counter timer operation. capture channel timer, that take snapshot timer value when
input signal transitions. capture event also generate interrupt.
Four match registers timer that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four external outputs corresponding match registers, with following
capabilities:
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match. HIGH match. Toggle match. nothing match.
7.15 System tick timer
Cortex-M3 includes system tick timer (SYSTICK) that intended generate dedicated SYSTICK exception, normally interval.
7.16 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
7.16.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) (Tcy(WDCLK) multiples Tcy(WDCLK) (IRC), watchdog oscillator, main clock. This gives wide range potential timing choices watchdog operation under different power reduction conditions. also provides ability from entirely internal source that dependent external crystal associated components wiring increased reliability.
Watchdog Clock (WDCLK) source selected from Internal oscillator
7.17 Clocking power control
7.17.1 Crystal oscillators
LPC1311/13/42/43 include three independent oscillators. These system oscillator, Internal oscillator (IRC), watchdog oscillator. Each oscillator used more than purpose required particular application. Following reset, LPC1311/13/42/43 will operate from internal oscillator until switched software. This allows systems operate without external crystal bootloader code operate known frequency. Figure overview LPC1311/13/42/43 clock generation.
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system clock
clock (system)
SYSTEM CLOCK DIVIDER
clock (ROM) AHBCLKCTRL (AHB clock enable)
clocks (memories peripherals) clock (IOCONFIG)
AHBCLKCTRL
AHBCLKCTRL PERIPHERAL CLOCK DIVIDER main clock UART PERIPHERAL CLOCK DIVIDER TRACE CLOCK DIVIDER SYSTICK TIMER CLOCK DIVIDER SYSTEM oscillator CLOCK DIVIDER watchdog oscillator WDTUEN (WDT clock update enable) system oscillator CLOCK DIVIDER UART
oscillator
watchdog oscillator
MAINCLKSEL (main clock select) oscillator system oscillator watchdog oscilllator SYSPLLCLKSEL (system clock select)
trace clock SYSTICK timer
USBPLLCLKSEL (USB clock select)
USBUEN (USB clock update enable) oscillator system oscillator watchdog oscillator CLKOUT CLOCK DIVIDER
CLKOUT
CLKOUTUEN (CLKOUT update enable)
002aae859
clock available LPC1342/43 only.
LPC1311/13/42/43 clocking generation block diagram
7.17.1.1
Internal oscillator used clock source WDT, and/or clock that drives system subsequently CPU. nominal frequency MHz. trimmed accuracy over entire voltage temperature range.
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Upon power-up, chip reset, wake-up from Deep power-down mode, LPC1311/13/42/43 clock source. Software later switch other available clock sources.
7.17.1.2
System oscillator
system oscillator used clock source CPU, with without using PLL. LPC134x, system oscillator must used provide clock source USB.
system oscillator operates frequencies MHz. This frequency boosted higher frequency, maximum operating frequency, system PLL. processor clock frequency referred CCLK elsewhere this document.
7.17.2 System
LPC134x contain system dedicated generating clock. LPC131x contain system only. system PLLs identical. accepts input clock frequency range MHz. input frequency multiplied high frequency with Current Controlled Oscillator (CCO). multiplier integer value from operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip reset enabled software. program must configure activate PLL, wait lock, then connect clock source. settling time
7.17.3 Clock output
LPC1311/13/42/43 features clock output function that routes oscillator, system oscillator, watchdog oscillator, main clock output pin.
7.17.4 Wake-up process
LPC1311/13/42/43 begin operation power-up when awakened from Deep power-down mode using oscillator clock source. This allows chip operation resume quickly. main oscillator needed application, software will need enable these features wait them stabilize before they used clock source.
7.17.5 Power control
LPC1311/13/42/43 support variety power control features. There three special modes processor power reduction: Sleep mode, Deep-sleep mode, Deep power-down mode. clock rate also controlled needed changing clock sources, reconfiguring values, and/or altering clock divider value. This allows trade-off power versus processing speed based application requirements. addition, register provided shutting down clocks individual on-chip
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32-bit Cortex-M3 microcontroller
peripherals, allowing fine tuning power consumption eliminating dynamic power peripherals that required application. Selected peripherals have their clock divider which provides even better power control.
7.17.5.1
Sleep mode
When Sleep mode entered, clock core stopped. Resumption from Sleep mode does need special sequence re-enabling clock core. Sleep mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Sleep mode generate interrupts cause processor resume execution. Sleep mode eliminates dynamic power used processor itself, memory systems related controllers, internal buses. 7.17.5.2 Deep-sleep mode
Deep-sleep mode, chip Sleep mode, addition analog blocks shut down increased power savings. user configure Deep-sleep mode large extend, selecting oscillators, PLLs, (LPC134x only), BOD, ADC, flash shut down remain powered during Deep-sleep mode. user also select which oscillators analog blocks will powered after chip exits from Deep-sleep mode. GPIO pins pins total) serve external wake-up pins dedicated start logic wake chip from Deep-sleep mode. timing wake-up process from Deep-sleep mode depends which blocks selected powered down during deep-sleep. lowest power consumption, clock source should switched before entering Deep-sleep mode, oscillators PLLs should turned during deep-sleep, should selected clock source when chip wakes from deep-sleep. switched glitch-free provides clean clock signal after start-up. power consumption concern, oscillators and/or PLLs left running Deep-sleep mode obtain short wake-up times when waking from deep-sleep. 7.17.5.3 Deep power-down mode Deep power-down mode, power shut entire chip with exception WAKEUP pin. LPC1311/13/42/43 wake from Deep power-down mode WAKEUP pin.
7.18 System control
7.18.1 Reset
Reset four sources LPC1311/13/42/43: RESET pin, Watchdog reset, power-on reset (POR), Brown-Out Detection (BOD) circuit. RESET Schmitt trigger input pin. Assertion chip reset source, once operating voltage attains usable level, starts initializes flash controller.
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32-bit Cortex-M3 microcontroller
When internal reset removed, processor begins executing address which initially reset vector mapped from boot block. that point, processor peripheral registers have been initialized predetermined values.
7.18.2 Brownout detection
LPC1311/13/42/43 includes four levels monitoring voltage VDD(3V3) pin. this voltage falls below four selected levels, asserts interrupt signal NVIC. This signal enabled interrupt Interrupt Enable Register NVIC order cause interrupt; not, software monitor signal reading dedicated status register. additional threshold level selected cause forced reset chip.
7.18.3 Code security (Code Read Protection CRP)
This feature LPC1311/13/42/43 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection: CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using PIO0_1 pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
addition three levels, sampling PIO0_1 valid user code disabled. details LPC13xx user manual.
7.18.4 Boot loader
boot loader controls initial operation after reset also provides means program flash memory. This could initial programming blank device, erasure re-programming previously programmed device, programming flash memory application program running system. boot loader code executed every time part reset powered loader either execute command handler user application code, LPC134x, obtain boot image attached device through USB.
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level during reset PIO0_1 considered external hardware request start command handler device enumeration. state PIO0_3 determines whether UART interface will used (LPC134x only).
7.18.5 interface
peripherals located bus.
7.18.6 AHB-Lite
AHB-Lite connects instruction (I-code) data (D-code) buses Cortex-M3 flash memory, main static RAM, boot ROM.
7.18.7 External interrupt inputs
GPIO pins level edge sensitive interrupt inputs.
7.18.8 Memory mapping control
Cortex-M3 incorporates mechanism that allows remapping interrupt vector table alternate locations memory map. This controlled Vector Table Offset Register contained NVIC. vector table located anywhere within bottom Cortex-M3 address space. vector table must located word (512 byte) boundary because NVIC LPC1311/13/42/43 configured total interrupts.
7.19 Emulation debugging
Debug functions integrated into Cortex-M3. Serial wire debug supported.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VDD(IO) Parameter supply voltage (3.3 input/output supply voltage input voltage tolerant pins; only valid when VDD(IO) supply voltage present supply ground -(0.5VDD(IO)) (1.5VDD(IO)); Tstg Tj(max) Ptot(pack) storage temperature maximum junction temperature total power dissipation (per package) based package heat transfer, device power consumption human body model; pins
Conditions core external rail
-0.5
+5.5
Unit
Ilatch
supply current ground current latch-up current
+150
electrostatic discharge voltage
-5000
+5000
following applies limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
Including voltage outputs 3-state mode. peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
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Static characteristics
Table Static characteristics Tamb unless otherwise specified. Symbol VDD(3V3) VDD(IO) Parameter supply voltage (3.3 input/output supply voltage supply current Active mode; VDD(3V3) Tamb code Conditions Typ[1]
Unit
while(1){}
executed from flash; CCLK CCLK Sleep mode; VDD(3V3) Tamb
[2][3][4] [3][4][5] [2][3][4]
while(1){}
executed from flash; CCLK Deep-sleep mode; VDD(3V3) Tamb Deep power-down mode; VDD(3V3) VDD(IO) Tamb IDD(IO) supply current Deep power-down mode; VDD(3V3) VDD(IO) Tamb
[7][8]
Standard port pins RESET pin; Figure Figure LOW-level input current on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage
[12]
VDD(IO); on-chip pull-down resistor disabled VDD(IO); on-chip pull-up/down resistors disabled configured provide digital function output active
[9][10] [11]
Vhys
VDD(IO)
VDD(IO)
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Table Static characteristics .continued Tamb unless otherwise specified. Symbol IOHS IOLS Parameter LOW-level output voltage HIGH-level output current LOW-level output current Conditions VDD(IO)
[12]
Typ[1]
Unit
[12]
[12]
HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current VDD(IO) VDD(IO)
[13]
[13]
High-drive output (PIO0_7); Figure Figure LOW-level input current on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current pull-down current pull-up current VDD(IO) VDD(IO) VDD(IO) I2C-bus Vhys
LPC1311_13_42_43_0
VDD(IO); on-chip pull-down resistor disabled VDD(IO); on-chip pull-up/down resistors disabled configured provide digital function output active
[9][10] [11]
Vhys
0.5VDD(IO)
VDD(IO) 0.3VDD(IO)
[12]
VDD(IO) 0.7VDD(IO)
[12]
[12]
[12]
pins (PIO0_4 PIO0_5); Figure HIGH-level input voltage LOW-level input voltage hysteresis voltage
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Table Static characteristics .continued Tamb unless otherwise specified. Symbol Oscillator pins Vi(xtal) Vo(xtal) VBUS Vth(rs)se crystal input voltage crystal output voltage OFF-state output current supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage HIGH-level output voltage low-/full-speed; driven; low-/full-speed; GN[15]
Parameter LOW-level output voltage input leakage current
Conditions IOLS VDD(IO)
[12]
Typ[1]
1.95 1.95 5.25
Unit
[14]
pins (LPC1342/43 only) |(D+) (D-)| includes range
Ctrans ZDRV
0.18 44.1
transceiver capacitance driver output with series resistor; impedance driver steady state drive which high-speed capable
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. enabled; system oscillator disabled; system disabled. disabled. peripherals disabled AHBCLKCTRL register. Peripheral clocks UART, SSP, trace clock, SysTick timer disabled syscon block. disabled; system oscillator enabled; system enabled. oscillators analog blocks turned PDRUNCFG register. Main regulator reduced power mode. WAKEUP pulled HIGH externally; LPC134x: USB_DP USB_DM pulled externally. Including voltage outputs 3-state mode.
[10] VDD(3V3) VDD(IO) supply voltages must present. [11] 3-state outputs into 3-state mode when VDD(IO) grounded. [12] Accounts voltage drop supply lines. [13] Allowed long current limit does exceed maximum current allowed device. [14] VSS. [15] Includes external resistors USB_DP USB_DM.
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Table static characteristics Tamb unless otherwise specified; frequency MHz, VDD(3V3) Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2]
VDD(3V3)
Unit
monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
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offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDD(3V3) 1024
002aae787
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
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static characteristics
Table static characteristics[1] Tamb Symbol Parameter threshold voltage Conditions interrupt level assertion de-assertion interrupt level assertion de-assertion interrupt level assertion de-assertion interrupt level assertion de-assertion reset level assertion de-assertion
1.69 1.84 2.29 2.44 2.59 2.74 2.87 2.98 1.49 1.64
Unit
Interrupt levels selected writing level value control register BODCTRL, LPC13xx user manual.
Power consumption
(mA)
002aae993
VDD(3V3)
Conditions: Tamb active mode entered executing code while(1){} from flash; VDD(3V3) internal pull-up resistors disabled; system oscillator system enabled; IRC, disabled; peripherals disabled AHBCLKCTRL register (AHBCLKCTRL 0x1F); peripheral clocks disabled.
Typical supply current versus regulator supply voltage VDD(3V3) active mode
LPC1311_13_42_43_0
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Semiconductors
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32-bit Cortex-M3 microcontroller
(mA)
002aae994
temperature (°C)
Conditions: Active mode entered executing code while(1){} from flash; VDD(3V3) internal pull-up resistors disabled; system oscillator system enabled; IRC, disabled; peripherals disabled AHBCLKCTRL register (AHBCLKCTRL 0x1F); peripheral clocks disabled.
Typical supply current versus temperature active mode
(mA)
002aae995
temperature (°C)
Conditions: VDD(3V3) Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator system enabled; IRC, disabled; peripherals disabled AHBCLKCTRL register (AHBCLKCTRL 0x1F); peripheral clocks disabled.
Typical supply current versus temperature Sleep mode
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32-bit Cortex-M3 microcontroller
(mA)
002aae997
VDD(3V3)
temperature (°C)
Conditions: main regulator reduced power mode; disabled; analog blocks enabled PDSLEEPCFG register.
Typical supply current versus temperature Deep-sleep mode (analog blocks enabled)
VDD(3V3)
002aae998
temperature (°C)
Conditions: main regulator reduced power mode; disabled; analog blocks disabled PDSLEEPCFG register.
Typical supply current versus temperature Deep-sleep mode (analog blocks disabled)
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32-bit Cortex-M3 microcontroller
1000 (nA)
002aae996
VDD(3V3)
temperature (°C)
Typical supply current versus temperature Deep power-down mode Table Power consumption Deep-sleep mode individual analog blocks Tamb VDD(3V3) Analog block enabled PDSLEEPCFG register System System oscillator output
Conditions
Typical IDD[1]
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. other blocks disabled PDSLEEPCFG register; main regulator reduced power mode.
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Electrical characteristics
002aae990
(mA)
Conditions: VDD(3V3) VDD(IO) PIO0_7.
High-drive output: Typical HIGH-level output voltage versus HIGH-level output current IOH.
(mA)
002aaf019
Conditions: VDD(3V3) VDD(IO) pins PIO0_4 PIO0_5.
I2C-bus pins (high current sink): Typical LOW-level output current versus LOW-level output voltage
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32-bit Cortex-M3 microcontroller
(mA)
002aae991
Conditions: VDD(3V3) VDD(IO) standard port pins PIO0_7.
Typical LOW-level output current versus LOW-level output voltage
002aae992
(mA)
Conditions: VDD(3V3) VDD(IO) standard port pins.
Typical HIGH-level output voltage versus HIGH-level output source current
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32-bit Cortex-M3 microcontroller
002aae988
Conditions: VDD(3V3) VDD(IO) standard port pins.
Typical pull-up current versus input voltage
002aae989
Conditions: VDD(3V3) VDD(IO) standard port pins.
Typical pull-down current versus input voltage
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32-bit Cortex-M3 microcontroller
Dynamic characteristics
10.1 Flash memory
Table Flash characteristics Tamb unless otherwise specified. Symbol Nendu tret Parameter endurance retention time powered unpowered
Number program/erase cycles.
Conditions
10000
Unit cycles years years
10.2 External clock
Table Dynamic characteristic: external clock Tamb VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
1000
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
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32-bit Cortex-M3 microcontroller
10.3 Internal oscillators
Table Dynamic characteristic: internal oscillators Tamb VDD(3V3) V[1]. Symbol fosc(RC)
Parameter internal oscillator frequency
Conditions
11.88
Typ[2]
12.12
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages.
12.15 (MHz) 12.05 VDD(3V3)
002aae987
11.95
11.85
temperature (°C)
Conditions: Frequency values typical values. accuracy guaranteed VDD(3V3) Tamb Variations between parts cause fall outside accuracy specification voltages below
Internal oscillator frequency temperature
10.4 I2C-bus
Table Dynamic characteristic: I2C-bus pins (Fast-mode Plus) Tamb VDD(3V3) VDD(IO) V.[1][2][3] Symbol fSCL tSU;DAT
Parameter clock frequency fall time data set-up time
Conditions
Unit
Parameters valid over operating temperature range unless otherwise specified. Main clock frequency MHz; system clock divider AHBCLKDIV 0x1; I2C-bus interface configured master mode. capacitance external pull-up resistance
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32-bit Cortex-M3 microcontroller
tLOW
tHIGH tSU;DAT
002aae860
I2C-bus pins clock timing
10.5 interface
Table Symbol Tcy(PCLK) Tcy(clk) master tv(Q) th(Q) slave tv(Q) th(Q)
Dynamic characteristics pins mode Parameter PCLK cycle time clock cycle time data set-up time data hold time data output valid time data output hold time data set-up time data hold time data output valid time data output hold time mode mode mode mode mode mode mode mode
Conditions
13.9 27.8 Tcy(PCLK)
Tcy(clk) Tcy(PCLK) Tcy(PCLK)
Unit
[3][4] [3][4] [3][4] [3][4]
Tcy(clk) (SSPCLKDIV SCR) CPSDVSR) fmain. clock cycle time derived from rate Tcy(clk) function main clock frequency fmain, peripheral clock divider (SSPCLKDIV), parameter (specified SSP0CR0 register), CPSDVSR parameter (specified clock prescale register). Tamb VDD(3V3) VDD(IO) Tcy(clk) Tcy(PCLK). Tamb VDD(3V3) VDD(IO)
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32-bit Cortex-M3 microcontroller
Tcy(clk)
tclk(H)
tclk(L)
(CPOL
(CPOL tv(Q) MOSI DATA VALID DATA VALID MISO DATA VALID DATA VALID CPHA th(Q)
tv(Q) MOSI DATA VALID DATA VALID MISO DATA VALID DATA VALI
th(Q)
CPHA
002aae829
master timing mode
LPC1311_13_42_43_0
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32-bit Cortex-M3 microcontroller
Tcy(clk)
tclk(H)
tclk(L)
(CPOL
(CPOL MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID DATA VALID th(Q) CPHA
MOSI DATA VALID tv(Q) MISO DATA VALI
DATA VALID th(Q) DATA VALID CPHA
002aae830
slave timing mode
LPC1311_13_42_43_0
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Preliminary data sheet
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32-bit Cortex-M3 microcontroller
10.6 interface (LPC1342/43 only)
Table Dynamic characteristics: pins (full-speed) VDD(3V3), unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
13.8 13.7 +18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SE0/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
LPC1311_13_42_43_0
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Preliminary data sheet
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32-bit Cortex-M3 microcontroller
Application information
11.1 Suggested interface solutions (LPC1342/43 only)
VDD(IO)
USB_CONNECT
LPC134x
soft-connect switch
USB_VBUS USB_DP USB_DM VSSIO
002aae608
USB-B connector
LPC1342/43 interface self-powered device
VDD(IO)
LPC134x
USB_VBUS USB_DP USB_DM VSSIO
USB-B connector
002aae609
LPC1342/43 interface bus-powered device
11.2 XTAL input
input voltage on-chip oscillators limited oscillator driven clock slave mode, recommended that input coupled through capacitor with limit input voltage specified range, choose additional capacitor ground which attenuates input voltage factor Ci/(Ci Cg). slave mode, minimum mV(RMS) needed.
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Preliminary data sheet
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32-bit Cortex-M3 microcontroller
LPC1xxx
XTALIN
002aae788
Slave mode operation on-chip oscillator
11.3 XTAL Printed Circuit Board (PCB) layout guidelines
crystal should connected close possible oscillator input output pins chip. Take care that load capacitors Cx1,Cx2, case third overtone crystal usage have common ground plane. external components must also connected ground plain. Loops must made small possible order keep noise coupled small possible. Also parasitics should stay small possible. Values should chosen smaller accordingly increase parasitics layout.
11.4 Standard configuration
Figure shows possible modes standard pins. pull-up pull-down resistors (Rpu Rpd) enabled disabled. default value each standard port input with enabled. details modes hysteresis control, LPC13xx user manual.
VDD(IO)
enable output
input
hysteresis control
002aae828
Standard configuration
LPC1311_13_42_43_0
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Preliminary data sheet
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32-bit Cortex-M3 microcontroller
Package outline
LQFP48: plastic profile quad flat package; leads; body
SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
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Preliminary data sheet
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Semiconductors
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32-bit Cortex-M3 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
terminal index area
detail
terminal index area
Dimensions Unit A(1) D(1) 4.85 4.70 4.55 E(1)
scale
1.00 0.05 0.35 0.85 0.02 0.28 0.80 0.00 0.23
0.75 4.85 4.70 0.65 4.55 4.55 0.60 0.45 4.55
0.05 0.08
Note Plastic metal protrusions 0.075 maximum side included. Outline version References JEDEC JEITA -European projection
hvqfn33_po
Issue date 09-03-17 09-03-23
Package outline (HVQFN33)
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Preliminary data sheet
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32-bit Cortex-M3 microcontroller
Abbreviations
Table Acronym AMBA EFIFO GPIO UART Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral BrownOut Detection Packet Embedded Trace Macrocell First-In, First-Out General Purpose Input/Output Input/Output Least Significant Mass Storage Class Physical Layer Phase-Locked Loop Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Start-of-Frame Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial
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32-bit Cortex-M3 microcontroller
Revision history
Table Revision history Release date <tbd> Data sheet status Change notice Supersedes Preliminary data sheet Document LPC1311_13_42_43_0
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32-bit Cortex-M3 microcontroller
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
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32-bit Cortex-M3 microcontroller
Contents
7.6.1 7.6.2 7.8.1 7.9.1 7.9.1.1 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 General description Features Applications Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview Cortex-M3 processor On-chip flash program memory On-chip SRAM Memory map. Nested Vectored Interrupt Controller (NVIC) Features Interrupt sources. IOCONFIG block Fast general purpose parallel Features interface (LPC1342/43 only) Full-speed device controller Features UART Features serial controller Features I2C-bus serial controller Features 10-bit Features General purpose external event counters/timers 7.14.1 Features 7.15 System tick timer 7.16 Watchdog timer. 7.16.1 Features 7.17 Clocking power control 7.17.1 Crystal oscillators 7.17.1.1 Internal oscillator 7.17.1.2 System oscillator 7.17.2 System 7.17.3 Clock output 7.17.4 Wake-up process 7.17.5 Power control 7.17.5.1 Sleep mode
7.17.5.2 Deep-sleep mode. 7.17.5.3 Deep power-down mode 7.18 System control 7.18.1 Reset 7.18.2 Brownout detection 7.18.3 Code security (Code Read Protection CRP) 7.18.4 Boot loader. 7.18.5 interface 7.18.6 AHB-Lite 7.18.7 External interrupt inputs 7.18.8 Memory mapping control 7.19 Emulation debugging Limiting values Static characteristics static characteristics Power consumption Electrical characteristics. Dynamic characteristics. 10.1 Flash memory 10.2 External clock. 10.3 Internal oscillators 10.4 I2C-bus 10.5 interface 10.6 interface (LPC1342/43 only) Application information 11.1 Suggested interface solutions (LPC1342/43 only) 11.2 XTAL input 11.3 XTAL Printed Circuit Board (PCB) layout guidelines. 11.4 Standard configuration Package outline. Abbreviations Revision history Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
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more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: October 2009 Document identifier: LPC1311_13_42_43_0

LPC1311/13/42/43 Rev. 00.17 October 2009 32-bit Cortex-M3 mi

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