JPEG-D Baseline JPEG Decoder Megafunction Implements high-pe

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JPEG-D Baseline JPEG Decoder Megafunction Implements high-pe

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Baseline ISO/IEC 10918-1 JPEG Compliance
JPEG-D
Baseline JPEG Decoder Megafunction
Implements high-performance image video decoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG megafunctions, JPEG-D provides highperformance solution variety image video decompression applications. can, example, decode 16:9 HDTV, 1920x1152, 4:2:0. addition processing baseline JPEG streams, megafunction decompress non-standard motion JPEG streams. also enhanced with optional IDCT block that enables down-scaling frequency domain, feature that allows decompression various resolutions from same compressed stream. megafunction includes FIFO-like pixel stream input/output interfaces, other standard interfaces (e.g. AMBA) also available. megafunction designed reliability ease integration, been proven number ASIC FPGA designs. deliverables include software bit-accurate model that facilitates system chip verification.
Programmable Huffman Tables
(two
Programmable quantization
tables (four)
four color components
(optionally extendable components)
Supports possible scan confi-
gurations JPEG formats input/output data
Supports image size
Supports restart mark-
Additional Image Processing Capabilities
Motion JPEG decoding Decompressing various reso-
lutions downscaling frequency domain (optional)
Designed Easy Integration
Stand alone operation Automatic self-programming
Applications
high-performance JPEG-D megafunction suitable implementing variety multimedia applications, including: Digital cameras camcorders Office automation equipment (multifunction printers, scanners, digital copiers etc) Medical imaging systems Video production suites Video conference display-projection systems Surveillance systems
JPEG stream headers parsing
Header errors catching Broadcasting decoded image
parameters controlling peripherals such raster block converter
Designed High Quality
Robust verification environment
includes bit-accurate software model
ASIC FPGA proven mul-
tiple designs
Scan-ready design architecture
Block Diagram
Register File Frame, Scan, Parameters JPEG Stream Stream Parser Huffman Decoder Control Unit Image Data
UnStuff
FIFO
Expand DIFF decode
ZZ-1
IDCT
Huffman Tables
Quant. Tables
IDCT Buffer
JPEG-D
January 2008
Functional Description
decoding path highly autonomous, since JPEG-D self-configured (with table, image format encoding options) parsing incoming JPEG stream's headers. megafunction parses checks JPEG marker segments signals case detects error. Decoded image parameters made available controlling peripherals such block-to-raster converter. Designed continuous data flow, JPEG-D address most demanding frame-based video decompression applications. Optional decoding various resolutions from same JPEG data-stream without need extra buffering enabled when IDCT block configured during synthesis support downscaling frequency domain.
Support
megafunction delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Verification
megafunction been verified through extensive simulation rigorous code coverage measurements. also been embedded several products, proven both ASIC FPGA technologies.
Deliverables
megafunction available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. Altera version includes: Post-synthesis EDIF netlist Sophisticated self-checking Testbench (Verilog versions Verilog 2001) Simulation script, vectors, expected results, comparison utility Software (C++) Bit-Accurate Model Place route script Comprehensive user documentation, including detailed specifications system integration guide
Implementation Results
JPEG-D reference designs have been evaluated variety technologies. following sample Altera results obtained after speed optimization during synthesis place route, while assuming that megafunction I/Os routed off-chip.
Altera Device Apex 20KE EP20K400E-1 Apex-II EP2A15-C7 Cyclone EP1C12-C6 Cyclone-II EP2C8-C6 Stratix EP1S10-C5 Stratix-II EP2S15-C3 Hardcopy-II HC210 Logic 8,849 8,912 8,796 6,796 6,158 6,053 ALUTs 55,220 HCELLs Frequency Special Features M512 M512
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
This megafunction developed multimedia experts Alma Technologies S.A.

JPEG-D Baseline JPEG Decoder Megafunction Implements high-pe

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