Programmable Huffman Tables JPEG-C Baseline JPEG Codec Core

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Programmable Huffman Tables JPEG-C Baseline JPEG Codec Core

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Baseline ISO/IEC 10918-1 JPEG Compliance
Programmable Huffman Tables
JPEG-C
Baseline JPEG Codec Core
Implements high-performance, half-duplex image video encoder/decoder (codec) that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG cores, JPEG-C provides high-performance solution variety image video decompression applications. can, example, encode decode over frames/sec HDTV, 1440x1152, 4:2:0, even FPGA devices. typical 0.09µ process ASIC, core requires just 95,000 gates operates MHz. addition processing baseline JPEG streams, core compress decompress non-standard motion JPEG streams. also options. Encoding enhanced with optional add-on bit-rate control block, which benefit applications that have tight bandwidth constraints. Decoding enhanced with optional IDCT block that enables down-scaling frequency domain, feature that allows decompression various resolutions from same compressed stream. core includes FIFO-like pixel stream input/output interfaces, other standard interfaces (e.g. AMBA) also available. core designed reliability ease integration, been proven number ASIC FPGA designs. deliverables include software bit-accurate model that facilitates system-on-chip verification.
(two
Programmable quantization
tables four)
color components (op-
tionally extendable components)
Supports possible scan confi-
gurations JPEG formats input/output data
image size Supports restart mark-
Additional Image Processing Capabilities
Motion JPEG encoding/decoding Rate-Control (optional) Decompressing various reso-
lution downscaling frequency domain (optional)
Designed Easy Integration
Encoding Mode Single clock input sample Fully programmable through
standard JPEG stream marker segments
Automatic headers generation Automatic program-once
Applications
JPEG-C utilized variety multimedia applications including: Office automation equipment (Multifunction printers, scanners, digital copiers etc) Digital cameras camcorders Video production, video conference Display-projection systems Surveillance systems
code-many operation
Decoding Mode Stand-alone operation Automatic self-programming
JPEG stream headers parsing
Header errors catching Broadcasting decoded
Block Diagram
parameters controlling peripherals such raster block converter
Designed High Quality
Robust verification environment
includes bit-accurate software model
ASIC FPGA proven mul-
tiple designs
Scan-ready design architecture
March 2009
Functional Description
encoding, JPEG-C automatically configured feeding with JPEG headers, which contain table specification, image format, encoding options data. core's configuration modified after encoding multiple frames. Image samples color space format input JPEG-C block block, raster scan order. Consuming single clock cycle image sample while encoding, JPEG-C address most demanding framebased video compression applications. JPEG-C outputs complete JPEG-compliant data stream, including JPEG headers, size which dynamically controlled optional rate-control block used. JPEG-C's decoding path highly autonomous, since self-configured (with table, image format encoding options) parsing incoming JPEG stream's headers. core parses checks JPEG marker segments signals case detects error. Decoded image parameters made available controlling peripherals such block-to-raster converter. Designed continuous data flow decoding, JPEG-C address most demanding frame-based video decompression applications. Optional decoding various resolutions from same JPEG data-stream without need extra buffering enabled when IDCT block configured during synthesis support downscaling frequency domain.
Verification
core been verified through extensive simulation rigorous code coverage measurements. Being embedded numerous products, core silicon proven both FPGA ASIC technologies.
Deliverables
core available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. Actel version includes: Post-synthesis EDIF netlist Sophisticated self-checking Testbench (Verilog versions Verilog 2001) Simulation script, vectors, expected results, comparison utility Place route script Comprehensive user documentation, including detailed specifications system integration guide Software (C++) Bit-Accurate Model
Implementation Results
JPEG-C reference designs have been evaluated variety technologies. following sample Actel results core optimized speed.
Actel Device Axcelerator AX2000-2 Axcelerator RTAX2000S-1 Proasic Plus APA1000-STD Proasic3E A3P3000-2 Cells 24,112 24,310 45,791 44,299 7,511 7,698 8,049 11,759 Comb 16,601 16,612 37,742 32,540 Frequency Special Features
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2009, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
This core developed multimedia experts Alma Technologies S.A.

Programmable Huffman Tables JPEG-C Baseline JPEG Codec Core

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