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Programmable Huffman Tables JPEG-C Baseline JPEG Codec Megaf
Top Searches for this datasheetBaseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables JPEG-C Baseline JPEG Codec Megafunction Implements high-performance, half-duplex image video encoder/decoder (codec) that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG megafunctions, JPEG-C provides highperformance solution variety image video decompression applications. can, example, encode decode over frames/sec HDTV, 1440x1152, 4:2:0. addition processing baseline JPEG streams, megafunction compress decompress non-standard motion JPEG streams. also options. Encoding enhanced with optional add-on bit-rate control block, which benefit applications that have tight bandwidth constraints. Decoding enhanced with optional IDCT block that enables down-scaling frequency domain, feature that allows decompression various resolutions from same compressed stream. megafunction includes FIFO-like pixel stream input/output interfaces, other standard interfaces (e.g. AMBA) also available. megafunction designed reliability ease integration, been proven number ASIC FPGA designs. deliverables include software bit-accurate model that facilitates systemon-chip verification. (two Programmable quantization tables (four) color components (op- tionally extendable components) Supports possible scan confi- gurations JPEG formats input/output data image size Supports restart mark- Additional Image Processing Capabilities Motion JPEG encoding/decoding Rate-Control (optional) Decompressing various reso- lution downscaling frequency domain (optional) Designed Easy Integration Encoding Mode Single clock input sample Fully programmable through standard JPEG stream marker segments Automatic headers generation Automatic program-once Applications JPEG-C utilized variety multimedia applications including: Office automation equipment (Multifunction printers, scanners, digital copiers etc) Digital cameras camcorders Video production, video conference Display-projection systems Surveillance systems code-many operation Decoding Mode Stand-alone operation Automatic self-programming JPEG stream headers parsing Header errors catching Broadcasting decoded Block Diagram parameters controlling peripherals such raster block converter Designed High Quality Robust verification environment includes bit-accurate software model ASIC FPGA proven mul- tiple designs Scan-ready design architecture January 2008 Functional Description encoding, JPEG-C automatically configured feeding with JPEG headers, which contain table specification, image format, encoding options data. megafunction's configuration modified after encoding multiple frames. Image samples color space format input JPEG-C block block, raster scan order. Consuming single clock cycle image sample while encoding, JPEG-C address most demanding framebased video compression applications. JPEG-C outputs complete JPEG-compliant data stream, including JPEG headers, size which dynamically controlled optional rate-control block used. JPEG-C's decoding path highly autonomous, since self-configured (with table, image format encoding options) parsing incoming JPEG stream's headers. megafunction parses checks JPEG marker segments signals case detects error. Decoded image parameters made available controlling peripherals such block-to-raster converter. Designed continuous data flow decoding, JPEG-C address most demanding frame-based video decompression applications. Optional decoding various resolutions from same JPEG data-stream without need extra buffering enabled when IDCT block configured during synthesis support downscaling frequency domain. Support megafunction delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available. Verification megafunction been verified through extensive simulation rigorous code coverage measurements. Being embedded numerous products, megafunction silicon proven both FPGA ASIC technologies. Deliverables megafunction available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. Altera version includes: Post-synthesis EDIF netlist Sophisticated self-checking Testbench (Verilog versions Verilog 2001) Simulation script, vectors, expected results, comparison utility Place route script Comprehensive user documentation, including detailed specifications system integration guide Software (C++) Bit-Accurate Model Implementation Results JPEG-C reference designs have been evaluated variety technologies. following Altera results obtained after speed optimization during synthesis place route, while assuming that megafunction I/Os routed off-chip. Altera Device Apex 20KE EP20K400E-1 Apex-II EP2A15-C7 Stratix EP1S10-C5 Cyclone EP1C20-C6 Cyclone-II EP2C20-C6 Stratix-II EP2S30-C3 Hardcopy-II HC210 Logic 15,548 15,810 11,629 15,305 12,986 11,015 ALUTs 97,873 HCELLs Frequency Special Features M512 M512 CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. 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