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JPEG-E Baseline JPEG Encoder Core Implements high-performanc


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Baseline ISO/IEC 10918-1 JPEG Compliance
JPEG-E
Baseline JPEG Encoder Core
Implements high-performance image encoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG cores, JPEG-E provides high-performance solution variety image video compression applications. can, example, encode over frames/sec HDTV, 1440x1152, 4:2:0, FPGA devices. addition processing baseline JPEG streams, core compress non-standard motion JPEG streams. also enhanced with optional add-on bit-rate control block, which benefit applications that have tight bandwidth constraints. core includes FIFO-like pixel stream input/output interfaces. Other standard interfaces (e.g. AMBA) available. core designed reliability ease integration, been proven number ASIC FPGA designs. deliverables include software bit-accurate model that facilitates system chip verification.
Programmable Huffman Tables (two Programmable quantization tables (four) four color components (optionally extendable components) Supports possible scan configurations JPEG formats input/output data Supports image size Supports restart markers
Additional Image Processing Capabilities
Motion JPEG encoding/decoding Rate-Control (optional)
Designed Easy Integration
Single clock input sample encoding Fully programmable through standard JPEG stream marker segments Automatic headers generation Automatic program-once encode-many operation
Applications
high-performance JPEG-E core suitable implementing variety multimedia applications, including: Digital cameras camcorders Office automation equipment (multifunction printers, scanners, digital copiers etc) Medical imaging systems Video production suites Video conference display-projection systems Surveillance systems
Designed High Quality
Robust verification environment includes bit-accurate software model ASIC FPGA proven multiple designs Scan-ready design architecture
Block Diagram
October 2008
Functional Description
JPEG-E configured feeding with JPEG headers, which contain table specification, image format, encoding options data. core's configuration modified after encoding multiple frames. Image samples color space format input JPEG-E block block, raster scan order. Consuming single clock cycle image sample, JPEG-E address most demanding frame-based video compression applications. JPEG-E outputs complete JPEG-compliant data stream, including JPEG headers, size which dynamically controlled optional rate-control block used.
Deliverables
core available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. Lattice version includes: Post-synthesis EDIF netlist Sophisticated self-checking Testbench (Verilog versions Verilog 2001) Simulation script, vectors, expected results, comparison utility Software (C++) Bit-Accurate Model Place route script Comprehensive user documentation, including detailed specifications system integration guide
Implementation Results
JPEG-E reference designs have been evaluated variety technologies. following sample Lattice results optimized speed.
Lattice Device LFXP15-5 LFXP2-17E-7 LFEC15-5 LFECP10-5 ECP2 LFE2-12E-7 LFSC3GA15-7 Slices 4,187 3,209 4,187 3,156 3,223 4,287 MULT18X18, MULT9X9 MULT18X18, MULT9X9 MULT18X18, MULT9X9 Other I/Os Fmax (MHz)
Related Cores
SVE-JPEG-E SpeedView Enabled JPEG Encoder that produces SpeedView enabled JPEG data streams.
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Verification
core been verified through extensive simulation rigorous code coverage measurements. also been embedded several products, proven both ASIC FPGA technologies.
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
This core developed multimedia experts Alma Technologies S.A.

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