Output 1.5A Less High Efficiency Step-down Switching Regulators with B

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Output 1.5A Less High Efficiency Step-down Switching Regulators with B

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Single-chip built-in type Switching Regulator Series
Output 1.5A Less High Efficiency Step-down Switching Regulators with Built-in Power MOSFET
BD9102FVM, BD9104FVM, BD9106FVM
No.09027EAT34
Description ROHM's high efficiency step-down switching regulator (BD9102FVM, BD9104FVM, BD9106FVM) power supply designed produce voltage including 1.24 volts from volts power supply line. Offers high efficiency with original pulse skip control technology synchronous rectifier. Employs current mode control system provide faster transient response sudden change load. Features Offers fast transient response with current mode control system. Offers highly efficiency load range with synchronous rectifier (Nch/Pch FET) SLLM (Simple Light Load Mode) Incorporates soft-start function. Incorporates thermal protection ULVO functions. Incorporates short-current protection circuit with time delay function. Incorporates shutdown function Employs small surface mount package MSOP8 Power supply HDD, power supply portable electronic devices like PDA, power supply including ASIC Lineup Parameter voltage Output voltage Output current UVLO Threshold voltage Short-current protection with time delay function Soft start function Standby current Operating temperature range Package Absolute Maximum Rating (Ta=25) Parameter voltage PVCC voltage voltage SW,ITH voltage Power dissipation Power dissipation Operating temperature range Storage temperature range Maximum junction temperature
BD9102FVM 4.05.5V 1.24V±2% 0.8A Max. 2.7V Typ. built-in built-in Typ. -25+85 MSOP8
BD9104FVM 4.55.5V 3.30V±2% 0.9A Max. 4.1V Typ. built-in built-in Typ. -25+85 MSOP8
BD9106FVM 4.05.5V Adjustable(1.02.5V) 0.8A Max. 3.4V Typ. built-in built-in Typ. -25+85 MSOP8
Symbol PVCC SW,ITH Topr Tstg Tjmax
Limits -0.3+7 -0.3+7 -0.3+7 -0.3+7 387.5*2 587.4*3 -25+85 -55+150 +150
Unit
should exceeded. Derating done 3.1mW/ temperatures above Ta=25. Derating done 4.7mW/ temperatures above Ta=25,Mounted Glass Epoxy
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1/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Recommended Operating Conditions (Ta=25) BD9102FVM Parameter Symbol Min. Max. voltage PVCC voltage voltage average output current
should exceeded.
Technical Note
BD9104FVM Min. Max.
BD9106FVM Min. Max.
Unit
PVCC Isw*4
Electrical Characteristics BD9102FVM(Ta=25,VCC=5V,EN=VCC unless otherwise specified.) Parameter Symbol Min. Typ. Standby current Bias current voltage High voltage input current Oscillation frequency resistance resistance Output voltage SInk current Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
Max. 0.60 0.50 1.265
Unit
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V VOUT=H VOUT=L VCC=HL
ISTB VENL VENH FOSC RONP RONN VOUT ITHSI ITHSO VUVLOTh VUVLOHys TLATCH
1.215
0.35 0.25 1.24
Design GuaranteeOutgoing inspection done products
BD9104FVM(Ta=25,VCC=5V,EN=VCC unless otherwise specified.) Parameter Symbol Min. Typ. Standby current Bias current voltage High voltage input current Oscillation frequency resistance resistance Output voltage SInk current Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
Max. 0.60 0.50 3.366
Unit
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V VOUT=H VOUT=L VCC=HL
ISTB VENL VENH FOSC RONP RONN VOUT ITHSI ITHSO VUVLOTh VUVLOHys TLATCH
3.234
0.35 0.25 3.300
Design GuaranteeOutgoing inspection done products
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2/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
otherwise specified.) Parameter Symbol Min. Typ. Max. Standby current Bias current voltage High voltage input current Oscillation frequency resistance resistance reference voltage Output voltage SInk current Source Current UVLO threshold voltage UVLO hysteresis voltage Soft start time Timer latch time
Technical Note
Unit
Conditions EN=GND Standby mode Active mode VEN=5V PVCC=5V PVCC=5V
ISTB VENL VENH FOSC RONP RONN VADJ VOUT ITHSI ITHSO VUVLOTh VUVLOHys TLATCH
0.780
0.35 0.25 0.800 1.200
0.60 0.50 0.820
ADJ=H ADJ=L VCC=HL
Design GuaranteeOutgoing inspection done products
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3/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Characteristics data VCC-VOUT
Ta=25
OUTPUT VOLTAGE:VOUT[V]
Technical Note
[BD9102FVM]
OUTPUT VOLTAGE:VOUT[V]
Ta=25
[BD9104FVM]
OUTPUT VOLTAGE:VOUT[V]
Ta=25
[BD9106FVM]
INPUT VOLTAGE:VCC[V]
INPUT VOLTAGE:VCC[V]
INPUT VOLTAGE:VCC[V]
Fig.1 Vcc-Vout VEN-VOUT
OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V]
Fig.2 Vcc-Vout
Fig.3 Vcc-Vout
OUTPUT VOLTAGE:VOUT[V]
VCC=5V Ta=25
[BD9102FVM]
VCC=5V Ta=25
[BD9104FVM]
VCC=5V Ta=25
[BD9106FVM]
VOLTAGE:VEN[V]
VOLTAGE:VEN[V]
VOLTAGE:VEN[V]
Fig.4 Ven-Vout IOUT-VOUT
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
Fig.5 Ven-Vout
Fig.6 Ven-Vout
OUTPUT VOLTAGE:VOUT[V]
VCC=5V Ta=25
[BD9102FVM]
VCC=5V Ta=25
[BD9104FVM]
[BD9106FVM]
VCC=5V Ta=25
OUTPUT CURRENT:IOUT[A]
OUTPUT CURRENT:IOUT[A]
OUTPUT CURRENT:IOUT[A]
Fig.7 Iout-Vout Soft start
[BD9102FVM]
Fig.8 Iout-Vout
Fig.9 Iout-Vout
[BD9104FVM]
[BD9106FVM]
VCC=PVCC=EN
VCC=PVCC=EN
VCC=PVCC=EN
VOUT
Ta=25
VOUT
Ta=25
VOUT
Ta=25
Fig.10 Soft start waveform
Fig.11 Soft start waveform
Fig.12 Soft start waveform
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4/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
waveform IO=10mA
[BD9102FVM] [BD9104FVM]
Technical Note
[BD9106FVM]
VOUT
VCC=5V Ta=25
VOUT
VCC=5V Ta=25
VOUT
VCC=5V Ta=25
Fig.13 waveform Io=10mA(SLLM control) waveform IO=200mA
[BD9102FVM]
Fig.14 waveform Io=10mA(SLLMcontrol)
Fig.15 waveform Io=10mA(SLLMcontrol
[BD9104FVM]
[BD9106FVM]
VOUT
VCC=5V Ta=25
VOUT
VCC=5V Ta=25
VOUT
VCC=5V Ta=25
Fig.16 waveform Io=200mA(PWM control) Transient response IO=100mA 600mA
[BD9102FVM]
Fig.17 waveform Io=200mA(PWM control)
Fig.18 waveform Io=200mA(PWM control VOUT=1.8V)
[BD9104FVM]
[BD9106FVM]
VOUT
VOUT
VOUT
IOUT
VCC=5V Ta=25
IOUT
VCC=5V Ta=25
IOUT
VCC=5V Ta=25
Fig.19 Transient response Io=100600mA(10s) Transient response IO=600mA 100mA
[BD9102FVM]
Fig.20 Transient response Io=100600mA(10s)
Fig.21 Transient response Io=100600mA(10s) (VOUT=1.8V)
[BD9106FVM]
[BD9104FVM]
VOUT
VOUT
VOUT
IOUT
IOUT
VCC=5V Ta=25 VCC=5V Ta=25
IOUT
VCC=5V Ta=25
Fig.22 Transient response Io=600100mA(10s)
Fig.23 Transient response Io=600100mA(10s)
Fig.24 Transient response Io=600100mA(10s) (VOUT=1.8V)
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5/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Ta-VOUT
Technical Note
1.28 OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
1.85
OUTPUT VOLTAGE:VOUT[V]
1.27 1.26 1.25 1.24 1.23 1.22 1.21
VCC=5V
[BD9102FVM]
3.45 3.35 3.25 3.15 3.05
VCC=5V
[BD9104FVM]
1.84 1.83 1.82 1.81 1.79 1.78 1.77 1.76 1.75
VCC=5V
[BD9106FVM]
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig.25 Ta-VOUT Efficiency
EFFICIENCY:[%] EFFICIENCY:[%] OUTPUT CURRENT:IOUT[mA] 1000
Fig.26 Ta-VOUT
Fig.27 Ta-VOUT
Ta=25
[BD9102FVM]
Ta=25
EFFICIENCY:[%]
Ta=25
[BD9104FVM] OUTPUT CURRENT:IOUT[mA] 1000
[BD9106FVM]
OUTPUT CURRENT:IOUT[mA]
1000
Fig.28 Efficiency (VCC=EN=5V VOUT=1 24V) Reference characteristics
NMOS RESISTANCE:RONN[]
Fig.29 Efficiency (VCC=EN=5V,VOUT=3.3V)
Fig.30 Efficiency (VCC=EN=5V,VOUT=1.8V)
VCC=5V 0.35 0.25 0.15 0.05
VCC=5V
PMOS RESISTANCE:R ONP[]
1.15 FREQUENCY:FOSC[MHz] 1.05 0.95 0.85
0.35 0.25 0.15 0.05
VCC=5V
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig.31 Ta-FOSC
VOLTAGE:VEN[V]
Fig.32 Ta-RONN
Fig.33Ta-RONP
VCC=5V
CIRCUIT CURRENT:ICC[A]
VCC=5V
FREQUENCY:FOSC[MHz]
Ta=25
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
BD9102FVM BD9104FVM BD9106FVM
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
INPUT VOLTAGE:VCC[V]
Fig.34 Ta-VEN
Fig.35 Ta-ICC
Fig.36 Vcc-Fosc
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6/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Block diagram, Application circuit BD9102FVM,BD9104FVM
VREF VOUT PVCC PGND Amp. SLOPE Soft Start Current Comp. Driver Logic
Technical Note
Current Sense/ Protect
Input PVCC
4.7H
Output
View
UVLO
PGND
VOUT
Fig.37 BD9102FVM BD9104FVM View
BD9106FVM PVCC PGND
Fig.38 BD9102FVM BD9104FVM Block diagram
VREF Current Comp. Amp. SLOPE Driver Logic Current Sense/ Protect Input PVCC
4.7H
Output
View Soft Start
UVLO
PGND
Fig.39 BD9106FVM View function table
Fig.40 BD9106FVM Block diagram
name VOUT/ADJ PGND PVCC
function Output voltage detect pin/ BD9106FVM GmAmp output pin/Connected phase compensation capacitor Enable pin(Active High) Ground source Pch/Nch drain output source power supply input
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7/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
Information advantages Advantage 1Offers fast transient response with current mode control system. Conventional product (VOUT which volts) BD9104FVM(Load response IO=100mA600mA)
VOUT 228mV VOUT 110mV
IOUT
IOUT
Voltage drop sudden change load reduced 50%. Fig.41 Comparison transient response Advantage Offers high efficiency load range. lighter load: Utilizes current mode control mode called SLLM lighter load, which reduces various dissipation such switching dissipation (PSW), gate charge/discharge dissipation, dissipation output capacitor (PESR) on-resistance dissipation (PRON) that otherwise cause degradation efficiency lighter load.
Achieves efficiency improvement lighter load.
Efficiency
SLLM
heavier load: Utilizes synchronous rectifying mode on-resistance FETs incorporated power transistor. resistance P-channel FET: 0.35 (Typ.) resistance N-channel FET: 0.25 (Typ.)
inprovement SLLM system improvement synchronous rectifier
0.001
0.01 Output current Io[A]
Fig.42 Efficiency
Achieves efficiency improvement heavier load. Offers high efficiency load range with improvements mentioned above. Advantage 3Supplied smaller package like MOSP8 small-sized power incorporated. Allows reduction size application products Output capacitor required current mode control: ceramic capacitor Inductance required operating frequency MHz: inductor Reduces mounting area required.
15mm DC/DC Convertor Controller RITH VOUT 10mm CITH
RITH CITH
Fig.43 Example application
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8/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
Operation BD9102FVM, BD9104FVM, BD9106FVM synchronous rectifying step-down switching regulator that achieves faster transient response employing current mode control system. utilizes switching operation (Pulse Width Modulation) mode heavier load, while utilizes SLLM (Simple Light Load Mode) operation lighter load improve efficiency. Synchronous rectifier does require power dissipated rectifier externally connected conventional DC/DC converter junction shoot-through protection circuit limits shoot-through current during operation, which power dissipation reduced. Current mode control Synthesizes control signal with inductor current feedback loop added voltage feedback. (Pulse Width Modulation) control oscillation frequency MHz. signal form turns P-channel (while N-channel turned OFF), inductor current increases. current comparator (Current Comp) receives signals, current feedback control signal (SENSE: Voltage converted from voltage feedback control signal (FB), issues RESET signal both input signals identical each other, turns P-channel (while N-channel turned rest fixed period. control repeat this operation.
SLLM (Simple Light Load Mode) control When control mode shifted from heavier load lighter load vise versa, switching pulse designed turn with device held operated normal control loop, which allows linear operation without voltage drop deterioration transient response during mode switching from light load heavy load vise versa. Although control loop continues operate with signal from RESET signal from Current Comp, designed that RESET signal held issued shifted light load mode, with which switching tuned switching pulses thinned under control. Activating switching intermittently reduces switching dissipation improves efficiency.
SENSE Current Comp Level Shift Amp. RESET Driver Logic Load VOUT
VOUT
Fig.44 Diagram current mode control
PVCC SENSE IL(AVE) PVCC SENSE
Current Comp
Current Comp
RESET
RESET
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
switching
Fig.45 switching timing chart
Fig.46 SLLMswitching timing chart
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9/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
Description operations Soft-start function terminal shifted "High" activates soft-starter gradually establish output voltage with current limited during startup, which possible prevent overshoot output voltage inrush current. Shutdown function With terminal shifted "Low", device turns Standby Mode, function blocks including reference voltage circuit, internal oscillator drivers turned OFF. Circuit current during standby (Typ.). UVLO function Detects whether input voltage sufficient secure output voltage this supplied. hysteresis width (Typ.) provided prevent output chattering. BD9102FVM BD9104FVM TSS=1msec(typ.) BD9106FVM TSS=3msec(typ.)
Hysteresis 100mV
VOUT
Soft start Standby mode Operating mode Standby mode UVLO
Operating mode
Standby mode
Operating mode
Standby mode
UVLO
Fig.47 Soft start, Shutdown, UVLO timing chart
UVLO
Short-current protection circuit with time delay function Turns output protect from breakdown when incorporated current limiter activated continuously least output thus held tuned recovered restarting re-unlocking UVLO.
Output latch VOUT Limit 1msec Standby mode Standby mode Timer latch
Operating mode
Operating mode
Fig.48 Short-current protection circuit with time delay timing chart
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10/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Switching regulator efficiency Efficiency expressed equation shown below: POUT POUT POUT+PD
Technical Note
Efficiency improved reducing switching regulator power dissipation factors follows: Dissipation factors: resistance dissipation inductor FETPD(I Gate charge/discharge dissipationPD(Gate) Switching dissipationPD(SW) dissipation capacitorPD(ESR) Operating current dissipation ICPD(IC) 1)PD(I R)=IOUT (RCOIL[]DC resistance inductor, RON[]ON resistance IOUT[A]Output current.) (Cgs[F]Gate capacitance FET,f[H]Switching frequency,V[V]Gate driving voltage FET) 3)PD(SW)= IDRIVE (CRSS[F]Reverse transfer capacitance FET,IDRIVE[A]Peak current gate.)
4)PD(ESR)=IRMS (IRMS[A]Ripple current capacitor,ESR[]Equivalent series resistance.) (ICC[A]Circuit current.)
Consideration permissible dissipation heat generation this functions with high efficiency without significant heat generation most applications, special consideration needed permissible dissipation heat generation. case extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, permissible dissipation and/or heat generation must carefully considered. dissipation, only conduction losses resistance inductor resistance considered. Because conduction losses considered play leading role among other dissipation mentioned above including gate charge/discharge dissipation switching dissipation.
P=IOUT
1000
using alone
Power dissipation:Pd [mW]
duty (=VOUT/VCC) RCOILDC resistance coil RONPON resistance P-channel RONNON resistance N-channel IOUTOutput current VCC=5V, VOUT=3.3V, RCOIL=0.15, RONP=0.35, RONN=0.25 IOUT=0.8A, example, D=VOUT/VCC=3.3/5=0.66 =0.231+0.085 =0.316[] P=0.8 298[mV]
587.4mW
j-a=322.6/W
mounted glass epoxy
j-a=212.8/W
387.5mW
Fig.49 Thermal derating curves
Ambient temperature:Ta
RONP greater than RONN this dissipation increases duty becomes greater. With consideration dissipation above, thermal design must carried with sufficient margin allowed.
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11/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Selection components externally connected Selection inductor
Technical Note
VOUT
inductance significantly depends output ripple current. seen equation (1), ripple current decreases inductor and/or switching frequency increases. [A](1) Appropriate ripple current output should more less maximum output current. [A](2) [H](3) (IL: Output ripple current, Switching frequency)
Fig.50 Output ripple current
Current exceeding current rating inductor results magnetic saturation inductor, which decreases efficiency. inductor must selected allowing sufficient margin with which peak current exceed current rating.
VCC=5V, VOUT=3.3V, f=1MHz, example, =4.675 4.7[H]
*Select inductor resistance component (such ACR) minimize dissipation inductor better efficiency.
Selection output capacitor (CO)
Output capacitor should selected with consideration stability region equivalent series resistance required smooth ripple voltage. Output ripple voltage determined equation
VOUT
[V](4) (IL: Output ripple current, ESR: Equivalent series resistance output capacitor) *Rating capacitor should determined allowing sufficient margin against output voltage. Less allows reduction output ripple voltage.
Fig.51 Output capacitor
output rise time must designed fall within soft-start time, capacitance output capacitor should determined with consideration requirements equation (5): Tss: Soft-start time Ilimit: Over current detection level, 2A(Typ) VOUT case BD9104FVM, instance, VOUT=3.3V, IOUT=0.8A, TSS=1ms, Inappropriate capacitance cause problem startup. ceramic capacitor recommended. Selection input capacitor (Cin)
Input capacitor select must capacitor capacitance sufficient cope with high ripple current prevent high transient voltage. ripple current IRMS given equation (6): CC(VCC-VOUT) Worst case IRMS(max.) [A](6) IOUT
VOUT
When twice Vout, IRMS= Fig.52 Input capacitor
VCC=5V, VOUT=3.3V, IOUTmax.=0.8A, 5(5-3.3) =0.46[ARMS]
10F/10V ceramic capacitor recommended reduce dissipation input capacitor better efficiency.
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12/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
Determination RITH, CITH that works phase compensator Current Mode Control designed limit inductor current, pole (phase lag) appears frequency area filter consisting output capacitor load resistance, while zero (phase lead) appears high frequency area output capacitor ESR. phases easily compensated adding zero power amplifier output with described below cancel pole power amplifier.
fp(Min.) Gain [dB] fp(Max.) IOUTMin. IOUTMax. fz(ESR)
fz(ESR)= Pole power amplifier When output current decreases, load resistance increases pole frequency lowers. fp(Min.)= [Hz]with lighter load [Hz]with heavier load
Phase [deg]
Fig.53 Open loop gain characteristics fp(Max.)=
Gain [dB] fz(Amp.)
Zero power amplifier Increasing capacitance output capacitor lowers pole frequency while zero frequency does change. (This because when capacitance doubled, capacitor reduces half.) fz(Amp.)=
Phase [deg]
Fig.54 Error phase compensation characteristics
VOUT VOUT RITH CITH
VCC,PVCC
VOUT
GND,PGND
Fig.55 Typical application Stable feedback loop achieved canceling pole (Min.) produced output capacitor load resistance with zero correction error amplifier. fz(Amp.)= fp(Min.)
Determination output voltage (for BD9106FVM only) output voltage VOUT determined equation (7): VADJ: Voltage terminal (0.8V Typ.) With adjusted, output voltage determined required.(Adjustable output voltage range 1.0V2.5V) k100 resistor resistor resistance higher than100 used, check assembled carefully ripple voltage etc.
4.7H Output
Fig.56 Determination output voltage
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13/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
BD9102FVM, BD9104FVM, BD9106FVM Cautions Board layout
Technical Note
RITH CITH
VOUT/ADJ
PVCC PGND
VOUT
Fig.57 Layout diagram sections drawn with heavy line, thick conductor pattern short possible. input ceramic capacitor closer pins PVCC PGND, output capacitor closer PGND. CITH RITH between pins neat possible with least necessary wiring. Table1.Recommended parts list application [BD9102FVM] symbol part value manufacturer Inductor 4.7H Sumida CITH RITH Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor 330pF Kyocera Kyocera murata ROHM
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series MCR10 3002
Table2. Recommended parts list application [BD9104FVM] symbol part value manufacturer Inductor 4.7H Sumida CITH RITH Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor 330pF Kyocera Kyocera murata ROHM
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series MCR10 5102
Table3.Recommended parts list application [BD9106FVM] symbol part value manufacturer Inductor 4.7H Sumida CITH Ceramic capacitor Ceramic capacitor Ceramic capacitor 750pF Kyocera Kyocera murata
series CMD6D11B CM316X5R106M10A CM316X5R106M10A GRM18series
Table4.BD9106FVM RITH recommended value Vout[V] RITH *BD9106FVM: resistance recommended RITH depends output voltage, check output voltage determination resistance.
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14/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
equivalence circuit
1pin(VOUT) BD9106FVM 1pin(ADJ)
Technical Note
VOUT
2pin(ITH)
3pin(EN)
2.8M
2.2k
6pin(SW) PVCC PVCC PVCC
Fig.58 equivalence circuit
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15/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
Notes Absolute Maximum Ratings While utmost care taken quality control this product, application that exceed some absolute maximum ratings including voltage applied operating temperature range result breakage. broken, short-mode open-mode identified. expected encounter with special mode that exceed absolute maximum ratings, requested take necessary safety measures physically including insertion fuses. Electrical potential must designed have lowest electrical potential operating conditions. Short-circuiting between terminals, mismounting When mounting board, care must taken avoid mistake orientation alignment. Failure result breakdown. Short-circuiting foreign matters entered between output terminals, between output power supply also cause breakdown. 4.Operation Strong electromagnetic field noted that using strong electromagnetic radiation cause operation failures. Thermal shutdown protection circuit Thermal shutdown protection circuit circuit designed isolate from thermal runaway, intended protect guarantee thermal shutdown protection circuit which once activated should used thereafter operation originally intended. Inspection with board capacitor must connected lower impedance during inspection with board, capacitor must discharged after each process avoid stress electrostatic protection, provide proper grounding assembling processes with special care taken handling storage. When connecting jigs inspection process, sure turn power supply before connected removed. Input terminals This monolithic with isolation between P-substrate each element illustrated below. This P-layer N-layer each element form junction, various parasitic element formed. resistor joined transistor terminal shown junction works parasitic diode following relationship satisfied; GND>Terminal resistor side), GND>Terminal transistor side); GND>Terminal transistor side), parasitic transistor activated N-layer other element adjacent above-mentioned parasitic diode. structure inevitably forms parasitic elements, activation which cause interference among circuits, and/or malfunctions contributing breakdown. therefore requested take care device such manner that voltage lower than P-substrate) applied input terminal, which result activation parasitic elements.
Resistance (Pin (Pin Transistor (NPN) substrate Parasitic diode Parasitic diode transistor substrate Parasitic diode transistor (Pin (Pin Parasitic diode
Fig.59 Simplified structure monorisic Ground wiring pattern small-signal large-current provided, will recommended separate large-current pattern from small-signal pattern establish single ground reference point that resistance wiring pattern voltage fluctuations large current will cause fluctuations voltages small-signal GND. attention cause fluctuations wiring pattern external parts well.
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16/17
2009.05 Rev.A
BD9102FVM, BD9104FVM, BD9106FVM
Ordering part number
Technical Note
Part
Part 9102,9104,9106
Package FVM: MSOP8
Packaging forming specification Embossed tape reel (MSOP8)
MSOP8
<Tape Reel information>
2.9±0.1 (MAX 3.25 include BURR)
Tape
0.29±0.15 0.6±0.2
Embossed carrier tape 3000pcs
direction 1pin product upper right when hold
Quantity Direction feed
4.0±0.2
2.8±0.1
reel left hand pull tape right hand
1pin
1PIN MARK 0.475 +0.05 0.22 -0.04 0.08 0.65
+0.05 0.145 -0.03
0.9MAX 0.75±0.05
0.08±0.05
Direction feed
(Unit
Reel
Order quantity needs multiple minimum quantity.
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17/17
2009.05 Rev.A
Notice
Notes
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R0039A

Output 1.5A Less High Efficiency Step-down Switching Regulators with B

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