Flexible Step-down Switching Regulators with Built-in Power MOSFET

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Flexible Step-down Switching Regulators with Built-in Power MOSFET

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Single-chip Type with built-in Switching Regulator Series
Flexible Step-down Switching Regulators with Built-in Power MOSFET
BD9006F, BD9006HFP, BD9007F, BD9007HFP
No.09027EAT35
Overview high-accuracy frequency flexible step-down switching regulator switching regulator with built-in POWER FET, which withstands high pressure. operational frequency freely configurable with external resistance. features wide input voltage range (7V~35V) high frequency accuracy (BD9006F, BD9006HFP; f=200~500kHz), Furthermore, external synchronization input enables synchronous operation with external clock.
Features Minimal external components Wide input voltage range: 7V35V Frequency voltage accuracy: ±5%(BD9006F,BD9006HFP f=200500kHz) ±20%(BD9007F, BD9007HFP) Built-in P-ch POWER Output voltage setting enabled with external resistor: 0.8VVIN Reference voltage accuracy: 0.8V±2% Wide operating temperature range: -40+105 dropout: 100% duty cycle Standby mode supply current: (Typ.) Oscillation frequency variable with external resistor: 50500kHz External synchronization enabled Soft start function: soft start time fixed (Typ.) Built-in overcurrent protection circuit Built-in thermal shutdown protection circuit High-power HRP7 package mounted (BD9006HFP,BD9007HFP) Compact SOP8 package mounted (BD9006F,BD9007F)
Applications fields industrial equipment, such Flat printer, DVD, audio, navigation, communication such ETC,
Product lineup Item Output Current Input Range Oscillation Frequency Range Oscillation Frequency Accuracy External Synchronous Function Standby Function Operating Temperature Package BD9006F,BD9006HFP 7V35V 50500kHz Provided Provided -40+105 SOP8/HRP7 BD9007F,BD9007HFP 7V35V 50500kHz ±20% Provided Provided -40+105 SOP8/HRP7
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1/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Absolute Maximum Ratings (Ta=25oC) Parameter Power Supply Voltage Output Switch Voltage Output Switch Current EN/SYNC Voltage Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Maximum Junction Temperature
Technical Note
Symbol VEN/SYNC VRT,VFB,VINV HRP7 SOP8 Topr Tstg Tjmax
Limits
Unit
0.69
-40+105 -55+150
Should exceed Pd-value. Reduce 44mW/ over 25,when mounted 2-layerPCB (PCB incorporates thermal via. Copper foil area reverse side PCB: Copper foil area reverse side PCB: Reduce 5.52mW/ over 25,when mounted 2-layer
Recommended Operating Range Parameter Operating Power Supply Voltage Output Switch Current Output Voltage (min pulse width) Oscillation Frequency Oscillation Frequency Resistance Possible Operating Range Parameter Operating Power Supply Voltage BD9006F,BD9006HFP BD9007F,BD9007HFP Unit BD9006F,BD9006HFP 50500 27360 BD9007F,BD9007HFP 50500 27360 Unit
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2/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Electrical Characteristics BD9006F,BD9006HFP (Unless otherwise specified, Ta=25, VIN=13.2V, VEN/SYNC=5V) Parameter Standby Circuit Current Circuit Current Block POWER Resistance Operating Output Current Overcurrent Protection Output Leak Current Error Block Reference Voltage Reference Voltage Reference Voltage Input Regulation Input Bias Current Maximum Voltage Minimum Voltage Sink Current Source Current Soft Start Time Oscillator Block Oscillation Frequency Frequency Input Regulation Enable/Sync Input Block Output Voltage Output Voltage Sink Current External Sync Frequency
*Not designed radiation resistant.
Technical Note
Symbol ISTB
Spec Values Min. Typ. Max.
Unit
Conditions VEN/SYNC=0V IO=0A,RT=51k,VINV=0.7V
IOLIMIT IOLEAK
ISW=50mA
VIN=35V, VEN/SYNC=0V
VREF1 VREF2 VREF VFBH VFBL IFBSINK IFBSOURCE
0.784 0.780 -0.47
0.800 0.800 -1.16
0.816 0.820 -2.45
VFB=VINV VIN=1016V,VFB=VINV
VINV=0.6V VINV=0V VINV=2V VFB=1V,VINV=1V VFB=1V,VINV=0.6V Ta=-40105
FOSC FOSC
RT=51k VIN=1016V VEN/SYNC Sweep Ta=-40105 VEN/SYNC Sweep Down, Ta=-40105 RT=51k, EN/SYNC=500kHz,Duty
VENON VENOFF IEN/SYNC FSYNC
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3/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Electrical Characteristics BD9007F,BD9007HFP (Unless otherwise specified, Ta=25, VIN=13.2V, VEN/SYNC=5V) Parameter Standby Circuit Current Circuit Current Block POWER Resistance Operating Output Current Overcurrent Protection Output Leak Current Error Block Reference Voltage Reference Voltage Reference Voltage Input Regulation Input Bias Current Maximum Voltage Minimum Voltage Sink Current Source Current Soft Start Time Oscillator Block Oscillation Frequency Frequency Input Regulation Enable/Sync Input Block Output Voltage Output Voltage Sink Current External Sync Frequency
*Not designed radiation resistant.
Technical Note
Symbol ISTB
Spec Values Min. Typ. Max.
Unit
Conditions VEN/SYNC=0V IO=0A,RT=51k,VINV=0.7V
IOLIMIT IOLEAK
ISW=50mA
VIN=35V, VEN/SYNC=0V
VREF1 VREF2 VREF VFBH VFBL IFBSINK IFBSOURCE
0.784 0.780 -0.47
0.800 0.800 -1.16
0.816 0.820 -2.45
VFB=VINV VIN=1016V,VFB=VINV
VINV=0.6V VINV=0V VINV=2V VFB=1V,VINV=1V VFB=1V,VINV=0.6V Ta=-40105
FOSC FOSC
RT=51k VIN=1016V VEN/SYNC Sweep Ta=-40105 VEN/SYNC Sweep Down, Ta=-40105 RT=51k, EN/SYNC=500kHz,Duty
VENON VENOFF IEN/SYNC FSYNC
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4/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Reference Data
0.816
OSCILATING FREQUENCY:fosc[kHz]
Technical Note
52.5
OSCILATING FREQUENCY:fosc[kHz
REFERENCE VOLTAGE:VREF[V]
0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 AMBIENT TEMPERATURE:Ta[]
52.0 51.5 51.0 50.5 50.0 49.5 49.0 48.5 48.0 47.5 AMBIENT TEMPERATURE:Ta[] RT=330k
RT=160k
AMBIENT TEMPERATURE:Ta[]
Fig.1 Output reference voltage Ambient temperature (All series)
OSCILATING FREQUENCY:fosc[kHz]
Fig.2 Frequency Ambient temperature (All series)
OSCILATING FREQUENCY:fosc[kHz]
STAND-BY CURRENT:ISTB
Fig.3 Frequency Ambient temperature (All series)
AMBIENT TEMPERATURE:Ta[]
AMBIENT TEMPERATURE:Ta[]
RT=51k
RT=30k
Ta=105 Ta=25,-
INPUT VOLTAGE:VIN[V]
Fig.4 Frequency Ambient temperature (All series)
Fig.5 Frequency Ambient temperature (All series)
RESISTANCE:RON[]
Fig.6 Standby Current (All series)
EN/SYNC INPUT CURRENT:[mA]
CIRCUIT CURRENT: ICC[mA]
Ta=105 From Top: Ta=105 Ta=25 Ta=25 Ta=-40 Ta=-40
INPUT VOLTAGE:VEN/SYNC[V]
Inflection Point From Top: VEN=7V (Ta=105) VEN=6.8V (Ta=25) VEN=6.4V(Ta=-40)
From Top: Ta=105 Ta=25 Ta=-40
INPUT VOLTAGE: VIN[V]
OUTPUT CURRENT:Io[A]
Fig.7 Circuit Current (All series)
RESISTANCE:R ON[]
RESISTANCE:R ON[]
Fig.8 EN/SYNC Input Current (All series)
Fig.9 Resistance VIN=7V (All series)
CONVERSION EFFICIENCY 5.0V From Top: 5.0V output 3.3V output 3.3V 2.5V output 2.5V 1.5V output 1.5V
OUTPUT CURRENT:Io[A]
From Top: Ta=105 Ta=25 Ta=-40
OUTPUT CURRENT:Io[A]
From Top: Ta=105 Ta=25 Ta=-40
VIN=13.2V f=100kHz Ta=25
OUTPUT CURRENT:Io[A]
Fig.10 Resistance VIN=13.2V (All series)
Fig.11 Resistance VIN=35V (All series)
Fig.12 Efficiency f=100kHz (All series)
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5/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
From Left: Ta=105 Ta=-40 Ta=25
CONVERSION EFFICIENCY
CONVERSION EFFICIENCY
OUTPUT CURRENT:Io[A]
From Top: 5.0V output 3.3V output 2.5V output 1.5V output
OUTPUT VPLTAGE:Vo
OUTPUT CURRENT:Io[A]
From Top: 5.0V output 3.3V output 2.5V output 1.5V output
VIN=13.2V f=300kHz Ta=25
VIN=13.2V f=500kHz Ta=25
VIN=13.2V f=300kHz Vo=5V
OUTPUT CURRENT:Io[A]
Fig.13 Efficiency f=300kHz (All series)
INPUT VOLTAGE INPUT VOLTAGE OUTPUT CURRENT:Io[A] Vo=5V f=300kHz Ta=-40
Fig.14 Efficiency f=500kHz (All series)
Fig.15 Over-current Protection Operation Current (All series)
INPUT VOLTAGE Vo=5V f=300kHz Ta=105
Vo=5V f=300kHz Ta=25
OUTPUT CURRENT:Io[A]
OUTPUT CURRENT:Io[A]
Fig.16 lowest voltage possible operation (All series)
Fig.17 lowest voltage possible operation (All series)
Fig.18 lowest voltage possible operation (All series)
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6/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Block Diagrams Application circuit assignment (BD9006F,BD9007F)
PVIN
Technical Note
(BD9006HFP,BD9007HFP)
VREG Internal SOFT START Bias SYNC
EN/SYNC
EN/SYNC
220F
220F
Internal Bias
Vref
CURRENT LIMIT SDWN Reset SDWN
DRIVER
SOFT START
SYNC
ERROR
COMPARATOR Slope
0.8V
ERROR
COMPARATOR SDWN Reset SDWN
CURRENT LIMIT
0.8V Slope
DRIVER
22000pF
EN/SYNC
UVLO/
22000pF
UVLO/
330F
330F
PVIN
EN/SYNC
Fig.19 name PVIN Function Power system power supply input Output Error output Output voltage feedback name
Fig.20 Function Power supply input Output Error output Ground Output voltage feedback Frequency setting resistor connection
EN/SYNC Enable/Synchronizing pulse input Frequency setting resistor connection Ground Power supply input
EN/SYNC Enable/Synchronizing pulse input Ground
*VIN PVIN must shorted before
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7/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Description operations ERROR ERROR block error amplifier used input reference voltage (0.8V Typ.) voltage. output controls switching duty output voltage These pins externally mounted facilitate phase compensation. Inserting capacitor resistor between these pins enables adjustment phase margin. (Refer recommended examples pages 11~13.)
SOFT START SOFT START block provides function prevent overshoot output voltage through gradually increasing normal rotation input error amplifier when power supply turns gradually increase switching Duty. soft start time 5msec (Typ.).
SYNC making "EN/SYNC" terminal less than 0.8V, circuit shut down. Furthermore, applying pulse with higher frequency than configured oscillation frequency "EN/SYNC" terminal, external sync possible. (Sync possible with double configured frequency-configured frequency 500kHz)
OSC(Oscillator) This circuit generates pulse wave input slope, connecting resistance "RT", 50~500kHz oscillating frequency configured. (Refer p.11 Fig.24)
slope This block generates tooth waves from clock generated OSC. generated tooth waves sent COMPARATOR.
COMPARATOR COMPARATOR block comparator make comparison between internal tooth wave output switching pulse switching pulse duty varies with value. (min Duty width 250ns.)
(Thermal Shut Down) order prevent thermal destruction/thermal runaway block will turn output when chip temperature reaches approximately more. When chip temperature falls specified level, output will reset. However, since designed protect chip junction temperature should provided with thermal shutdown detection temperature less than approximately.150.
CURRENT LIMIT While output POWER P-ch voltage between drain source current) exceeds reference voltage internally with this block will turn output latch. overcurrent protection detection values have been shown below: BD9006F,BD9006HFP, BD9007F,BD9007HFP (Typ.) Furthermore, since this overcurrent protection automatically reset, after output turned latched, latch will reset with RESET signal output each oscillation frequency. However, this protection circuit only effective preventing destruction from sudden accident. does support continuous operation protection circuit (e.g. load, which significantly exceeds output current capacitance, normally connected). Furthermore, since overcurrent protection detection value negative temperature characteristics, consider thermal design.
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8/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Timing Chart (All series) Basic Operation
Technical Note
Internal slope
VEN/SYNC
Fig.21 External synchronizing function order activate external synchronizing function, connect frequency setting resistor then input synchronizing signal EN/SYNC pin. synchronizing signal, input pulse wave higher than frequency determined with setting resistor (RT). However, external sync frequency should configured less than double configured frequency. (ex.) When configured frequency 100kHz, external sync frequency should less than 200kHz. Furthermore, pulse wave's voltage should under 0.8V HIGH voltage over 2.6V (when HIGH voltage over EN/SYNC input current increases [see Fig.8]), through rate stand-up (and stand-down) under 20V/S.
VIN=13.2V
BD9006HFP
330F 22000pF EN/SY 220F
open
Ven/sync=05V f=450kHz SR=20V/s Duty=50%
open
Fig.22 External Sync Sample Circuit (Vo=3.3V, Io=1A, f=300kHz, EN/SYNC=450kHz)
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9/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Description external components
Technical Note
EN/SYNC
Fig.23 Design Procedure Vo=Output voltage, (Max.)=Maximum input voltage (Max.)=Maximum load current, f=Oscillation frequency Setting output voltage Output voltage obtained formula shown below: formula select Furthermore, less. Select current passing through small enough output current. Sample Calculations When Vo=3.3V, (Typ.)=13.2V Io(Max.)=1A f=300kHz When VO=3.3V R2=15k R1=46.875k47k R1=47k
Selection coil (L1) When VIN=13.2V, Vo=3.3V, Io=1A f=300kHz, value coil obtained formula shown below: =27.5µH33µH Output ripple current should typically approximately this coil optimum value, normal (continuous) L1=33µH Oscillation achieved. Furthermore, value coil with adequate margin that peak current passing through coil will exceed rated current coil. Selection output capacitor (Co) VIN=13.2V, Vo=3.3V, L=33µH, f=300kHz output capacitor determined according output ripple voltage Vo(p-p) required. Obtain required =0.25 value formula shown below then select IL=0.25A capacitance. rating capacitor with adequate margin output voltage. Also, maximum allowable ripple current with adequate margin Furthermore, output rise time should shorter than soft start time. Select output capacitor having value smaller than that obtained formula shown below. CMAX
When ILIMIT: Io(Max)=1A, Vo=3.3V CMAX 910µ
ILIMIT2A (BD9006F,BD9006HFP, BD9007F,BD9007HFP) this capacitances optimum, faulty startup result. (3.0m soft start time(min).)
CMAX=910µF
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10/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Design Method Selection diode (D1) diode rating with adequate margin maximum load current. Also, make setting rated inverse voltage with adequate margin maximum input voltage. diode with forward voltage short reverse recovery time will provide high efficiency. Selection input capacitor (CIN, C28) capacitors, ceramic capacitor bypass capacitor should inserted between GND. sure insert ceramic capacitor 10µF CIN. capacitor should have significantly large ripple current. ripple current IRMS obtained following formula:
Sample Calculations When VIN(max.)=35V Io=(max.)2A Diode ratings must include: Current over Withstand minimum When VIN=13.2V, Vo=3.3V Io=1A:
IRMS=0.433A
Select capacitors that accept this ripple current. capacitance optimum, malfunction. Setting oscillating frequenPcy Referring Fig.24 following page, select oscillating frequency used. Setting phase compensation phase margin through inserting capacitor capacitor resistor between pin. Each value varies with output coil, capacitance, voltage, load. Therefore, phase compensation optimum value according these conditions. (For details, refer Application circuit page.11) this setting optimum, output oscillation result.
When f=300kHz From p.11 Fig.24, resistance RT=51k selected. RT=51k Please contact there questions regarding phase compensation configuration.
values listed above reference values. actual mounting characteristics vary with routing wirings types parts use. connection, recommended thoroughly verify these values actual system prior use.
Directions pattern layout
BD9006HFP
SIGNAL
POWER
Arrange wirings shown heavy lines short possible broad pattern. Locate input ceramic capacitor close VIN-GND possible. Locate close possible. Locate close possible, provide shortest wiring from pin. Locate away from possible. Separate POWER (Schottky diode, capacitor's GND) SIGNAL (RT, GND), that noise doesn't have effect SIGNAL all. Design POWER wire line wide short possible. Additional pattern expand compensation flexibility.
Fig.24
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11/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Fig.25 BD9006F Reference Layout Pattern
Fig.26 BD9006HFP Reference Layout Pattern
shown above ,design pattern large possible within inner layer. Gray zones indicate GND.
OSCILATION FREQUENCY:fosc[kHz]
OSCILATING FREQUENCY SETTEING RESISTANCE:RT[k]
RT[k]
fosc[kHz]
RT[k]
fosc[kHz]
Fig.27 Resistance Values Oscillating Frequency Phase Compensation setting procedure Application stability conditions
values graph oscillating frequency Typical values, variance of±5% forBD9006F/HFP ±20% BD9007F/HFP should considered.
following section describes stability conditions negative feedback system. Since DC/DC converter application sampled according switching frequency, (frequency 0-dB gain) overall system should 1/10 less switching frequency. following section summarizes targeted characteristics this application. (0-dB) gain, phase delay 150° less (i.e. phase margin more). this occasion 1/10 less switching frequency. Responsiveness determined with restrictions GBW. improve responsiveness, higher switching frequency should provided. Replace secondary phase delay (-180°) with secondary phase lead inserting two-phase leads, ensure stability through phase compensation. Furthermore, (i.e., frequency 0-dB gain) determined according phase compensation capacitance provided error amplifier. Consequently, order reduce GBW, increase capacitance value. Typical integrator (low pass filter) Open loop characteristics integrator
-20dB/decade GBW(b) -90° Phase margin -180°
Feedback
Gain [dB]
Point
2RCA
[Hz]
Phase
Point fb=GBW=
[Hz]
-180
Since error amplifier provided with phase compensation, pass filter applied. case DC/DC converter application, becomes parallel resistance feedback resistance.
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12/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
output capacitors having high ESR, such electrolyte capacitor
Technical Note
output capacitors that have high (i.e., several phase compensation setting procedure becomes comparatively simple. Since DC/DC converter application resonant circuit attached output, -180° phase-delay occurs that area. component present, however +90° phase-lead occurs shift phase delay -90°. Since phase delay should within 150°, very effective method tends increase ripple component output voltage. resonant circuit With provided
RESR
[Hz]
this resonance point, a-180° phase-delay occurs.
[Hz]: Resonance fESR [Hz]: Phase lead 2RESRC -90° phase-delay occurs.
According changes phase characteristics, ESR, only phase lead should inserted. this phase lead, select either methods shows below: Insert Feedback Resistance
Insert integrator.
Phase lead
2C1R1
[Hz]
Phase lead
2C2R3
[Hz]
cancel resonance, frequency insert phase lead should close resonant frequency. setting above have estimated. Consequently, setting adjusted actual system. Furthermore, since these characteristics vary with layout loading conditions, precise calculations should made actual system. 3For output capacitors having ESR, such impedance electrolyte capacitor OS-CON order capacitors with (i.e., several tens phase-leads should inserted that -180°phasedelay, resonance, will compensated. following section shows typical phase compensation procedure. Phase compensation with secondary phase lead
Phase leadfz2 Phase leadfz1
2R1C1 2R3C2
[Hz] [Hz]
resonantfr frequency
[Hz]
phase lead frequency, insert both phase leads close resonant frequency. According empirical rule, setting phase lead frequency with lower than resonant frequency phase lead frequency with higher than resonant frequency will provide stable application conditions.
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13/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
DC/DC converter controller
Load Output voltage
Maximum load
Inadequate phase margin
Adequate phase margin
<Reference> Measurement open loop DC/DC converter measure open loop DC/DC converter, gain phase analyzer measure frequency characteristics. <Procedure> Check ensure output causes oscillation maximum load inclosed loop. Isolate insert (with amplitude approximately.100mVpp). Measure (probe) oscillation that Furthermore, phase margin also measured with load responsiveness. Measure variations output voltage when instantaneously changing load from load maximum load. Even though ringing phenomenon caused, phase margin, ringing takes place. Phase margin provided. However, specific phase margin probed.
Please contact have questions regarding phase compensation.
Heat Loss thermal design, sure operate within following conditions. (Since temperatures described hereunder guaranteed temperature, take margin into account.) ambient temperature less. chip junction temperature less. chip junction temperature considered following patterns: obtain from surface temperature actual state, Reference value :HRP7 SOP8 32.5/W obtain from ambient temperature actual Reference. value HRP7 89.3/W Single piece 54.3/W 2-layer (Copper foil area front side PCB: 22.7/W 2-layer (Copper foil area front side PCB: size: (PCB incorporates thermal via.) Copper foil area front side PCB: SOP8 222.2/W Single piece 181.8/W 1-layer size: heat loss obtained formula shown below: Ron: resistance (refer page.4) Load current Output voltage VIN: Input voltage ICC: Circuit current (refer page.3) Switching rise/fall time (approximately 20nsec) Oscillation frequency
wave from
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14/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Internal Power
Internal Power
167k
EN/SYNC
Internal Power
Internal Power
SYNC
Fig.28 Equivalent circuit Notes Absolute maximum ratings excess absolute maximum ratings, such supply voltage, temperature range operating conditions, etc., break down devices, thus making impossible identify breaking mode, such short circuit open circuit. over rated values will expect exceed absolute maximum ratings, consider adding circuit protection devices, such fuses. potential Ground-GND potential should maintain minimum ground voltage level. Furthermore, terminals should lower than potential voltage including electric transients. Thermal design thermal design that allows sufficient margin light power dissipation (Pd) actual operating conditions. Inter-pin shorts mounting errors When attaching substrate, special attention direction proper placement attached incorrectly, destroyed. Furthermore, when using with EN/SYNC terminals shorted, 5-pin (SOP8 package) 7-pin (HRP7 package) EN/SYNC terminal 6-pin terminal shorted, also damaged when VIN>7V. Operation strong electromagnetic field caution when using presence strong electromagnetic field doing cause malfunction. Inspection with printed circuit board When testing application board, connecting capacitor with impedance subjects stress. Always discharge capacitors after each process step. Always turn IC's power supply before connecting removing from fixture, during inspection process. Ground during assembly steps antistatic measure. similar precaution when transporting storing input (Fig. This monolithic contains isolation substrate layers between adjacent elements keep them isolated. junctions formed intersection these layers with layers other elements, creating parasitic, creating parasitic diode transistor. example, relation between each potential follows: When GND>pin GND>pin junction operates parasitic diode. When >GND>pin junction operates parasitic transistor. Parasitic diodes occur inevitably structure operation parasitic diodes result mutual interference among circuits, operational faults, physical damage. Accordingly, methods which parasitic diodes operate, such applying voltage that lower than substrate) voltage input pin, should used.
Resistor (Terminal (Terminal Transistor (NPN) (Terminal Parasitic Element
(Terminal
Substrate
Parasitic Element Parasitic Element
Substrate
Parasitic Element
Fig.29 Typical simple construction monolithic
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15/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
wiring pattern recommended separate large-current pattern from small-signal pattern establish single ground reference point PCB, that resistance wiring pattern voltage fluctuations large current will cause fluctuations voltages small-signal GND. Prevent fluctuations wiring pattern external parts. Temperature protection (thermal shut down) circuit This built-in temperature protection circuit prevent thermal destruction described above, sure this within power dissipation range. Should condition exceeding power dissipation range continue, chip temperature will rise activate temperature protection circuit, thus turning output power element. Then, when temperature falls, circuit will automatically reset. Furthermore, temperature protection circuit activated under condition exceeding absolute maximum ratings, attempt temperature protection circuit design. application shown below, there mode which each potential inverted, example, short-circuited Ground with external diode charged, internal circuits damaged. avoid damage, recommended insert backflow prevention diode series with bypass diode between each VIN.
Bypass diode
Backflow prevention diode
Fig.30
Thermal reduction characteristics HRP7
POWER DISSIPATIONPD POWER DISSIPATIONPD
SOP8
1.4W 2.3W 5.5W 7.3W
AMBIENT TEMPERATURETa
AMBIENT TEMPERATURETa
Single piece Size: (PCB incorporates thermal via) Copper foil area front side PCB: 2-layer (Copper foil area reverse side PCB: 2-layer (Copper foil area reverse side PCB: 4-layer (Copper foil area reverse side PCB: Fig.31
Single piece When mounted ROHM standard
(Glass epoxy
Fig.32
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16/17
2009.05 Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Ordering part number
Technical Note
Part
Part 9006, 9007
Package SOP8 HRP7
Packaging forming specification Embossed tape reel (SOP8) Embossed tape reel (HRP7)
SOP8
<Tape Reel information>
5.0±0.2 (MAX 5.35 include BURR)
Tape Quantity
0.9±0.15 0.3MIN
Embossed carrier tape 2500pcs
direction 1pin product upper left when hold
6.2±0.3
4.4±0.2
Direction feed
reel left hand pull tape right hand
0.595
1.5±0.1
+0.1 0.17 -0.05
0.11
1.27 0.42±0.1
1pin
(Unit
Direction feed
Reel
Order quantity needs multiple minimum quantity.
HRP7
<Tape Reel information>
9.395±0.125 (MAX 9.745 include BURR)
1.017±0.2
Tape
1.905±0.1
Embossed carrier tape 2000pcs
direction 1pin product upper right when hold
8.82±0.1 (5.59)
Quantity Direction feed
1.523±0.15
0.835±0.2
10.54±0.13
8.0±0.13
(7.49)
reel left hand pull tape right hand
1pin
0.8875
+5.5° 4.5° -4.5° 0.73±0.1 +0.1 0.27 -0.05
0.08±0.05
1.27
0.08
Direction feed
(Unit
Reel
Order quantity needs multiple minimum quantity.
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17/17
2009.05 Rev.A
Notice
Notes
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R0039A

Flexible Step-down Switching Regulators with Built-in Power MOSFET

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