Universal driver multiplex rates Rev. July 2009 Product data shee

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PCF8576C
Universal driver multiplex rates
Rev. July 2009 Product data sheet
PCF8576C peripheral device which interfaces almost Liquid Crystal Display (LCD)1 with multiplex rates. generates drive signals static multiplexed containing four backplanes segments easily cascaded larger applications. PCF8576C compatible with most microprocessors microcontrollers communicates two-line bidirectional I2C-bus. Communication overheads minimized display with auto-incremented addressing, hardware subaddressing.
Features
Single-chip controller driver segment drives: twenty 7-segment numeric characters 14-segment alphanumeric characters graphics elements Versatile blinking modes external components required (even multiple device applications) Selectable backplane drive configuration: static backplane multiplexing Selectable display bias configuration: static, Internal bias generation with voltage-follower buffers 4-bit display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching static duplex drive modes Wide logic supply range: From low-threshold LCDs guest-host LCDs high-threshold twisted nematic LCDs power consumption cascaded large applications 2560 segments possible) Cascadable with 24-segment driver PCF8566 external components Compatible with chip-on-glass technology Separate combined logic supplies Optimized pinning plane wiring both multiple PCF8576C applications Power-saving mode extremely power consumption battery-operated telephone applications
definition abbreviations acronyms used this data sheet found Section
Semiconductors
PCF8576C
Universal driver multiplex rates
Ordering information
Table Ordering information Package Name PCF8576CH PCF8576CT PCF8576CTT LQFP64 VSO56 HTSSOP56 Description plastic profile quad flat package; leads; body plastic very small outline package, leads Version SOT314-2 SOT190-1 Type number
plastic thermal enhanced thin shrink small outline package, leads; SOT793-1 body width exposed PCF8576CU/10 PCF8576CU PCF8576CU/2 wire bond die; bonding pads; 2.82 0.38 mm[2] bare die; bumps; 2.82 0.40 mm[2]
PCF8576CU/10 PCF8576CU/10 wire bond die; bonding pads; 2.82 0.38 mm[1] PCF8576CU PCF8576CU/2
PCF8576CU PCF8576CU/2
Delivery form: chip FFC. Delivery form: chip tray.
Marking
Table Marking codes Marking code PCF8576CH PCF8576CT PCF8576CTT PC8576C-1 PC8576C-1 PC8576C-2 Type number PCF8576CH PCF8576CT PCF8576CTT PCF8576CU/10 PCF8576CU PCF8576CU/2
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Product data sheet
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PCF8576C
Universal driver multiplex rates
Block diagram
BACKPLANE OUTPUTS
DISPLAY SEGMENT OUTPUTS
VOLTAGE SELECTOR
DISPLAY LATCH
VLCD
BIAS GENERATOR
SHIFT REGISTER
PCF8576C
TIMING SYNC DISPLAY CONTROLLER OSCILLATOR POWERON RESET COMMAND DECODER INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER DATA POINTER BLINKER INPUT BANK SELECTOR DISPLAY BITS OUTPUT BANK SELECTOR
013aaa094
Block diagram PCF8576C
PCF8576C_9
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PCF8576C
Universal driver multiplex rates
Pinning information
Pinning
n.c. n.c. n.c.
n.c. n.c.
PCF8576CH
SYNC
VLCD
n.c.
n.c.
n.c.
001aag241
view. mechanical details, Figure
configuration PCF8576CH (LQFP64)
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PCF8576C
Universal driver multiplex rates
SYNC
001aag240
VLCD
PCF8576CT
view. mechanical details, Figure
configuration PCF8576CT (VSO56)
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PCF8576C
Universal driver multiplex rates
SYNC
013aaa095
VLCD
PCF8576CTT
view. mechanical details, Figure
configuration PCF8576CTT (HTSSOP56)
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PCF8576C
Universal driver multiplex rates
PCF8576CU
VLCD
013aaa096
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SYNC
view. mechanical details, Figure Figure Figure
locations PCF8576CU
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PCF8576C
Universal driver multiplex rates
description
Table Symbol description PCF8576CH SYNC VLCD BP0, BP2, BP1, n.c.
Description PCF8576CT PCF8576CTT PCF8576CU 5[1] I2C-bus serial data input output I2C-bus serial clock input cascade synchronization input output external clock input/output supply voltage internal oscillator enable input subaddress inputs I2C-bus address input; logic ground supply voltage backplane outputs segment outputs connected
substrate (rear side die) wired should electrically connected.
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PCF8576C
Universal driver multiplex rates
Functional description
PCF8576C versatile peripheral device designed interface microprocessor microcontroller wide variety LCDs. directly drive static multiplexed containing backplanes segments. display configurations possible with PCF8576C depend number active backplane outputs required. Display configuration selection shown Table display configurations given Table implemented typical system shown Figure
Table Display configurations segment numeric Digits Indicator symbols 14-segment numeric Characters Indicator symbols matrix
Number Backplanes Elements
segment drives PANEL elements)
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8576C
backplanes
013aaa098
Typical system configuration
host microprocessor microcontroller maintains 2-line I2C-bus communication channel with PCF8576C. Biasing voltages multiplexed waveforms generated internally, removing need external bias generator. internal oscillator selected connecting VSS. only other connections required complete system power supplies (pins VDD, VLCD) panel selected application.
Power-on-reset
power-on PCF8576C resets following starting conditions:
PCF8576C_9
backplane segment outputs selected drive mode multiplex with bias Blinking switched Input output bank selectors reset defined Table
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PCF8576C
Universal driver multiplex rates
I2C-bus interface initialized data pointer subaddress counter cleared
Remark: transfer data I2C-bus least after power-on allow reset action complete.
bias generator
full-scale voltage (Voper) obtained from VLCD. voltage temperature compensated externally through VLCD supply VLCD. Fractional biasing voltages obtained from internal voltage divider comprising three series resistors connected between VLCD. center resistor switched circuit provide bias voltage level multiplex configuration.
voltage selector
voltage selector coordinates multiplexing accordance with selected drive configuration. operation voltage selector controlled mode-set command from command decoder. biasing configurations that apply preferred modes operation, together with biasing characteristics functions VLCD resulting discrimination ratios (D), given Table
Table drive mode static Preferred drive modes: summary characteristics Number bias Backplanes Bias levels configuration static
0.354 0.333 0.333 0.333
0.791 0.745 0.638 0.577
2.236 2.236 1.915 1.732
multiplex multiplex multiplex multiplex
practical value VLCD determined equating Voff(RMS) with defined threshold voltage (Vth), typically when exhibits approximately contrast. static drive mode suitable choice VLCD Vth. Multiplex drive modes with bias possible discrimination hence contrast ratios smaller.
Bias calculated where values
bias bias on-state voltage (Von(RMS)) calculated with Equation
where VLCD resultant voltage segment where values
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PCF8576C
Universal driver multiplex rates
static mode multiplex multiplex multiplex off-state voltage (Voff(RMS)) calculated with Equation
Discrimination ratio Von(RMS) Voff(RMS) determined from Equation
Using Equation discrimination drive mode multiplex with
bias bias
1.732 discrimination drive mode multiplex with
1.528
advantage these drive modes reduction full scale voltage VLCD follows:
multiplex (1/2 bias): 2.449V
multiplex (1/2 bias): 2.309V
These compare with when bias used. should noted that VLCD sometimes referred operating voltage.
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Universal driver multiplex rates
drive mode waveforms
7.4.1 Static drive mode
static drive mode used when single backplane provided LCD. Backplane segment drive waveforms this mode shown Figure
VLCD VLCD VLCD state (on) state (off) segments
Sn+1
Waveforms driver. VLCD
state
-VLCD VLCD
state
-VLCD Resultant waveforms segment.
mgl745
Vstate1(t) VSn(t) VBP0(t). Von(RMS) VLCD. Vstate2(t) VSn+1(t) VBP0(t). Voff(RMS)
Static drive mode waveforms
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Universal driver multiplex rates
7.4.2 Multiplex drive mode
When backplanes provided LCD, multiplex mode applies. PCF8576C allows bias bias (see Figure Figure
VLCD VLCD state VLCD VLCD VLCD VLCD state segments
Sn+1
Waveforms driver. VLCD VLCD state -VLCD -VLCD VLCD VLCD state -VLCD -VLCD Resultant waveforms segment.
mgl746
Vstate1(t) VSn(t) VBP0(t). Von(RMS) 0.791VLCD. Vstate2(t) VSn(t) VBP1(t). Voff(RMS) 0.354VLCD
Waveforms multiplex drive mode with bias
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PCF8576C
Universal driver multiplex rates
VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD Waveforms driver. VLCD 2VLCD VLCD state -VLCD -2VLCD -VLCD VLCD 2VLCD VLCD state -VLCD -2VLCD -VLCD Resultant waveforms segment.
mgl747
segments
state state
Sn+1
Vstate1(t) VSn(t) VBP0(t). Von(RMS) 0.745VLCD Vstate2(t) VSn(t) VBP1(t) Voff(RMS) 0.333VLCD.
Waveforms multiplex drive mode with bias
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Universal driver multiplex rates
7.4.3 Multiplex drive mode
When three backplanes provided LCD, multiplex drive mode applies shown Figure
VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD Sn+1 2VLCD VLCD VLCD 2VLCD VLCD Waveforms driver. VLCD 2VLCD VLCD state -VLCD -2VLCD -VLCD VLCD 2VLCD VLCD state -VLCD -2VLCD -VLCD state state segments
Sn+2
Resultant waveforms segment.
mgl748
Vstate1(t) VSn(t) VBP0(t). Von(RMS) 0.638VLCD. Vstate2(t) VSn(t) VBP1(t). Voff(RMS) 0.333VLCD.
Waveforms multiplex drive mode with bias
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Universal driver multiplex rates
7.4.4 multiplex drive mode
When four backplanes provided LCD, multiplex drive mode applies, shown Figure
VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD 2VLCD VLCD VLCD state state segments
Sn+1
Sn+2
2VLCD VLCD VLCD 2VLCD VLCD Waveforms driver. VLCD 2VLCD VLCD
Sn+3
state
-VLCD -2VLCD -VLCD VLCD 2VLCD VLCD
state
-VLCD -2VLCD -VLCD
Resultant waveforms segment.
mgl749
Vstate1(t) VSn(t) VBP0(t). Von(RMS) 0.577VLCD. Vstate2(t) VSn(t) VBP1(t). Voff(RMS) 0.333VLCD.
Waveforms multiplex mode with bias
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Universal driver multiplex rates
Oscillator
internal logic drive signals PCF8576C timed frequency fclk, which equals either built-in oscillator frequency fosc external clock frequency fclk(ext). clock frequency (fclk) determines frame frequency (ffr) maximum rate data reception from I2C-bus. allow I2C-bus transmissions their maximum data rate kHz, fclk should chosen above kHz.
7.5.1 Internal clock
internal oscillator enabled connecting VSS. this case, output from clock signal cascaded PCF8576s PCF8566s system. Remark: PCF8576C backwards compatible with PCF8576 (Voper Where resistor Rext OSC) present, internal oscillator selected.
7.5.2 External clock
Connecting enables external clock source. then becomes external clock input. Remark: clock signal must always supplied device. Removing clock, freezes state, which suitable liquid crystal.
Timing
timing PCF8576C sequences internal data flow device. This includes transfer display data from display display segment outputs. cascaded applications, synchronization signal (SYNC) maintains correct timing relationship between PCF8576Cs system. timing also generates frame frequency which derived integer division clock frequency (see Table frame frequency mode commands when internal clock used frequency applied when external clock used.
Table frame frequencies Frame frequency Nominal frame frequency (Hz)
PCF8576C mode Normal mode
-2880 -480
Power saving mode
possible values fclk Table fclk kHz. fclk kHz.
ratio between clock frequency frame frequency depends mode which device operating. power-saving mode reduction ratio times smaller; this allows clock frequency reduced factor six. reduced clock frequency results significant reduction power consumption.
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Universal driver multiplex rates
lower clock frequency disadvantage increasing response time when large amounts display data transmitted I2C-bus. When device unable process display data byte before next arrives, holds line until first display data byte stored. This slows down transmission rate I2C-bus data loss occurs.
Display register
display register holds display data while corresponding multiplex signals generated. There one-to-one relationship between data display register, segment outputs column display RAM.
Shift register
shift register transfers display information from display display register while previous data displayed.
Segment outputs
drive section includes segment outputs, S39, which must connected directly LCD. segment output signals generated based multiplexed backplane signals with data residing display register. When less than segment outputs required, unused segment outputs should left open-circuit.
7.10 Backplane outputs
drive section includes four backplane outputs: BP3. backplane output signals generated based selected drive mode.
multiplex drive mode: must connected directly LCD.
less than four backplane outputs required unused outputs left open-circuit.
multiplex drive mode: carries same signal BP1, therefore these
adjacent outputs tied together give enhanced drive capabilities.
multiplex drive mode: BP2, respectively carry same
signals also paired increase drive capabilities.
static drive mode: same signal carried four backplane outputs they
connected parallel very high drive requirements.
7.11 Display
display static 4-bit which stores data. logic bitmap indicates on-state corresponding element; similarly, logic indicates off-state. There direct relationship between addresses segment outputs, between individual bits word backplane outputs. display Figure shows rows which correspond with backplane outputs BP3, columns which correspond with segment outputs S39. multiplexed applications segment data first, second, third fourth display time-multiplexed with BP0, BP1, respectively.
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Universal driver multiplex rates
display addresses (columns)/segment outputs display bits (rows)/ backplane outputs (BP)
mbe525
Display showing direct relationship between addresses segment outputs; also between bits word backplane outputs.
Display
When display data transmitted PCF8576C, display bytes received stored display accordance with selected drive mode. data stored arrives does wait acknowledge cycle with commands. Depending current multiplex drive mode, data stored singularly, pairs, triplets quadruplets. illustrate filling order, example 7-segment numeric display showing drive modes given Figure filling organization depicted applies equally other types. following applies Figure
static drive mode, eight transmitted data bits placed eight
successive 4-bit words.
multiplex mode, eight transmitted data bits placed pairs into
four successive 4-bit words.
multiplex mode, eight bits placed triples into
three successive 4-bit words, with third address left unchanged. recommended this display because difficult addressing. This last may, necessary, controlled additional transfer this address care should taken avoid overwriting adjacent data because always full bytes transmitted.
multiplex mode, eight transmitted data bits placed quadruples into
successive 4-bit words.
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Product data sheet Rev. July 2009
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Semiconductors
drive mode
segments
backplanes
display filling order display addresses (columns)/segment outputs byte1
transmitted display byte
Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6
Sn+1 Sn+7
display bits (rows)/ backplane outputs (BP)
Sn+1
display addresses (columns)/segment outputs byte1 byte2 display bits (rows)/ backplane outputs (BP)
multiplex Sn+2 Sn+3
Sn+1 Sn+2
display bits (rows)/ backplane outputs (BP)
display addresses (columns)/segment outputs byte1 byte2 byte3
multiplex
Universal driver multiplex rates
display addresses (columns)/segment outputs byte1 byte2 byte3 byte4 byte5
display bits (rows)/ backplane outputs (BP)
multiplex
PCF8576C
Sn+1
001aaj646
data unchanged.
Relationship between layout, drive mode, display filling order display data transmitted over I2C-bus
Semiconductors
PCF8576C
Universal driver multiplex rates
7.12 Data pointer
addressing mechanism display realized using data pointer. This allows loading individual display data byte series display data bytes, into location display RAM. sequence commences with initialization data pointer load data pointer command (see Table 13). After this, data byte stored starting display address indicated data pointer (see Figure 13). Once each byte stored, data pointer automatically incremented based selected configuration. contents data pointer incremented follows:
static drive mode eight. multiplex drive mode four. multiplex drive mode three. multiplex drive mode two.
I2C-bus data access terminates early, state data pointer unknown. Consequently, data pointer must rewritten prior further accesses.
7.13 Sub-address counter
storage display data conditioned contents subaddress counter. Storage allowed take place only when contents subaddress counter match with hardware subaddress applied subaddress counter value defined device select command (see Table 14). contents subaddress counter hardware subaddress match then data storage blocked data pointer will incremented data storage taken place. subaddress counter also incremented when data pointer overflows. storage arrangements described lead extremely efficient data loading cascaded applications. When series display bytes sent display RAM, automatic wrap-over next PCF8576C occurs when last address exceeded. Subaddressing across device boundaries successful even change next device cascade occurs within transmitted character (such during 14th display data byte transmitted multiplex mode).
7.14 Bank selector
7.14.1 Output bank selector
output bank selector (see Table 15), selects four bits display address transfer display register. actual selected depends drive mode operation instant multiplex sequence.
multiplex mode: addresses selected, followed sequentially
contents then
multiplex mode: bits selected sequentially. multiplex mode: bits selected. static mode: selected.
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PCF8576C
Universal driver multiplex rates
PCF8576C includes bank switching feature static multiplex drive modes. static drive mode, bank select command request contents selected display instead contents multiplex drive mode, contents bits selected instead bits This enables preparation display information alternative bank ability switch once been assembled.
7.14.2 Input bank selector
input bank selector (see Table loads display data into display based selected drive configuration. Using bank select command, display data loaded into static drive mode bits into multiplex drive mode. input bank selector functions independently output bank selector.
7.15 Blinker
display blinking capabilities PCF8576C very versatile. whole display blinked frequencies selected blink command. blinking frequencies integer fractions clock frequency; ratios between clock blinking frequencies depend mode which device operating (see Table
Table Blink frequencies Normal operating mode ratio Power saving mode ratio Blink frequency blinking
Blinking mode
blink -92160 blink -184320 blink -368640
blink -15360 blink -30720 blink -61440
additional feature arbitrary selection segments blinked. This applies static multiplex drive modes implemented without communication overheads. Using output bank selector, displayed banks exchanged with alternate banks blinking frequency. This mode also specified blink command (see Table 16). multiplex modes, where alternate bank available, groups segments blinked selectively changing display data fixed time intervals. entire display needs blinked frequency other than nominal blink frequency, this done using mode command reset display enable required rate (see Table
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PCF8576C
Universal driver multiplex rates
Basic architecture
Characteristics I2C-bus
I2C-bus provides bidirectional, two-line communication between different modules. lines Serial Data line (SDA) Serial Clock Line (SCL). When connected output stages device, both lines must connected positive supply pull-up resistor. Data transfer initiated only when busy.
8.1.1 transfer
data transferred during each clock pulse. data line must remain stable during HIGH period clock pulse. Changes data line this time will interpreted control signal. transfer illustrated Figure
data line stable; data valid change data allowed
mba607
transfer
8.1.1.1
START STOP conditions Both data clock lines remain HIGH when busy. HIGH-to-LOW change data line, while clock HIGH, defined START condition (S). LOW-to-HIGH change data line, while clock HIGH, defined STOP condition (P). START STOP conditions illustrated Figure
START condition STOP condition
mbc622
Definition START STOP conditions
8.1.2 System configuration
device generating message transmitter device receiving message receiver. device that controls message master devices which controlled master slaves. system configuration illustrated Figure
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Universal driver multiplex rates
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
System configuration
8.1.3 Acknowledge
number data bytes transferred between START STOP conditions from transmitter receiver unlimited. Each byte eight bits followed acknowledge bit. acknowledge HIGH level signal transmitter during which time master generates extra acknowledge related clock pulse. Acknowledgement I2C-bus illustrated Figure
slave receiver which addressed must generate acknowledge after
reception each byte.
master receiver must generate acknowledge after reception each byte that
been clocked slave transmitter.
device that acknowledges must pull-down line during acknowledge
clock pulse, that line stable during HIGH period acknowledge related clock pulse (set-up hold times must taken into consideration).
master receiver must signal end-of-data transmitter generating
acknowledge last byte that been clocked slave. this event, master receiver must leave data line HIGH during pulse acknowledge. master will generate STOP condition.
data output transmitter acknowledge data output receiver acknowledge from master START condition clock pulse acknowledgement
mbc602
Acknowledgement I2C-bus
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Universal driver multiplex rates
8.1.4 PCF8576C I2C-bus controller
PCF8576C acts I2C-bus slave receiver. does initiate I2C-bus transfers transmit data I2C-bus master receiver. only data output from PCF8576C acknowledge signals selected devices. Device selection depends I2C-bus slave address, transferred command data hardware subaddress. single device application, hardware subaddress inputs normally tied which defines hardware subaddress multiple device applications tied using binary coding scheme that devices with common I2C-bus slave address have same hardware subaddress. power-saving mode possible that PCF8576C able keep with highest transmission rates when large amounts display data transmitted. this situation occurs, PCF8576C forces line until internal operations completed. This known clock synchronization feature I2C-bus serves slow down fast transmitters. Data loss does occur.
8.1.5 Input filter
enhance noise immunity electrically adverse environments, low-pass filters provided lines.
I2C-bus protocol
I2C-bus slave addresses (0111000 0111001) reserved PCF8576C. least significant slave address that PCF8576C responds defined level tied input SA0. Therefore, types PCF8576C distinguished same I2C-bus which allows:
PCF8576Cs same I2C-bus very large applications. types multiplex same I2C-bus.
I2C-bus protocol shown Figure sequence initiated with START condition from I2C-bus master which followed PCF8576C slave addresses available. PCF8576Cs with corresponding level acknowledge parallel with slave address PCF8576Cs with alternative level ignore whole I2C-bus transfer. After acknowledgement, more command bytes follow which define status addressed PCF8576Cs. last command byte tagged with cleared most significant bit, continuation command bytes also acknowledged addressed PCF8576Cs bus. After last command byte, series display data bytes follow. These display bytes stored display address specified data pointer subaddress counter. Both data pointer subaddress counter automatically updated data directed intended PCF8576C device. acknowledgement after each byte made only (A0, addressed PCF8576C. After last display byte, I2C-bus master issues STOP condition (P).
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Universal driver multiplex rates
slave address byte
acknowledge addressed PCF8576Cs
acknowledge selected PCF8576C only
COMMAND
DISPLAY DATA
byte(s)
byte(s) update data pointers necessary, subaddress counter
mbe538
I2C-bus protocol
Command decoder
command decoder identifies command bytes that arrive I2C-bus. available commands carry continuation their most significant position shown Figure When this set, indicates that next byte transfer arrive will also represent command. this reset, indicates that command byte last transfer. Further bytes will regarded display data. five commands available PCF8576C defined Table
REST OPCODE
msa833
last command commands continue
General format byte command Table Command mode Definition PCF8576C commands OPCODE Section 8.3.1 defines drive mode, bias configuration, display status power dissipation mode Section 8.3.2 data pointer define display addresses Section 8.3.3 define eight hardware subaddresses Section 8.3.4 defines input bank selection (storage arriving display data); defines output bank selection (retrieval display data) Section 8.3.5 defines blink frequency blink mode
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Reference
Description
load data pointer
device select bank select
blink
PCF8576C_9
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Universal driver multiplex rates
8.3.1 Mode command
Table drive mode command description Backplane BP0, BP0, BP1, BP0, BP1, BP2, drive mode Drive mode static Table bias
bias configuration command description Display status command description[1]
bias bias
Table
Display status disabled (blank) enabled
possibility disable display allows implementation blinking under external control.
Table
Power dissipation mode command description
Display status normal mode power saving mode
8.3.2 Load data pointer command
Table Load data pointer command description Bits Description binary value,
8.3.3 Device select command
Table Device select command description Bits Description binary value,
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Universal driver multiplex rates
8.3.4 Bank select command
Table Bank Input bank Output bank
Bank select command[1] Mode Static multiplex drive mode bits bits bits bits Value
bank select command effect multiplex drive modes.
8.3.5 Blink command
Table Blink frequency command description Table Blink mode command description Blink frequency
Blink mode normal blinking alternate bank blinking
Display controller
display controller executes commands identified command decoder. contains status registers PCF8576C coordinates their effects. controller also responsible loading display data into display required filling order.
Internal circuitry
VLCD SDA, CLK, OSC, SA0, SYNC BP3,
013aaa109
Device protection diagram
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Universal driver multiplex rates
Limiting values
CAUTION Static voltages across liquid crystal display build when supply voltage (VLCD) while supply voltage (VDD) off, vice versa. This cause unwanted display artifacts. avoid such artifacts, VLCD must applied removed together.
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Parameter VLCD supply voltage supply voltage input voltage
Conditions
-0.5
Unit
-0.5
each pins SCL, SDA, CLK, SYNC, SA0, each pins
IDD(LCD) Ptot Tstg VESD
output voltage input current output current supply current ground supply current supply current total power dissipation output power storage temperature electrostatic discharge voltage latch-up current
Values with respect VDD.
-0.5
+150 ±4000 ±200
According store transport conditions (document SNW-SQ-623) devices have stored temperature humidity Pass level; Human Body Model (HBM) according JESD22-A114. Pass level; Machine Model (MM), according JESD22-A115. Pass level; latch-up testing, according JESD78.
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Universal driver multiplex rates
Static characteristics
Table Static characteristics VLCD Tamb unless otherwise specified. Symbol Supplies VLCD IDD(lp) Logic IL(OSC) RSYNC_N VPOR IOH(CLK) IOL(SDA) LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current leakage current leakage current pull-down current SYNC resistance power-on reset voltage input capacitance LOW-level input voltage HIGH-level input voltage HIGH-level output current LOW-level output current voltage voltage resistance resistance
VLCD bias. outputs open-circuit; inputs VDD; external clock with duty factor; I2C-bus inactive. Resets logic when VPOR. Periodically sampled, tested. Outputs measured time.
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Parameter supply voltage supply voltage supply current: low-power mode supply current
Conditions
Unit
fclk VLCD fclk kHz; connected pins CLK, SYNC, OSC, pins CLK, SYNC, OSC, pins SYNC VSS; pins CLK, SCL, SDA, pins
0.7VDD
0.3VDD 0.05 0.3VDD
0.05
0.7VDD
I2C-bus; pins
outputs
Cbpl pins Csgm pins VLCD pins VLCD pins
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Universal driver multiplex rates
11.1 Typical supply current characteristics
mbe530 mbe529
(µA) normal mode
-IDD(LCD) (µA)
power-saving mode
(Hz)
(Hz)
VLCD Tamb
VLCD Tamb
function
-IDD(LCD) function
(µA) normal mode fclk
mbe528
-IDD(LCD) (µA)
mbe527
power-saving mode fclk
VLCD external clock; Tamb
VLCD external clock; Tamb
function
-IDD(LCD) function
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11.2 Typical output characteristics
mbe532 mbe526
RO(max)
RO(max)
10-1
Tamb (°C)
VLCD Tamb
VLCD
RO(max) function
RO(max) function Tamb
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Dynamic characteristics
Table Dynamic characteristics VLCD Tamb unless otherwise specified. Symbol fclk Parameter clock frequency power saving mode; tclk(H) tclk(L) tSYNC_NL tPD(drv) tBUF tHD;STA tSU;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO
Conditions
Unit
Timing characteristics: driver timing waveforms (see Figure normal mode; VLCD
clock HIGH time clock time SYNC time driver propagation delay free time between STOP START condition hold time (repeated) START condition set-up time repeated START condition period clock HIGH period clock rise time both signals fall time both signals capacitive load each line data set-up time data hold time set-up time STOP condition
tPD(SYNC_N) SYNC propagation delay
Timing characteristics: I2C-bus (see Figure
fclk kHz, I2C-bus maximum transmission speed derated. timing values valid within operating supply voltage ambient temperature range referenced with input voltage swing VDD.
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1/fCLK tclk(H) tclk(L) 0.7VDD 0.3VDD
0.7VDD SYNC 0.3VDD tPD(SYNC_N) tSYNC_NL BP3, (VDD tPD(drv)
mce424
tPD(SYNC_N)
Driver timing waveforms
tBUF
tLOW
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA tSU;STO
mga728
I2C-bus timing waveforms
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Semiconductors
PCF8576C
Universal driver multiplex rates
Application information
13.1 Cascaded operation
large display configurations, PCF8576Cs recognized same I2C-bus using 3-bit hardware subaddress (A0, programmable I2C-bus slave address (SA0).
Table Cluster Addressing cascaded PCF8576C Device
Cascaded PCF8576Cs synchronized. They share backplane signals from devices cascade. Such arrangement cost-effective large applications since backplane outputs only device need through-plated backplane electrodes display. other PCF8576Cs cascade contribute additional segment outputs their backplane outputs left open-circuit (see Figure 29). PCF8576C also cascaded with PCF8566. connections identical PCF8576C cascade.
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Product data sheet
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SYNC
VLCD segment drives PANEL
PCF8576CT
13,15, 14,16 (open-circuit) 2560 elements)
VLCD HOST MICROPROCESSOR/ MICROCONTROLLER SYNC
mbe533
VLCD
segment drives
PCF8576CT
13,15, 14,16
backplanes
Cascaded PCF8576C configuration
SYNC line provided maintain correct synchronization between cascaded PCF8576Cs. This synchronization guaranteed after power-on reset. only time that SYNC likely needed synchronization accidentally lost (e.g. noise adverse electrical environments; defining multiplex mode when PCF8576Cs with differing levels cascaded). SYNC organized input/output pin; output selection being realized open-drain driver with internal pull-up resistor. PCF8576C asserts SYNC line monitors SYNC line other times. synchronization cascade lost, restored first PCF8576C assert SYNC. timing relationship between backplane waveforms SYNC signal various drive modes PCF8576C shown Figure single plane wiring packaged PCF8576Cs chip-on-glass cascading, Figure
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Product data sheet
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Semiconductors
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Universal driver multiplex rates
SYNC
static drive mode.
(1/2 bias)
(1/3 bias)
SYNC
multiplex drive mode.
(1/3 bias)
SYNC
multiplex drive mode.
(1/3 bias)
SYNC
multiplex drive mode.
mgl755
Excessive capacitive coupling between SYNC will cause erroneous synchronization. this problem increase capacitance SYNC line (e.g. external capacitor between SYNC VDD.) Degradation positive edge SYNC pulse countered external pull-up resistor.
Synchronization cascade various PCF8576C drive modes
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Product data sheet
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PCF8576C
Universal driver multiplex rates
SYNC VLCD SYNC VLCD open backplanes segments
mbe537
PCF8576CT
PCF8576CT
Single plane wiring packaged PCF8576CTs
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Product data sheet
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Universal driver multiplex rates
Package outline
LQFP64: plastic profile quad flat package; leads; body SOT314-2
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 10.1 0.75 0.45 0.12 1.45 1.05 1.45 1.05
12.15 12.15 11.85 11.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT314-2 REFERENCES 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT314-2 (LQFP64) PCF8576CH
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Product data sheet
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Universal driver multiplex rates
VSO56: plastic very small outline package; leads
SOT190-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 0.13 0.012 0.004 0.12 0.11 0.25 0.01 0.42 0.30 0.22 0.14 21.65 21.35 11.1 11.0 0.75 15.8 15.2 2.25 0.089 0.063 0.055 1.45 1.30 0.90 0.55
0.017 0.0087 0.85 0.012 0.0055 0.84
0.44 0.62 0.0295 0.43 0.60
0.057 0.035 0.008 0.004 0.004 0.051 0.022
Notes Plastic metal protrusions (0.012 inch) maximum side included. Plastic interlead protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT190-1 REFERENCES JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 97-08-11 03-02-19
Package outline SOT190-1 (VSO56) PCF8576CT
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Product data sheet
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Semiconductors
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Universal driver multiplex rates
HTSSOP56: plastic thermal enhanced thin shrink small outline package; leads; body width exposed
SOT793-1
exposed
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.05 0.80 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.08
Notes Plastic metal protrusions 0.15 maximum side included. Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT793-1 REFERENCES 143E36T JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 03-03-04
Package outline SOT793-1 (HTSSOP56) PCF8576CTT
PCF8576C_9 B.V. 2009. rights reserved.
Product data sheet
Rev. July 2009
Semiconductors
PCF8576C
Universal driver multiplex rates
Bare outline
Wire bond die; bonding pads; 2.82 0.38 PCF8576CU/10
detail Dimensions Unit e(3) P1(1) P2(2) P3(1) P4(2) scale
0.610 0.38 2.82 3.00 0.110 0.097 0.110 0.097 0.096
Note size Passivation opening Dimension drawn scale Marking code: PC8576C-1 Outline version PCF8576CU/10 References JEDEC JEITA European projection
pcf8576cu_10_do
Issue date 09-06-02
Bare outline PCF8576CU/10
PCF8576C_9 B.V. 2009. rights reserved.
Product data sheet
Rev. July 2009
Semiconductors
PCF8576C
Universal driver multiplex rates
Wire bond die; bonding pads; 2.82 0.38
PCF8576CU
detail Dimensions Unit e(3) P1(1) P2(2) P3(1) P4(2) scale
0.610 0.38 2.82 3.00 0.110 0.097 0.110 0.097 0.096
Note size Passivation opening Dimension drawn scale Marking code: PC8576C-1 Outline version PCF8576CU References JEDEC JEITA European projection
pcf8576cu_do
Issue date 29-06-02
Bare outline PCF8576CU
PCF8576C_9 B.V. 2009. rights reserved.
Product data sheet
Rev. July 2009
Semiconductors
PCF8576C
Universal driver multiplex rates
Bare die; bumps; 2.82 0.40
PCF8576CU/2
detail detail Dimensions Unit 2.82 3.00 0.096 e(1) 0.610 0.094 scale
0.398 0.0175 0.380 0.094
Note Dimension drawn scale Marking code: PC8576C-2 Outline version PCF8576CU/2 References JEDEC JEITA European projection
pcf8576cu_2_do
Issue date 09-06-02
Bare outline PCF8576CU/2
PCF8576C_9 B.V. 2009. rights reserved.
Product data sheet
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Universal driver multiplex rates
Table bump description PCF8576CU coordinates represent position center each with respect center (x/y chip. Symbol SYNC VLCD
PCF8576C_9
(µm) 1087 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1074 -258 -418 -591 -751 -924 -1084 -1290 -1290 -1290 -1290 -1290
(µm) -1380 -1380 -1380 -1380 -1380 -1380 -1380 -1284 -1116 -945 -751 -485 1124 1284 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1243 1083
Description I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization input/output external clock input/output supply voltage internal oscillator enable input subaddress input subaddress input subaddress input subaddress input logic ground supply voltage backplane output backplane output backplane output backplane output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output
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Product data sheet
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Universal driver multiplex rates
Table bump description PCF8576CU coordinates represent position center each with respect center (x/y chip. Symbol Table Symbol (µm) -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1083 -923 -750 -590 -417 -257 (µm) -249 -422 -582 -755 -915 -1088 -1248 -1380 -1380 -1380 -1380 -1380 -1380 Description segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output segment output
Alignment marks (µm) -1290 -1295 1305 (µm) 1385 -1385 -1405
Handling information
input output pins protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that normal precautions taken described JESD625-A, 61340-5 equivalent standards.
Packing information
17.1 Tray information
Tray information PCF8576CU PCF8576CU/2 shown Figure Figure Table
PCF8576C_9
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Product data sheet
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Semiconductors
PCF8576C
Universal driver multiplex rates
001aai237
Tray details
marking code
001aaj619
Tray alignment Table Symbol
PCF8576C_9
Tray dimensions Description pocket pitch; direction pocket pitch; direction pocket width; direction pocket width; direction Value 5.59 6.35 3.22 3.50
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Product data sheet
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PCF8576C
Universal driver multiplex rates
Tray dimensions Description tray width; direction tray width; direction corner pocket center corner pocket center tray thickness tray cross section tray cross section pocket depth number pockets; direction number pockets; direction Value 50.67 50.67 5.78 6.29 3.94 1.76 2.46 0.89
Table Symbol
PCF8576C_9
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Product data sheet
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Universal driver multiplex rates
17.2 Film frame carrier information
lane
detail
Marking code
Straight edge wafer
013aaa112
Layout wafer film frame carrier PCF8576CU/10
PCF8576C_9
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Product data sheet
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Semiconductors
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Universal driver multiplex rates
Soldering packages
This text provides very brief insight into complex technology. more in-depth account soldering found Application Note AN10365 "Surface mount reflow soldering description".
18.1 Introduction soldering
Soldering most common methods through which packages attached Printed Circuit Boards (PCBs), form electrical circuits. soldered joint provides both mechanical electrical connection. There single soldering method that ideal packages. Wave soldering often preferred when through-hole Surface Mount Devices (SMDs) mixed printed wiring board; however, suitable fine pitch SMDs. Reflow soldering ideal small pitches high densities that come with increased miniaturization.
18.2 Wave reflow soldering
Wave soldering joining technology which joints made solder coming from standing wave liquid solder. wave soldering process suitable following:
Through-hole components Leaded leadless SMDs, which glued surface printed circuit board
SMDs wave soldered. Packages with solder balls, some leadless packages which have solder lands underneath body, cannot wave soldered. Also, leaded SMDs with leads having pitch smaller than ~0.6 cannot wave soldered, increased probability bridging. reflow soldering process involves applying solder paste board, followed component placement exposure temperature profile. Leaded packages, packages with solder balls, leadless packages reflow solderable. characteristics both wave reflow soldering are:
Board specifications, including board finish, solder masks vias Package footprints, including solder thieves orientation moisture sensitivity level packages Package placement Inspection repair Lead-free soldering versus SnPb soldering
18.3 Wave soldering
characteristics wave soldering are:
Process issues, such application adhesive flux, clinching leads, board
transport, solder wave parameters, time during which components exposed wave
Solder bath specifications, including temperature impurities
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Universal driver multiplex rates
18.4 Reflow soldering
characteristics reflow soldering are:
Lead-free versus SnPb soldering; note that lead-free reflow process usually leads
higher minimum peak temperatures (see Figure than SnPb process, thus reducing process window
Solder paste printing issues including smearing, release, adjusting process
window large small components board
Reflow temperature profile; this profile includes preheat, reflow which board
heated peak temperature) cooling down. imperative that peak temperature high enough solder make reliable solder joints solder paste characteristic). addition, peak temperature must enough that packages and/or boards damaged. peak temperature package depends package thickness volume classified accordance with Table
Table SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) Table Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) 2000 2000
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, indicated packing, must respected times. Studies have shown that small packages reach higher temperatures during reflow soldering, Figure
PCF8576C_9
B.V. 2009. rights reserved.
Product data sheet
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Universal driver multiplex rates
temperature
maximum peak temperature limit, damage level
minimum peak temperature minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Temperature profiles large small components
further information temperature profiles, refer Application Note AN10365 "Surface mount reflow soldering description".
PCF8576C_9
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Product data sheet
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Universal driver multiplex rates
Abbreviations
Table Acronym Abbreviations Description Direct Current Film Frame Carrier Human Body Model Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display Least Significant Machine Model Metal Oxide Semiconductor Most Significant Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Resistance-Capacitance Random Access Memory Root Mean Square Serial Clock Line Serial Data Line Surface Mount Device
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Universal driver multiplex rates
Revision history
Table Revision history Release date 20090709 Data sheet status Product data sheet Change notice Supersedes PCF8576C_8 Document PCF8576C_9 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Symbols updated checked with Symbols Library Changed values limiting values table (see Table from relative absolute values Added type Added bare outline drawings Added information Rewritten chapter (see Section 7.3) Product specification Product specification Product specification Product specification Product specification Product specification Product specification Product specification PCF8576C_7 PCF8576C_6 PCF8576C_5 PCF8576C_4 PCF8576C_3 PCF8576C_2 PCF8576C_1
PCF8576C_8 PCF8576C_7 PCF8576C_6 PCF8576C_5 PCF8576C_4 PCF8576C_3 PCF8576C_2 PCF8576C_1
20041122 20011002 19980730 19971114 19970402 19970203 19961209 19950630
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Product data sheet
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Universal driver multiplex rates
Legal information
21.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
21.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights. Bare tested compliance with their related technical specifications stated this data sheet point wafer sawing handled accordance with Semiconductors storage transportation conditions. there data sheet limits guaranteed, these will separately indicated data sheet. There post-packing tests performed individual wafers. Semiconductors control third party procedures sawing, handling, packing assembly die. Accordingly, Semiconductors assumes liability device functionality performance systems after third party sawing, handling, packing assembly die. responsibility customer test qualify their application which used. sales conditioned upon subject customer entering into written sale agreement with Semiconductors through legal department. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
21.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification.
21.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
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Product data sheet
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Universal driver multiplex rates
Contents
7.4.1 7.4.2 7.4.3 7.4.4 7.5.1 7.5.2 7.10 7.11 7.12 7.13 7.14 7.14.1 7.14.2 7.15 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.3.1 8.3.2 8.3.3 8.3.4 General description Features Ordering information Marking Block diagram Pinning information Pinning description Functional description Power-on-reset bias generator. voltage selector drive mode waveforms Static drive mode Multiplex drive mode Multiplex drive mode multiplex drive mode Oscillator. Internal clock. External clock Timing Display register Shift register Segment outputs. Backplane outputs Display Data pointer Sub-address counter Bank selector Output bank selector. Input bank selector Blinker. Basic architecture Characteristics I2C-bus transfer START STOP conditions System configuration Acknowledge PCF8576C I2C-bus controller Input filter I2C-bus protocol Command decoder Mode command Load data pointer command Device select command Bank select command 8.3.5 11.1 11.2 13.1 17.1 17.2 18.1 18.2 18.3 18.4 21.1 21.2 21.3 21.4 Blink command. Display controller Internal circuitry Limiting values Static characteristics Typical supply current characteristics. Typical output characteristics Dynamic characteristics Application information Cascaded operation Package outline Bare outline Handling information Packing information Tray information Film frame carrier information Soldering packages Introduction soldering. Wave reflow soldering Wave soldering. Reflow soldering. Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
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Universal driver multiplex rates Rev. July 2009 Product data shee

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