EBE21RD4AEFA (256M words bits, Ranks) Density: Organization 256M

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EBE21RD4AEFA (256M words bits, Ranks) Density: Organization 256M

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Registered DDR2 SDRAM DIMM
EBE21RD4AEFA (256M words bits, Ranks)
Density: Organization 256M words bits, ranks Mounting pieces 512M bits DDR2 SDRAM sealed FBGA Package: 240-pin socket type dual line memory module (DIMM) height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) Power supply: 1.8V 0.1V Data rate: 533Mbps/400Mbps (max.) Four internal banks concurrent operation (components) Interface: SSTL_18 Burst lengths (BL): /CAS Latency (CL): Precharge: auto precharge operation each burst access Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Posted /CAS programmable additive latency better command data efficiency Off-Chip-Driver Impedance Adjustment On-DieTermination better signal quality /DQS disabled single-ended Data Strobe operation piece clock driver, pieces register driver piece serial EEPROM bits EEPROM) Presence Detect (PD)
Document E0671E31 (Ver. 3.1) Date Published February 2006 Japan Printed Japan URL: http://www.elpida.com
This Product became November, 2006.
Elpida Memory, Inc. 2005-2006
EBE21RD4AEFA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin* (CL-tRCD-tRP) DDR2-533 (4-4-4) DDR2-400 (3-3-3) Contact
Part number EBE21RD4AEFA-5C-E EBE21RD4AEFA-4A-E
Package 240-pin DIMM (lead-free)
Mounted devices EDE5104AESK -5C-E
Gold
EDE5104AESK -5C-E EDE5104AESK -4A-E
Notes: Module /CAS latency component
Configurations
Front side
name VREF /DQS0 DQS0 /DQS1 DQS1 /RESET DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2
Data Sheet E0671E31 (Ver. 3.1)
Back side
name
name DQS9 /DQS9 DQ12 DQ13
name /CK0 /RAS /CS0 ODT0 DQ36
NC/Par_In /CAS /CS1 ODT1 DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35
DQS10 /DQS10 DQ14 DQ15 DQ20 DQ21 DQS11 /DQS11
DQ37 DQS13 /DQS13 DQ38 DQ39
DQ44
EBE21RD4AEFA
name DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26 name DQ40 DQ41 /DQS5 DQS5 DQ42 DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 name DQ22 DQ23 DQ28 DQ29 DQS12 /DQS12 DQ30 DQ31 DQS17 /DQS17 CKE1 name DQ45 DQS14 /DQS14 DQ46 DQ47 DQ52 DQ53 DQS15 /DQS15 DQ54 DQ55 DQ60 DQ61 DQS16 /DQS16 DQ62 DQ63 VDDSPD
DQ27 /DQS8 DQS8 CKE0 NC/Err_Out
Data Sheet E0671E31 (Ver. 3.1)
/DQS7 DQS7 DQ58 DQ59
EBE21RD4AEFA
Description
name (AP) BA0, DQ63 /RAS /CAS Function Address input address Column address Auto precharge Bank select address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground
/CS0, /CS1 CKE0, CKE1 /CK0 VDDSPD VREF ODT0, ODT1 /RESET Par_In*
DQS0 DQS17, /DQS0 /DQS17
control connection
Reset (forces register inputs low)
Parity address control
Err_Out*
Parity error found address control
Notes: Reset connected both reset register. NC/Err_Out (pin NC/Par_In (pin optional function check address command parity.
Data Sheet E0671E31 (Ver. 3.1)
EBE21RD4AEFA
Serial Matrix*1
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments bytes bytes DDR2 SDRAM SSTL 1.8V 3.75ns* 5.0ns* 0.5ns* 0.6ns* 7.8µs Registered Normal Weak Driver 3.75ns* 5.0ns* 0.5ns* 0.6ns*
Refresh rate/type Reserved Reserved
Data Sheet E0671E31 (Ver. 3.1)
Voltage interface level this assembly
SDRAM cycle time, SDRAM access from clock (tAC)
DIMM configuration type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency
DIMM type information SDRAM module attributes
SDRAM device attributes: General Minimum clock cycle time Maximum data access time (tAC) from clock
Minimum clock cycle time Maximum data access time (tAC) from clock Minimum precharge time (tRP)
Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD)
5.0ns* 0.6ns*
15ns
7.5ns 15ns
EBE21RD4AEFA
Byte
Function described Minimum active precharge time (tRAS)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
value
Comments 45ns 40ns 0.25ns* 0.35ns* 0.38ns* 0.48ns* 0.10ns* 0.15ns* 0.23ns* 0.28ns* 15ns*
Module rank density Address command setup time before clock (tIS) Address command hold time after clock (tIH) Data input setup time before clock (tDS)
Revision relock time
Data Sheet E0671E31 (Ver. 3.1)
Data input hold time after clock (tDH)
Write recovery time (tWR)
Internal write read command delay (tWTR) Internal read precharge command delay (tRTP) Memory analysis probe characteristics Extension Byte Active command period (tRC)
Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew Data hold skew (tQHS)
Checksum bytes
Manufacturer's JEDEC code Manufacturer's JEDEC code
7.5ns* 10ns*
7.5ns*
Undefined 60ns*
105ns* 8ns*
0.30ns* 0.35ns* 0.40ns* 0.45ns*
15µs Rev. Continuation code
Elpida Memory
EBE21RD4AEFA
Byte
Function described Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
value
Comments
(ASCII-8bit code) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Revision code Revision code
Data Sheet E0671E31 (Ver. 3.1)
Module part number Module part number
Module part number Module part number Module part number
Module part number Module part number Module part number
Manufacturing date Manufacturing date Module serial number
Manufacture specific data
Notes: These specifications defined based component specification, module.
EBE21RD4AEFA
Block Diagram
/RCS1 /RCS0 DQS0 /DQS0
/DQS /DQS
DQS9 /DQS9 /DQ7
/DQS /DQS
DQS1 /DQS1
DQS10 /DQS10 /DQS /DQS
/DQS /DQS
DQ11
DQ12 DQ15
DQS2
DQS11 /DQS11 /DQS /DQS
/DQS /DQS
/DQS2 DQ16 DQ19 DQS3 /DQS3 DQ24 DQ27 DQS4 /DQS4 DQ32 DQ35 DQS5 /DQS5 DQ40 DQ43 DQS6 /DQS6 DQ48 DQ51 DQS7 /DQS7 DQ56 DQ59 DQS8 /DQS8
/CS0*2 /CS1*2 /RAS /CAS CKE0 CKE1 /ODT0 /ODT1
DQ20 DQ23
DQS12 /DQS12 /DQS /DQS
/DQS /DQS
DQ28 DQ31
DQS13 /DQS13 /DQS /DQS
/RST
DQ36 DQ39
/DQS
/DQS
DQS14 /DQS14 /DQS
/DQS /DQS
/DQS
DQ44 DQ47
DQS15 /DQS15 /DQS
/DQS /DQS
/DQS
DQ52 DQ55
DQS16
/DQS16
/DQS /DQS
/DQS
/DQS
DQ60 DQ63
DQS17
/DQS17
/DQS
/DQS
/DQS
/DQS
/RCS0 /CS: SDRAMs /RCS1 /CS: SDRAMs RBA0 RBA1 BA1: SDRAMs RA13 A13: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs RCKE0 CKE: SDRAMs RCKE1 CKE: SDRAMs /RWE /WE: SDRAMs RODT0 ODT: SDRAMs RODT1 ODT: SDRAMs
D35: 512M bits DDR2 SDRAM bits EEPROM PLL: CUA877 Register: SSTUA32866
Serial
/RESET*3 PCK7*3
/PCK7*3 /CK0 /RESET
Notes: wring changed within nibble. /CS0 connects D/CS /CS1 connects /CSR VREF register1 register2. /CS1 connects D/CS /CS0 connects /CSR register3 register4. /RESET, PCK7 /PCK7 connect registers. PCK0 PCK6, PCK8, PCK9 SDRAMs /ODT connect register. /PCK0 /PCK6, /PCK8, /PCK9 /CK: SDRAMs Other signals connect four registers. PCK7 register /PCK7 /CK: register
VDDSPD
Serial
Data Sheet E0671E31 (Ver. 3.1)
EBE21RD4AEFA
Differential Clock Wiring (CK0, /CK0)
(nominal) SDRAM stack
OUT1
SDRAM stack
/CK0
Data Sheet E0671E31 (Ver. 3.1)
Register Register OUT'N' Feedback Feedback Register Register
Notes: clock delay from input clock input SDRAM register willl (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located close input possible.
EBE21RD4AEFA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol Tstg Value -0.5 +2.3 -0.5 +2.3 +100 Unit Note
Notes: DDR2 SDRAM component specification. Supporting +85°C being able extend +95°C with doubling auto-refresh commands frequency 32ms period (tREFI 3.9µs) higher temperature self-refresh entry control EMRS required. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Operating Conditions +85°C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Input reference voltage Termination voltage input logic high input input logic high input
Data Sheet E0671E31 (Ver. 3.1)
Notes: value VREF selected user provide optimum noise margin system. Typically value VREF expected about VDDQ transmitting device VREF expected track variations VDDQ. Peak peak noise VREF exceed VREF (DC). transmitting device must track VREF receiving device. VDDQ must equal VDD.
Symbol VDD, VDDQ VDDSPD VREF (DC) (DC) (AC) (AC)
min. 0.49 VDDQ VREF 0.04 -0.3
typ.
max.
Unit
Notes
VREF VREF 0.125 VREF 0.250
0.50 VDDQ 0.51 VDDQ VREF 0.04 VDDQ 0.3V VREF 0.125 VREF 0.250
EBE21RD4AEFA
Characteristics +85°C, 1.8V 0.1V,
Parameter Symbol Grade IDD0 3250 3660 Unit Test condition bank; (IDD), (IDD), tRAS tRAS min.(IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING bank; IOUT 0mA; CL(IDD), (IDD), (IDD), tRAS tRAS min.(IDD); tRCD tRCD (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD); Other control address inputs SWITCHING; Data inputs SWITCHING banks open; Fast Exit (IDD); MRS(12) Other control address inputs STABLE; Slow Exit Data inputs MRS(12) FLOATING banks open; (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING banks open, continuous burst reads, IOUT 0mA; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W
Operating current (ACT-PRE)
Operating current (ACT-READ-PRE) IDD1
3980 3560
Precharge power-down standby current Precharge quiet standby current Idle standby current Active power-down standby current Active standby current Operating current (Burst read operating) Operating current (Burst write operating)
Data Sheet E0671E31 (Ver. 3.1)
1470 1250
IDD2P
IDD2Q
1650 1430 2010 1790 1470
IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W
1250 2940 2710 4830 4140 4830 4140
banks open, continuous burst writes; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING
EBE21RD4AEFA
Parameter
Symbol
Grade
6200
Unit
Test condition (IDD); Refresh command every tRFC (IDD) interval; between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Self Refresh Mode; 0.2V; Other control address inputs FLOATING; Data inputs FLOATING bank interleaving reads, IOUT 0mA; CL(IDD), tRCD (IDD) (IDD); (IDD), (IDD), tRRD tRRD(IDD), tRCD (IDD); between valid commands; Address inputs STABLE during DESELECTs; Data pattern same IDD4W;
Auto-refresh current
IDD5 5710
Self-refresh current
IDD6
Operating current (Bank interleaving)
7420
Notes:
Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD)
Data Sheet E0671E31 (Ver. 3.1)
IDD7 6850
specifications tested after device properly initialized. Input slew rate specified Input Test Condition. parameters specified with disabled. Data consists DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, /UDQS. values must with combinations EMRS bits Definitions defined (AC) (max.) defined (AC) (min.) STABLE defined inputs stable level FLOATING defined inputs VREF VDDQ/2 SWITCHING defined inputs changing between every other clock cycle (once clocks) address control signals, inputs changing between every other data transfer (once clock) signals including masks strobes. Refer Timing Test Conditions.
Timing Test Conditions purposes testing, following parameters utilized.
DDR2-533 4-4-4 3.75 70000 DDR2-400 3-3-3
70000
Unit
EBE21RD4AEFA
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value 0.603 0.603 VDDQ +13.4 -13.4 Unit Notes VDDQ VOUT
Minimum required output pull-up under test load Maximum required output pull-down under test load Output timing measurement reference level VOTR Output minimum sink current Output minimum source current
Notes:
Parameter differential input voltage
Data Sheet E0671E31 (Ver. 3.1)
VDDQ device under test referenced. VDDQ 1.7V; VOUT 1.42V. VDDQ 1.7V; VOUT 0.28V. value VREF applied receiving device expected VTT. After calibration 25°C, VDDQ 1.8V.
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Symbol min. VDDQ 0.175 VDDQ 0.125 max. VDDQ VDDQ 0.175 VDDQ 0.125 Unit Note
differential cross point voltage differential cross point voltage
Notes: VID(AC) specifies input differential voltage |VTR -VCP| required switching, where true input signal (such DQS, LDQS UDQS) complementary input signal (such /CK, /DQS, /LDQS /UDQS). minimum value equal VIH(AC) VIL(AC). typical value VIX(AC) expected about VDDQ transmitting device VIX(AC) expected track variations VDDQ VIX(AC) indicates voltage which differential input signals must cross. typical value VOX(AC) expected about VDDQ transmitting device VOX(AC) expected track variations VDDQ VOX(AC) indicates voltage which differential output signals must cross.
(AC) (AC) (AC)
VDDQ
VSSQ
Differential Signal Levels*1,
Crossing point
EBE21RD4AEFA
Electrical Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter effective impedance value EMRS (A6, effective impedance value EMRS (A6, effective impedance value EMRS (A6, Deviation with respect VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) Unit Notes
Note: Test condition measurements. Measurement Definition Rtt(eff) Apply (AC) (AC) test separately, then measure current I(VIH(AC)) I(VIL(AC)) respectively. VIH(AC), VDDQ values defined SSTL_18.
Parameter Output impedance Output slew rate Parameter Input capacitance Input capacitance Data input/output capacitance
Data Sheet E0671E31 (Ver. 3.1)
Rtt(eff)
VIH(AC) VIL(AC) I(VIH(AC)) I(VIL(AC))
Measurement Definition Measure voltage (VM) test (midpoint) with load.
VDDQ
100%
Default Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Pull-up pull-down mismatch
Notes: Impedance measurement condition output source current: VDDQ 1.7V; VOUT 1420mV; (VOUT-VDDQ)/IOH must less than 23.4 values VOUT between VDDQ VDDQ-280mV. Impedance measurement condition output sink current: VDDQ 1.7V; VOUT 280mV; VOUT/IOL must less than 23.4 values VOUT between 280mV. Mismatch absolute value between pull pull down, both measured same temperature voltage. Slew rate measured from VIL(AC) VIH(AC). absolute value slew rate measured from equal greater than slew rate measured from This guaranteed design characterization.
Capacitance 25°C, 1.8V 0.1V)
Symbol Pins Address, /RAS, /CAS, /WE, /CS, CKE, DQS, /DQS, min.
Notes: Register component specification. component specification. DDR2 SDRAM component specification.
12.6
23.4
Unit V/ns
Notes
max.
Unit Notes
EBE21RD4AEFA
Characteristics +85°C VDD, VDDQ 1.8V 0.1V, (DDR2 SDRAM Component Specification)
Frequency (Mbps) Parameter /CAS latency Active read write command delay Precharge command period Active active/auto refresh command time output access time from output access time from high-level width low-level width half period Symbol tRCD tDQSCK tIPW tDIPW tDQSQ min. -500 -450 0.45 0.45 min. (tCL, tCH) 3750 0.35 min. max. +500 +450 0.55 0.55 8000 max. max. min. -600 -500 0.45 0.45 min. (tCL, tCH) 5000 0.35 min. max. +600 +500 0.55 0.55 8000 max. max. Unit Notes
Clock cycle time input hold time input setup time hold skew factor input high pulse width input pulse width Write postamble Write preamble Read preamble Read postamble Write recovery time
Data Sheet E0671E31 (Ver. 3.1)
Control Address input pulse width each input
input pulse width each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK
DQS-DQ skew associated signals
DQ/DQS output hold time from Write command first latching transition
falling edge setup time falling edge hold time from Mode register command cycle time
Address control input hold time Address control input setup time
Active precharge command Active auto-precharge delay Active bank active bank command period Auto precharge write recovery precharge time
tQHS tQHS tDQSS 0.25 tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tRPRE tRPST tRAS tRAP tRRD tDAL 0.35 0.35 0.35 tRCD min. (tWR/tCK)+ (tRP/tCK) 70000
tQHS 0.25 0.35 0.35 0.25
0.25
0.35 tRCD min. (tWR/tCK)+ (tRP/tCK)
70000
EBE21RD4AEFA
Frequency (Mbps) Parameter Internal write read command delay Internal read precharge command delay Exit self refresh non-read command Exit self refresh read command Exit precharge power down non-read command Exit active power down read command Exit active power down read command (slow exit/low power mode) minimum pulse width (high pulse width) Output impedance test driver delay Symbol tWTR tRTP tXSNR tXSRD tXARD tXARDS tCKE tOIT min. tRFC max.
min. tRFC max. Unit Notes
(+85°C +95°C)
Auto refresh active/auto refresh command tRFC time Average periodic refresh interval tREFI (0°C +85°C) tREFI
Minimum time clocks remains after tDELAY asynchronously drops
Notes:
each terms above, already integer, round next higher integer. Additive Latency. defines which active power down exit timing applied. figures Input Waveform Timing referenced from input signal crossing VIH(AC) level rising signal VIL(AC) falling signal applied device under test. figures Input Waveform Timing referenced from input signal crossing VIH(DC) level rising signal VIL(DC) falling signal applied device under test.
/DQS
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
Input Waveform Timing (tDS, tDH)
Input Waveform Timing (tIS, tIH)
Data Sheet E0671E31 (Ver. 3.1)
EBE21RD4AEFA
Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter turn-on delay turn-on turn-on (power down mode) turn-off delay turn-off turn-off (power down mode) power down entry latency power down exit latency Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tAC(min) tAC(min) 2000 tAC(min) tAC(min) 2000 tAC(max) 1000 2tCK tAC(max) 1000 tAC(max) 2.5tCK tAC(max) 1000 Unit Notes
Notes: turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD.
Parameter Input reference voltage
Data Sheet E0671E31 (Ver. 3.1)
Input Test Conditions
Symbol VREF VSWING(max.) SLEW Value VDDQ Unit V/ns Notes
Input signal maximum peak peak swing Input signal maximum slew rate
Notes: Input waveform timing referenced input signal crossing through VREF level applied device under test. input signal minimum slew rate maintained over range from VIL(DC) (max.) VIH(AC) (min.) rising edges range from VIH(DC) (min.) VIL(AC) (max.) falling edges shown below figure. timings referenced with input waveforms switching from VIL(AC) VIH(AC) positive transitions VIH(AC) VIL(AC) negative transitions.
Start falling edge input timing
VSWING(max.) Falling slew
(DC)(min.) (AC)(max.)
Rising slew
Start rising edge input timing
VDDQ (AC)(min.) (DC)(min.) VREF
Input Test Signal Wave forms
Measurement point
(DC)(max.) (AC)(max.)
(AC) min. (DC)(max.)
Output Load
EBE21RD4AEFA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX13) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9, AY11) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. BA0, (input pin) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table)
Bank Bank Bank Bank
Data Sheet E0671E31 (Ver. 3.1)
[Bank Select Signal Table]
Remark: VIH. VIL.
(input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH.
(input output pins) Data input output from these pins.
(input output pin) /DQS provide read data strobes output) write data strobes input).
EBE21RD4AEFA
(power supply pins) 1.8V applied. (VDD internal circuit.) VDDSPD (power supply pin) 1.8V applied (For serial EEPROM). (power supply pin) Ground connected. /RESET (input pin) LVCMOS reset input. When /RESET Low, registers reset. Par_IN (Parity input pin) Parity address control bus. Err_Out (Error output pin) Parity error found address control bus.
Data Sheet E0671E31 (Ver. 3.1)
Detailed Operation Part Timing Waveforms
Refer EDE5104AESK, EDE5108AESK datasheet (E0562E). pins component device fixed level module board. DIMM /CAS latency component registered type.
EBE21RD4AEFA
Physical Outline
Unit:
4.00 (DATUM -A-)
Component area (Front)
55.00 1.27 0.10
63.00 133.35
10.00
17.80
4.00
Component area (Back)
3.00
4.00
FULL
Detail
2.50 0.20
Detail
1.00
(DATUM -A-)
4.00
0.20 0.15
2.50
FULL
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
30.00
Data Sheet E0671E31 (Ver. 3.1)
EBE21RD4AEFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
Data Sheet E0671E31 (Ver. 3.1)
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
EBE21RD4AEFA
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Data Sheet E0671E31 (Ver. 3.1)
M01E0107

EBE21RD4AEFA (256M words bits, Ranks) Density: Organization 256M

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