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ADS8255
www.ti.com. SLAS657A 2009 REVISED SEPTEMBER 2009
16-BIT, 1-MSPS, UNIPOLAR SINGLE ENDED WITH ON-CHIP DRIVER (OPA) 8-CHANNEL DIFFERENTIAL MULTIPLEXER
FEATURES
1.0-MHz Sample Rate, Zero Latency Full Speed 16-Bit Resolution Supports Unipolar Single Ended Input Range: Built-In Eight Channel, Single Ended Multiplexer; with Channel Count Selection Auto/Manual Mode On-Board Single Ended Input, Differential Output Driver (OPA) Buffered Reference Output Level Shift Bipolar ±4-V Input with External Resistance Divider Reference/2 Output Offset External Signal Conditioner 16-/8-Bit Parallel Interface SNR: 94.2dB 2-kHz THD: -115dB 2-kHz Power Dissipation: 331.25 MSPS Internal Reference Internal Reference Buffer 64-Pin Package
APPLICATIONS
Medical Imaging/CT Scanners Automated Test Equipment High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems
DESCRIPTION
ADS8255 high-performance analog system-on-chip (SoC) device with 16-bit, 1-MSPS converter, internal reference, on-chip driver (OPA), 8-channel single ended multiplexer. channel count multiplexer auto/manual scan modes device user selectable. driver designed leverage very high noise performance differential optimum power usage levels. ADS8255 outputs buffered reference signal level shifting ±4-V bipolar signal with external resistance divider. Vref/2 output signal available offset signal conditioning circuit. device also includes 16-/8-bit parallel interface. ADS8255 available 64-pin package characterized from -40°C 85°C.
HIGH-SPEED CONVERTER FAMILY
TYPE/SPEED 18-Bit Pseudo-Diff Single Ended ADS8380 ADS8382 18-Bit Pseudo-Bipolar, Fully Diff ADS8482 ADS8327 16-Bit Pseudo-Diff ADS8328 ADS8319 ADS8318 16-Bit Pseudo-Bipolar, Fully Diff ADS8254 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS8406 ADS7890 ADS7883 ADS8413 ADS7891 ADS7881 ADS8372 ADS8472 ADS8402 ADS8412 ADS8422 ADS8370 ADS8371 ADS8471 ADS8255 ADS8401 ADS8405 ADS8411 ADS8410 ADS8285 ADS8284 ADS8484 ADS8383 ~600 ADS8381 ADS8481 1.25 4MHz
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2009, Texas Instruments Incorporated
ADS8255
SLAS657A 2009 REVISED SEPTEMBER 2009. www.ti.com
AUTO, MXCLK
VOLTAGE CLAMP
AGND +VBD BGND
OPA-1 MSPS
D0-D15 LOGIC BUFFER
OPA-2 VCMI
BYTE CONVST BUSY
VCM-O VREF/2
REFIN
BUF-REF
REFM
PD-RBUF
INTERNAL
REFOUT
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These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ±0.75 MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±0.75 MISSING CODES RESOLUTION (BIT) 64-pin ADS8255l ±1.5 -40°C 85°C PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION ADS8255IBRGCT ADS8255IBRGCR ADS8255IRGCT ADS8255IRGCR TRANSPORT MEDIA QUANTITY 2000 2000
ADS8255lB
most current package ordering information, Package Option Addendum this document, refer website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE CH(i) AGND (both inputs) AGND +VBD BDGND control digital input voltage control digital output Multiplexer control digital input voltage Power control digital input voltage Operating temperature range Storage temperature range Junction temperature (TJmax) package Lead temperature, soldering Power dissipation Thermal impedance Vapor phase sec) Infrared sec) VEE-0.3 -0.3 -0.3 -0.3 -0.3 (+VBD 0.3) -0.3 (+VBD 0.3) -0.3 (+VA 0.3) -0.3 (+VCC 0.3) Max-TA)/ °C/W UNIT
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SPECIFICATIONS
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage multiplexer input Absolute input range multiplexer input Input common-mode voltage SYSTEM PERFORMANCE Resolution missing codes
TEST CONDITIONS
UNIT
CH(i)P-CH(i)M [CH(i)P CH(i)M]
-Vref -0.2 (Vref)/2 (Vref)/2
Vref Vref (Vref)/2
ADS8255IB ADS8255I ADS8255IB ADS8255I ADS8255IB ADS8255I ADS8255IB ADS8255I 85°C ADS8255IB ADS8255I External reference 3FFF0H output code. VCC, variation 0.5V individually -0.1 -0.1 16-bit level -0.75 -1.5 -0.75 ±0.4 ±0.4 ±0.32 ±0.32 ±0.05 ±0.05 ±0.025 ±0.025 0.75 0.75
Bits Bits
Integral linearity
Differential linearity Offset error Offset drift Gain error
PPM/°C
Power supply rejection ratio SAMPLING DYNAMICS Conversion time
+VBD +VDB +VBD +VDB
Acquisition time Maximum throughput rate Aperture delay Aperture jitter Settling time Over voltage recovery DYNAMIC CHARACTERISTICS ADS8255I ADS8255IB Total harmonic distortion (THD) ADS8255I ADS8255IB ADS8255I ADS8255IB ADS8255I ADS8255IB Signal noise ratio (SNR) ADS8255I ADS8255IB ADS8255I ADS8255IB
only (OP1, OP2)+ only
-115 -115 -105 -105 -100 -100 94.8 94.8 94.2 94.2 93.5
Ideal input span, does include gain offset error. Measured relative acutal measured referenceThis endpoint INL, best fit. means least significant Calculated first nine harmonics input frequency. Submit Documentation Feedback Product Folder Link(s) :ADS8255
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SPECIFICATIONS (continued)
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER ADS8255I ADS8255IB Signal noise distortion (SINAD) ADS8255I ADS8255IB ADS8255I ADS8255IB ADS8255I ADS8255IB Spurious free dynamic range (SFDR) ADS8255I ADS8255IB ADS8255I ADS8255IB -3dB Small signal bandwidth VOLTAGE REFERENCE INPUT (REFIN) Reference voltage REFIN, Vref Reference input current INTERNAL REFERENCE OUTPUT (REFOUT) Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift BUFFERED REFERENCE OUTPUT (BUF-REF) Output current REFERENCE/2 OUTPUT (VCMO) Output current ANALOG MULTIPLEXER Number channels Channel channel crosstalk Channel selection DIGITAL INPUT-OUTPUT CONTROL PINS Logic Family-CMOS Logic level MULTIPLEXER CONTROL PINS Logic Family CMOS Logic Level POWER CONTROL PINS Logic Family CMOS Logic Level -0.3 +0.3 -0.3 +0.3 loads loads +VBD-1 +VBD-6 +VBD +VBD Auto sequencer with selection channel count Manual selection through control lines REFIN +85°C REFIN 85°C Static load 4.75 5.25 From (+VA), with 1-µF storage capacitor 4.081 4.096 4.111 PPM/°C 4.096 TEST CONDITIONS 94.7 94.7 93.85 93.85 92.2 92.6 UNIT
vary ±20%
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SPECIFICATIONS (continued)
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER POWER SUPPLY REQUIREMENTS +VBD Power supply voltage driver positive supply (VCC) current (for together) driver negative supply (VEE) current (for together) Supply Current, 1MHz Sample Rate Reference buffer (BUF-REF) supply current (VCC GND) TEMPERATURE RANGE Operating free VCC= PD-RBUF Quiescent current PD-RBUF -5V, inputs shorted each other connected inputs shorted each other connected 4.75 4.75 -7.5 11.65 5.25 5.25 TEST CONDITIONS UNIT
PD-RBUF=1 powers down Reference buffer (BUF-REF), note that does 3-state BUF-REF output.
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TIMING CHARACTERISTICS
specifications typical -40°C 85°C, =+VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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TIMING CHARACTERISTICS
specifications typical -40°C 85°C, +VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
MULTIPLEXER TIMING REQUIREMENTS
4.75 -7.5
tsu6 Setup time MXCLK rising edge Multiplexer driver settle time from MXCLK rising edge CONVST falling edge) UNIT
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ASSIGNMENTS
PACKAGE (TOP VIEW)
PD-RBUF AGND VCMI
BUF-REF VCMO AGND REFOUT REFIN REFM REFM AGND CONVST BYTE
ADS8255
+VBD BUSY BGND +VBD
NAME
MULTIPLEXER INPUT PINS INPUT PINS inverting input., connect 1-nF across Inverting input, connect 1-nF across VCMI Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Reference two' input buffer, common mode input signal. Device performance optimized source resistance this input. converts (VCHn VVCMI). VCMO output connected VCMI through resistance. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input.
REFERENCE INPUT/ OUTPUT PINS REFM REFIN REFOUT VCMO BUFREF Reference ground. Reference Input. 0.1-µF decoupling capacitor between REFIN REFM. Reference Output. 1-µF capacitor between REFOUT REFM when internal reference used. This outputs Refin/2 used common-mode voltage differential analog inputs. Buffered reference output. Useful level shift bipolar signals using external resistors.
AUTO MXCLK AGND AGND DB15 DB14 DB13 DB12 DB11 DB10
FUNCTIONS
DESCRIPTION
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FUNCTIONS (continued)
NAME DESCRIPTION
POWER CONTROL PINS PDRBUF High this powers down reference buffer (BUF-REF).
MULTIPLEXER CONTROL PINS AUTO High level this selects `Auto' mode multiplexer scanning. level selects manual mode multiplexer scanning Acts multiplexer address when Auto (manual mode). auto mode (Auto multiplexer channel selection reset rising edge MXCLK while Acts multiplexer address when AUTO=0 (Manual mode). auto mode (AUTO=1) select last multiplexer channel (channel count) auto scan sequence. Acts multiplexer address when AUTO=0 (Manual mode). auto mode (AUTO=1) select last multiplexer channel (channel count) auto scan sequence. Multiplexer channel selected rising edge MXCLK irrespective whether auto manual mode. Device BUSY output connected MXCLK that device selects next channel every sample. necessary allow three MXCLKs after device power During this period device loads factory settings driver amplifier multiplexer.
MXCLK
DATA 42-49, 52-59 Data DB15 DB14 DB13 DB12 DB11 DB10 (MSB) (LSB) 8-BIT BYTE ones ones ones ones ones ones ones ones BYTE D15(MSB) (LSB) 16-BIT BYTE
CONTROL PINS BUSY BYTE CONVST Status output. This held high when device converting. Byte Select Input. Used 8-bit reading. Refer DATA description above. Convert start. This input active independent input. Synchronization pulse parallel output. Chip Select.
DEVICE POWER SUPPLIES AGND +VBD BGND Negative supply (OP1, OP2) Positive supply (OP1, OP2, BUF-REF) Analog power supply. Analog ground. Digital Power Supply Bus. Digital ground interface digital supply.
CONNECTED PINS connection.
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DEVICE OPERATION TIMING DIAGRAMS
ADS8255 analog system-on-chip (SoC) device. device includes multiplexer, single-ended input/differential output driver differential input high-performance ADC, additional internal reference, buffered reference output, REF/2 output. Figure shows basic operation device (including elements). Subsequent sections describe detailed timings individual blocks device (primarily multiplexer ADC).
CONVST
BUSY
SELECTED CHANNEL
(n-1)
(n+1)
(n+2)
(n+3)
Vref differential input assuming alternate channels have+Vref Input SAMPLE, (VChi VCMI) S(m-1) -Vref
S(m) +Vref S(m+1) -Vref S(m+2) +Vref
Parallel
(n-2)
(n-1)
(n+1)
Figure Device Operation shown diagram, device controlled with only (CONVST) digital input. falling edge CONVST, BUSY output device goes high. high level BUSY indicates device sampled signal converting sample into digital equivalent. After conversion complete, BUSY output falls logic level device output data corresponding recently converted sample available reading. recommended (not mandatory) short BUSY output device MXCLK input. device selects channel every rising edge MXCLK. multiplexer differential. multiplexer driver designed settle 16-bit level before sampling; even maximum conversion speed. Control Timing: timing diagrams this section describe operation; multiplexer operation described following sections.
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CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(HOLD) SAMPLING (When Toggle) t(CONV) tpd2
t(CONV)
t(ACQ) BYTE tsu(ABORT) tsu5 tsu5 tpd4 tsu5 tsu5 tsu2 tsu(ABORT)
DB[15:8] Hi-Z D[15:8] DB[7:0]
Signal
tdis Hi-Z D[7:0] Hi-Z D[7:0]
Hi-Z
internal device
Figure Timing Conversion Acquisition Cycles With Toggling
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CONVST tpd1 BUSY tsu6 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) tpd2
t(CONV)
t(ACQ) tsu(ABORT) BYTE tsu5 tdis tpd4 Hi-Z Previous [15:8] Hi-Z D[15:8] DB[7:0] Previous Hi-Z [7:0] Hi-Z D[7:0]
Signal
tsu(ABORT) tsu5 tsu5 tsu5
tsu2 tdis Hi-Z D[7:0] Hi-Z Previous [7:0] Previous [15:8]
DB[15:8]
internal device
Figure Timing Conversion Acquisition Cycles With Toggling, Tied BDGND
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CONVST tpd1 BUSY tpd2
tpd3 CONVERT t(CONV) t(HOLD) t(CONV)
SAMPLING (When tsu(ABORT) BYTE tpd4 DB[15:8] Hi-Z
t(ACQ)
tsu5 tsu5 tdis
tsu(ABORT)
Hi-Z D[15:8] D[7:0] Hi-Z D[7:0]
DB[7:0]
Hi-Z
Signal
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND, Toggling
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CONVST tpd1 BUSY tpd2
CONVERT tpd3 t(HOLD)
t(CONV) tpd3 t(HOLD) t(ACQ)
t(CONV)
SAMPLING (When tsu(ABORT) BYTE tsu5 tdis tsu5 tsu(ABORT)
tsu5 DB[15:8] Previous D[7:0] D[15:8] DB[7:0] D[7:0]
Signal
tsu5
D[7:0] Next D[15:8]
Next D[7:0]
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND Auto Read
tsu4 BYTE Hi-Z Valid tdis Hi-Z Valid Valid tdis Hi-Z
DB[15:0]
Figure Detailed Timing Read Cycles
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Multiplexer: multiplexer modes sequencing namely auto sequencing manual sequencing. Multiplexer mode selection operation controlled with AUTO, MXCLK pins. Auto Sequencing: logic level AUTO selects auto sequencing mode. possible select number channels scanned (always starting from channel zero) auto sequencing mode. Pins select channel count (last channel auto sequence). every rising edge MXCLK while logic zero level, next higher channel ascending order) selected. Channel selection rolls over channel zero rising edge MXCLK after channel selection reaches channel count (last channel auto sequence selected pins C1and C2). time during sequence channel sequence reset channel zero. rising edge MXCLK while logic level resets channel selection channel zero. Table Channel Selection Auto Mode
CHANNEL COUNT PINS CLOCK MXCLK LAST CHANNEL SEQUENCE CHANNEL SEQUENCE 0,1,0,1,0,1,. 0,1,2,3,0,1,2,. 0,1,2,3,4,5,0,1,2,. 0,1,2,3,4,5,6,7,0,1,. (channel reset zero)
MXCLK
tsu6
Selected Channel
AUTO device operation auto mode
Figure Multiplexer Auto Mode Timing Diagram Manual Sequencing: logic zero level AUTO selects manual sequencing mode. Pins C1and channel address. rising edge MXCLK, addressed channel connected driver input. Table Channel Selection Manual Mode
MODE AUTO CHANNEL ADDRESS MXCLK CONNECTED CHANNEL
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Table Channel Selection Manual Mode (continued)
MODE AUTO CHANNEL ADDRESS MXCLK CONNECTED CHANNEL
MXCLK
tsu6
Selected Channel
AUTO device operation manual mode
Figure Multiplexer Manual Mode Timing Diagram
TYPICAL CHARACTERISTICS
HISTOGRAM (without switching)
70000 60000 50000 40000 30000
15000
HISTOGRAM (CH0 with switching CH0-1-0)
40000 35000 30000 25000 20000
Vref 4.096 35183 25°C, Throughput MSPS
INTERNAL REFERENCE VOLTAGE FREE-AIR TEMPERATURE
4.098 4.0975 +VBD
Reference Voltage
32773 32774
Vref 4.096 25C, Throughput MSPS
57619
30289
4.097
4.0965
20000 10000 32770 32771 32772 7164
4.096 4.0955
10000 5000
32771 32772
4.095
Free-Air Temperature
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
INTERNAL REFERENCE VOLTAGE SUPPLY VOLTAGE
4.0972 25°C 4.09719
ANALOG VOLTAGE (+VA) SUPPLY CURRENT (IA) FREE-AIR TEMPERATURE
43.5 Throughput MSPS
Supply Current
43.5 42.5 41.5
SUPPLY CURRENT (IA) ANALOG VOLTAGE (+VA)
25°C Throughput MSPS
Reference Voltage
Supply Current
4.09718 4.09717 4.09716 4.09715 4.09714 4.09713 4.75
42.5 41.5 40.5 Free Temperature
4.85
4.95 5.05 5.15 Supply Voltage
5.25
Analog Voltage
Figure
Figure POSITIVE SUPPLY CURRENT (ICC) FREE-AIR TEMPERATURE
Figure POSITIVE SUPPLY CURRENT (ICC) POSITIVE SUPPLY VOLTAGE (+VCC)
13.9 25°C
ANALOG SUPPLY CURRENT SAMPLE RATE
+VBD 25°C, Vref 4.096
Supply Current
Supply Current
13.8 13.7 13.6 13.5 13.4 13.3 13.2
Supply Current
Sample Rate KSPS
1000
Free Temperature
4.75
5.25
5.75 6.25 6.75 7.25 Supply Voltage
Figure SUPPLY CURRENT (IEE) FREE-AIR TEMPERATURE
12.5
Supply Current
Figure NEGATIVE SUPPLY CURRENT (IEE) NEGATIVE SUPPLY (-VEE)
10.98 10.96 10.94 10.92 10.9 10.88 10.86 10.84 10.82 10.8
Figure DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
Differential Nonlinearity
25°C
0.75 0.25 -0.25 -0.5 -0.75
Channel Vref 4.096 Throughput MSPS
Supply Current
11.5
10.5 Free Temperature
10.78 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 Supply Voltage
Free Temperature
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY ANALOG SUPPLY VOLTAGE (+VA)
Differential Nonlinearity
DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY SUPPLY VOLTAGE (VCC)
Differential Nonlinearity
Differential Nonlinearity
Channel Vref 4.096 0.75 25°C, Throughput MSPS 0.25 -0.25 -0.5 -0.75 4.75 4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
0.75 0.25 -0.25 -0.5 -0.75
Channel 25°C, Throughput MSPS
-0.2 -0.4 -0.6 -0.8
Channel Vref 4.096 25°C, Throughput MSPS, -VEE except where -2.5
VREF Voltage Reference
Supply Voltage
Figure DIFFERENTIAL NONLINEARITY MULTIPLEXER CHANNELS
Figure INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
Channel Vref 4.096 Throughput MSPS
Figure INTEGRAL NONLINEARITY ANALOG SUPPLY VOLTAGE (+VA)
Differential Nonlinearity
Integral Nonlinearity
-0.2 -0.4 -0.6 -0.8
-0.2 -0.4 -0.6 -0.8
Integral Nonlinearity
Vref 4.096 25°C, Throughput MSPS
-0.2 -0.4 -0.6 -0.8 4.75
Channel Vref 4.096 V,TA 25°C, Throughput MSPS
Multiplexer Channels
Free Temperature
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
Figure INTEGRAL NONLINEARITY REFERENCE VOLTAGE
Channel 25C, Throughput MSPS
Figure INTEGRAL NONLINEARITY SUPPLY VOLTAGE (+VCC)
Figure INTEGRAL NONLINEARITY MULTIPLEXER CHANNELS
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
-0.2 -0.4 -0.6 -0.8
-0.2 -0.4 -0.6 -0.8 4.75
-0.2 -0.4 -0.6 -0.8
Channel Vref 4.096 25°C, Throughput MSPS, -VEE except where -2.5
Vref 4.096 25°C, Throughput MSPS Multiplexer Channels
VREF Voltage Reference
5.25
5.75 6.25 6.75 7.25 Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
FULL CHIP OFFSET FREE-AIR TEMPERATURE
Channel Vref 4.096 Throughput MSPS Channel Vref 4.096 25°C, -VEE, Throughput MSPS,
FULL CHIP OFFSET SUPPLY VOLTAGE (VCC)
FULL CHIP OFFSET ANALOG SUPPLY VOLTAGE (+VA)
Channel Vref 4.096 25°C, Throughput MSPS
Full Chip Offset
Full Chip Offset
Full Chip Offset
-100 -150
Free Temperature
Supply Voltage
4.75
4.85
4.95 5.05 5.15 5.25 Supply Voltage
Figure FULL CHIP OFFSET REFERENCE VOLTAGE
Channel 25C, Throughput MSPS
Figure FULL CHIP OFFSET CHANNEL
0.08
Figure FULL CHIP GAIN ERROR FREE-AIR TEMPERATURE
0.07 Channel Vref 4.096 Throughput MSPS
Full Chip Gain Error
Vref 4.096 25°C, Throughput MSPS
Full Chip Offset
VREF Reference
Full Chip Offset
0.06 0.05 0.04 0.03 0.02
-100 -150
Multiplexer Channels
Free Temperature
Figure FULL CHIP GAIN ERROR SUPPLY VOLTAGE (VCC)
0.08 0.07 Channel VREF 4.096 25°C, Throughput MSPS
Figure FULL CHIP GAIN ERROR ANALOG SUPPLY VOLTAGE (+VA)
0.08 0.07 Channel Vref 4.096 V,TA 25°C, Throughput MSPS
Figure FULL CHIP GAIN ERROR REFERENCE VOLTAGE
0.08 0.07
Full Chip Gain Error
Full Chip Gain Error
0.06 0.05 0.04 0.03 0.02 0.01
0.06 0.05 0.04 0.03 0.02
Full Chip Gain Error
0.06 0.05 0.04 0.03 0.02 0.01 Channel 25C, Throughput MSPS VREF Voltage Reference
Supply Voltage
4.75
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
FULL CHIP GAIN ERROR MULTIPLEXER CHANNELS
0.08
SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE
96.2
TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
-110
Signal Noise Ratio
0.07
95.8 95.6 95.4 95.2 94.8 94.6
kHz, Throughput MSPS
Total Harmonic Distortion
Full Chip Gain Error
0.06 0.05 0.04 0.03 0.02 0.01
Vref 4.096 25°C, Throughput MSPS
Channel Vref 4.096
Channel Vref 4.096
-111 -112 -113 -114 -115 -116
kHz, Throughput MSPS
Multiplexer Channels
Free Temperature
Free Temperature
Figure SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
SFDR Spurious Free Dynamic Range
ENOB Effective Number Bits bits
15.6 15.5 15.4 15.3 15.2 15.1
Figure EFFECTIVE NUMBER BITS FREE-AIR TEMPERATURE
Signal Noise Ratio
Figure SIGNAL-TO-NOISE RATIO ANALOG SUPPLY VOLTAGE (+VA)
95.5 95.4 95.3 95.2 95.1 94.9 94.8 94.7 94.6 94.5 4.75
Channel Vref 4.096 25°C, kHz, Throughput MSPS
Channel Vref 4.096
kHz, Throughput MSPS
Channel Vref 4.096 kHz, Throughput MSPS
Free Temperature
Free Temperature
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
Figure TOTAL HARMONIC DISTORTION ANALOG SUPPLY VOLTAGE (+VA)
SFDR Spurious Free Dynamic Range
Figure SPURIOUS FREE DYNAMIC RANGE ANALOG SUPPLY VOLTAGE (+VA)
4.75
Channel Vref 4.096 25°C, kHz, Throughput MSPS
Figure EFFECTIVE NUMBERR BITS ANALOG SUPPLY VOLTAGE (+VA)
15.6
-110
Total Harmonic Distortion
Channel Vref 4.096
-111 -112 -113 -114 -115 -116 4.75
25°C, kHz, Throughput MSPS
ENOB Effective Number Bits bits
15.5 15.4 15.3 15.2 15.1 4.75
Channel Vref 4.096 25°C, kHz, Throughput MSPS
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
4.85 4.95 5.05 5.15 5.25 Analog Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO REFERENCE VOLTAGE
95.4 -110
TOTAL HARMONIC DISTORTION REFERENCE VOLTAGE
SFDR Spurious Free Dynamic Range
SPURIOUS FREE DYNAMIC RANGE REFERENCE VOLTAGE
118.5 117.5 116.5 115.5
Channel 25°C, kHz, Throughput MSPS
Total Harmonic Distortion
95.2
Signal Noise Ratio
94.8 94.6 94.4 94.2 93.8 93.6 93.4 93.2
Channel 25°C, kHz, Throughput MSPS
-111 -112 -113 -114 -115 -116 -117
Channel 25°C, kHz, Throughput MSPS
VREF Voltage Reference
VREF Voltage Reference
VREF Voltage Reference
Figure EFFECTIVE NUMBER BITS REFERENCE VOLTAGE
15.55
95.5
Figure SIGNAL-TO-NOISE RATIO SUPPLY VOLTAGE
95.4 Channel Vref 4.096 kHz, 25°C, Throughput MSPS, -VEE except where -2.5
Figure TOTAL HARMONIC DISTORTION SUPPLY VOLTAGE (VCC)
-110
ENOB Effective Number Bits bits
Signal Noise Ratio
15.5 15.45 15.4 15.35 15.3 15.25 15.2
Channel 25°C, kHz, Throughput MSPS
Total Harmonic Distortion
-111 -112 -113 -114 -115 -116 -117
95.3 95.2 95.1 94.9 94.8 94.7 94.6 94.5
Channel Vref 4.096 kHz, 25°C, Throughput MSPS, -VEE except where -2.5
VREF Voltage Reference
Supply Voltage
Supply Voltage
Figure SPURIOUS FREE DYNAMIC RANGE SUPPLY VOLTAGE (VCC)
SFDR Spurious Free Dynamic Range
ENOB Effective Number Bits bits
15.6 15.5 15.4 15.3 15.2 15.1
Figure EFFECTIVE NUMBER BITS SUPPLY VOLTAGE (VCC)
95.1 95.05
Figure SIGNAL-TO-NOISE RATIO SOURCE RESISTANCE (RIN)
Channel Vref 4.096 25°C, kHz, Throughput MSPS
Signal Noise Ratio
Channel Vref 4.096 kHz, 25°C, Throughput MSPS, -VEE except where -2.5
94.95 94.9 94.85 94.8 94.75 94.7 94.65 94.6 94.55
Channel Vref 4.096 kHz, 25°C, Throughput MSPS, -VEE except where -2.5
Supply Voltage
Supply Voltage
1000 Input Resistance
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION SOURCE RESISTANCE (RIN)
SFDR Spurious Free Dynamic Range
SPURIOUS FREE DYNAMIC RANGE SOURCE RESISTANCE (RIN)
116.4 116.35 116.3 116.25 116.2 116.15 116.1 116.05
Channel 25°C, kHz, Throughput MSPS
EFFECTIVE NUMBER BITS SOURCE RESISTANCE (RIN)
15.5
Total Harmonic Distortion
ENOB Effective Number Bits bits
-113.1 -113.2 -113.3 -113.4 -113.5 -113.6 -113.7 -113.8 -113.9 -114 -114.1 -114.2
Channel Vref 4.096 25°C, kHz, Throughput MSPS
15.48 15.46 15.44 15.42 15.4 15.38 15.36 15.34 15.32 15.3
Channel Vref 4.096 25°C, kHz, Throughput MSPS
Input Resistance
1000
Input Resistance
1000
Input Resistance
1000
Figure SIGNAL-TO-NOISE RATIO MULTIPLEXER CHANNELS
95.5
Signal Noise Ratio
Figure TOTAL HARMONIC DISTORTION MULTIPLEXER CHANNELS
Total Harmonic Distortion
Vref 4.096 kHz, 25°C, Throughput MSPS -112 -113 -114 -115 -116 -117
SFDR Spurious Free Dynamic Range
Figure SPURIOUS FREE DYNAMIC RANGE MULTIPLEXER CHANNELS
-110
Vref 4.096 kHz, 25°C, Throughput MSPS
95.4 95.3 95.2 95.1 94.9 94.8 94.7 94.6 94.5
Vref 4.096 kHz, 25°C, Throughput MSPS Multiplexer Channels
Multiplexer Channels
Multiplexer Channels
Figure EFFECTIVE NUMBER BITS MULTIPLEXER CHANNELS
15.5
Figure VCM_O VOLTAGE SUPPLY VOLTAGE (VCC)
2.04145 2.0414 2.04135 -VEE except where -2.5 Vref 4.096 25°C,
4.0871 4.087
Figure BUFFER REFERENCE OUTPUT VOLTAGE SUPPLY VOLTAGE (VCC)
-VEE except where -2.5 Vref 4.096 25°C
ENOB Effective Number Bits bits
15.45 15.4
BUF_REF Output
VCM_O Voltage
15.35 15.3 15.25 15.2 15.15 15.1 15.05 Vref 4.096 kHz, 25°C, Throughput MSPS Multiplexer Channels
2.0413 2.04125 2.0412 2.04115 2.0411 2.04105
4.0869 4.0868 4.0867 4.0866 4.0865
2.041 2.04095
4.0864
Supply Voltage
Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
TYPICAL
+VBD 25°C, MSPS, Vref 4.096
-0.1 -0.2 -0.3 -0.4 -0.5 10000 20000 30000 Codes Figure 40000 50000 60000
TYPICAL
+VBD 25°C, MSPS, Vref 4.096
-0.2 -0.4 -0.6 10000 20000 30000 Codes 40000 50000 60000
Figure
TYPICAL
-100 -120 -140 -160 -180 -200 Input Frequency kHz, MSPS, 95.2 SFDR SINAD 94.8
Power
100000
200000 300000 Frequency
400000
500000
Figure
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APPLICATION INFORMATION
discussed before, ADS8255 16-bit analog that includes various blocks like multiplexer, driver, internal reference, internal reference buffer, buffered reference output, Ref/2 output on-board. following diagram shows recommended analog digital interfacing ADS8255.
APPLICATION DIAGRAM
AUTO, MXCLK From Host
Signals Source
VOLTAGE CLAMP BUSY MSPS LOGIC BUFFER
OPA-
VCM- OPA-2
Host
BYTE CONVST
VREF/2 VCM-O: REFIN
BUF-REF: application board
REFOUT PD-RBUF Connect this power down `Ref-Buffer' REFM
INTERNAL
Figure Analog Digital Interface Diagram shown Figure ADS8255 accepts unipolar single ended analog input range Vref. application require interfacing bipolar input signals. following diagram shows conversion bipolar input signals unipolar differential signals.
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From BUF-REF (Note current o/p)
True Bipolar, Signals Note: Value depends signal signal kHz. Choose source RC/2
Figure Bipolar Input Signals Unipolar Differential Signals Conversion
MICROCONTROLLER INTERFACING
ADS8255 8-Bit Microcontroller Interface Figure shows parallel interface between ADS8255 typical microcontroller using 8-bit data bus. BUSY signal used falling edge interrupt microcontroller.
Analog
AGND Input Analog Input
REFIN REFM AGND
Micro Controller GPIO GPIO GPIO AD[7:0]
Digital BYTE CONVST DB[17:10] ADS8255 BDGND BDGND +VBD
Data D[17:0]
Figure ADS8255 Application Circuitry
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Analog
AGND
AGND
REFOUT
REFIN
REFM
ADS8255
Figure ADS8255 Using Internal Reference
AGND
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PRINCIPLES OPERATION
ADS8255 features high-speed successive approximation register (SAR) analog-to-digital converter (ADC). architecture based charge redistribution which inherently includes sample/hold function. Figure application circuit ADS8255. conversion clock generated internally. conversion time capable sustaining throughput. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8255 operate with external reference with range from reference voltage input (REFIN) converter internally buffered. clean, noise, well-decoupled reference voltage this required ensure good performance converter. noise band-gap reference like REF5040 used drive this pin. 0.1-µF decoupling capacitor required between REFIN REFM pins (pin converter. This capacitor should placed close possible pins device. Designers should strive minimize routing length traces that connect terminals capacitor pins converter. network also used filter reference voltage. 100- series resistor 0.1-µF capacitor, which also serve decoupling capacitor used filter reference voltage.
REFM
REF5040 REFIN
ADS8255
Figure ADS8255 Using External Reference ADS8255 also limited pass filtering capability built into converter. equivalent circuitry REFIN input shown Figure
REFIN REFM CDAC
CDAC
Figure Simplified Reference Input Circuit REFM input ADS8255 should always shorted AGND. 4.096-V internal reference included. When internal reference used, (REFOUT) connected (REFIN) with 0.1-µF decoupling capacitor 1-µF storage capacitor between (REFOUT) (REFM) (see Figure 72). internal reference converter double buffered. external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion. (REFOUT) left unconnected (floating) external reference used shown Figure 74).
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ANALOG INPUT
ADS8255 features analog multiplexer, high input impedance single ended differential driver, high-performance ADC. Typically would require alot care selection driving circuit components board layout high resolution driving. However, on-board driver simplifies user. that needed decouple AINP AINM with 1-nF decoupling capacitor across these terminals close device possible. multiplexer inputs tolerate source impedance specified device performance 1-MSPS operating speed. This relaxes constraints signal conditioning circuit. case true bipolar input signals, possible condition them with resister divider shown Figure device permits 1.2-k resistors divider with effective source impedance signal less than kHz. suitable capacitor value used limit signal which limits noise coming from resistor divider network. Care must taken about absolute analog voltage multiplexer input terminals. This voltage should exceed VEE. clamp driver limits voltage applied input.
Reading Data
ADS8255 outputs full parallel data straight binary format shown Table parallel output active when both low. There minimal quiet zone requirement around falling edge CONVST. This prior falling edge CONVST after falling edge. data read should attempted within this zone. other combination sets parallel output 3-state. BYTE used multiword read operations. BYTE used whenever lower bits output higher byte bus. Refer Table ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full scale range Least significant (LSB) +Full scale Midscale Midscale Zero ANALOG VALUE +Vref +Vref/65536 (+Vref) +Vref/2 +Vref/2-1LSB DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 CODE 7FFF 0000 FFFF 8000
output data full 16-bit word (D15-D0) DB15-DB0 pins (MSB-LSB) BYTE low. result also read 8-bit convenience. This done using only pins DB15-DB8. this case reads necessary: first before, leaving BYTE reading most significant bits pins DB15-DB8, then bringing BYTE high. When BYTE high, bits (D7-D0) appear pins DB15-DB8. This multiword read operation performed with multiple active (toggling) with held simplicity. This referred AUTO READ operation. Table Conversion Data Read
DATA READ BYTE High PINS DB15-DB8 D7-D0 D15-D8 PINS DB7-DB0 One's D7-D0
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8255IBRGCR ADS8255IBRGCT ADS8255IRGCR ADS8255IRGCT
Status PREVIEW PREVIEW PREVIEW PREVIEW
Package Type VQFN VQFN VQFN VQFN
Package Drawing
Pins Package Plan 2000 2000
Lead/Ball Finish Call Call Call Call
Peak Temp Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
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