HB54R1G9F2-B75B/10B (128M words bits, Ranks) HB54R1G9F2 128M rank
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Registered SDRAM DIMM
HB54R1G9F2-B75B/10B (128M words bits, Ranks)
HB54R1G9F2 128M rank Double Data Rate (DDR) SDRAM Module, mounting pieces 256Mbits SDRAM sealed package, piece clock driver, pieces register driver piece serial EEPROM bits EEPROM) Presence Detect (PD). Read write operations performed cross points /CK. This high-speed data transfer realized 2-bit prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. outline products 184-pin socket type package (dual lead out). Therefore, makes high density mounting possible without surface mount technology. provides common data inputs outputs. Decoupling capacitors mounted beside each module board. Note: push cover drop modules order protect from mechanical defects, which would electrical defects.
Features
184-pin socket type package (dual lead out) Outline: 133.35mm (Length) 43.18mm (Height) 4.80mm (Thickness) Lead pitch: 1.27mm 2.5V power supply (VCC/VCCQ) SSTL-2 interface inputs outputs Clock frequency: 133MHz/125MHz (max.) Data inputs outputs synchronized with banks operate simultaneously independently (Component) Burst read/write operation Programmable burst length: Burst read stop capability Programmable burst sequence Sequential Interleave Start addressing capability Even Programmable /CAS latency (CL): 8192 refresh cycles: 7.8µs (8192/64ms) variations refresh Auto refresh Self refresh
Document E0089H50 (Ver. 5.0) Date Published March 2003 Japan URL: http://www.elpida.com
This product became May, 2004.
Elpida Memory, Inc. 2001-2003 Hitachi, Ltd. 2000 Elpida Memory, Inc. joint venture DRAM company Corporation Hitachi, Ltd.
HB54R1G9F2-B75B/10B
Ordering Information
Part number HB54R1G9F2-B75B*1 HB54R1G9F2-10B*2 Clock frequency (max.) latency Package Contact
184-pin dual lead socket Gold type
Notes: 100MHz operation /CAS latency 3.0. 125MHz operation /CAS latency 3.5.
Configurations
Front side
name VREF DQS0 /RESET DQS1 VCCQ DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 DQ18 VCCQ
Data Sheet E0089H50 (Ver. 5.0)
Back side
name DQS8 DQ32 VCCQ DQ33
name VCCQ DM0/DQS9 VCCQ DQ12 DQ13 DM1/DQS10
name DM8/DQS17 VCCQ DQ36 DQ37 DM4/DQS13 DQ38 DQ39 DQ44 /RAS DQ45 VCCQ DM5/DQS14
DQS4 DQ34 DQ35 DQ40 VCCQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49
DQ14 DQ15 CKE1 VCCQ DQ20 DQ21 DM2/DQS11 DQ22
DQ46 DQ47 VCCQ DQ52 DQ53
HB54R1G9F2-B75B/10B
name DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 name VCCQ DQS6 DQ50 DQ51 VCCID DQ56 DQ57 DQS7 DQ58 DQ59 name DQ23 DQ28 DQ29 VCCQ DM3/DQS12 DQ30 DQ31 VCCQ /CK0 name DM6/DQS15 DQ54 DQ55 VCCQ DQ60 DQ61 DM7/DQS16 DQ62 DQ63 VCCQ VCCSPD
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
name BA0, DQ63 /RAS /CAS /S0, Function Address input address Column address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input output data strobe Clock input serial Data input/output serial Serial address input Power internal circuit Power circuit Power serial EEPROM Input reference voltage Ground
Bank select address
CKE0, CKE1 /CK0 DQS0 DQS8 VCCQ VCCSPD VREF VCCID /RESET
DM8/DQS9 DQS17
Data Sheet E0089H50 (Ver. 5.0)
identification flag connection
Reset (forces register inputs low)
HB54R1G9F2-B75B/10B
Serial Matrix*
Byte
Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments byte SDRAM bits SSTL 2.5V 2.5*5
-10B -10B -10B
Voltage interface level this assembly
SDRAM cycle time, -B75B SDRAM access from clock (tAC) -B75B
0.75ns*5 0.8ns*5 Self refresh Registered 0.2V 0.75ns*5 0.8ns*5
DIMM configuration type Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General
Minimum clock cycle time Maximum data access time (tAC) from clock -B75B Minimum clock cycle time Maximum data access time (tAC) from clock Minimum precharge time (tRP) Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD)
Data Sheet E0089H50 (Ver. 5.0)
20ns 15ns 20ns
HB54R1G9F2-B75B/10B
Byte Function described Minimum active precharge time (tRAS) -B75B -10B Module rank density Address command setup time before clock (tIS) -B75B -10B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments 45ns 50ns ranks 512MB 0.9ns*5 1.1ns*5 0.9ns*5 1.1ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future 65ns*5 70ns*5 75ns*5 80ns*5
Address command hold time after clock (tIH) -B75B -10B Data input setup time before clock (tDS) -B75B -10B Data input hold time after clock (tDH) -B75B -10B Superset information
-10B -10B -10B -10B revision -10B
Active command period (tRC) -B75B
Auto refresh active/ Auto refresh command cycle (tRFC) -B75B SDRAM cycle max. (tCK max.) Dout skew -B75B Data hold skew (tQHS) -B75B Superset information Checksum bytes B75B Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number
Data Sheet E0089H50 (Ver. 5.0)
12ns*
500ps*5 600ps*5 750ps*5 1000ps*5 Future Initial HITACHI (ASCII-8bit code)
HB54R1G9F2-B75B/10B
Byte Function described Module part number Module part number Module part number Module part number Module part number -B75B -10B Module part number -B75B -10B Module part number -B75B -10B Module part number -B75B -10B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Revision code Revision code
Module part number
Manufacturing date Manufacturing date
Module serial number
Manufacturer specific data
Notes: serial data protected. Serial data, "driven Low", Serial data, "driven High" Byte72 manufacturing location code. (ex: case Japan, byte72 4AH. shows ASCII code.) Bytes through assembly serial number. bits through defined ("1" "0"). These specifications defined based component specification, module.
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
Block Diagram
/RS1 /RS0 DQS0 DQS1 DQ11 DQS2 DQ16 DQ19 DQS3 DM3/DQS12 DQ28 DQ31 DM4/DQS13 DQ36 DQ39 DM5/DQS14 DQ44 DQ47 DM6/DQS15 DQ52 DQ55 DM7/DQS16 DQ60 DQ63 DM8/DQS17 DQ20 DQ23 DM2/DQS11 DQ12 DQ15 DM1/DQS10
DM0/DQS9
DQS8
DQ24 DQ27
DQS4
DQ32 DQ35
DQS5
DQ40 DQ43
DQS6
DQ48 DQ51
DQS7 DQ56 DQ59
/RAS /CAS CKE0 CKE1
/RS0 /CS: SDRAMs
/RS1 /CS: SDRAMs
RBA0 RBA1 BA1: SDRAMs RA12 A12: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs RCKE0 CKE: SDRAMs
D35: 256M bits SDRAM bits EEPROM (DQ, DQS) PLL: CDC857 Register: SSTV16859 Serial
RCKE1 CKE: SDRAMs /RWE /WE: SDRAMs /RESET
/PCK
VCC, VCCQ VREF VCCID open
Notes: pull-up resistor required open-drain/open-collector output. pull-up resistor recommended because normal line inacitve "high" state.
CK0, /CK0 PLL* Note: Wire Clock loading table/Wiring diagrams.
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
Differential Clock Wiring (CK0, /CK0)
(nominal) SDRAM stack
OUT1
SDRAM stack Register1
/CK0
OUT'N'
(Typically registers DIMM)
Feedback Register2
Notes: clock delay from input clock input SDRAM register willl (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located after pins PLL.
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
Functions
(CLK), (/CLK) (input pin): master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (/CS) (input pin): When Low, commands data input. When High, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins): These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation".
Functions
(input pins): address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9, AY11) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin): defines precharge mode when precharge command, read command write command issued. High when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. High when read write command, auto-precharge function enabled. While Low, auto-precharge function disabled. BA0, (input pin): BA0/BA1 bank select signals. memory array divided into bank bank bank bank Low, bank selected. High Low, bank selected. High, bank selected. High High, bank selected. (input pin): controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes High. level must kept cycle LCKEPW) least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH.
(input output pins): Data input output from these pins.
(input output pin): provide read data strobes output) write data strobes input). VCCQ (power supply pins): 2.5V applied. (VCC internal circuit VCCQ output buffer.)
VCCSPD (power supply pin): 2.5V applied (For serial EEPROM). (power supply pin): Ground connected.
/RESET (input pin): LVCMOS reset input. When /RESET low, registers reset outputs low.
Detailed Operation Part, Characteristics Timing Waveforms
Refer Series datasheet (E0086H). pins component device fixed level module board. DIMM /CAS latency Device registered type.
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC, VCCQ IOUT Tstg Value -1.0 +4.6 -1.0 +4.6 +100 Unit Note
Notes: Respect VSS. SDRAM component specification. Operating Conditions +70°C) (DDR SDRAM Component Specification)
Parameter Symbol VCC, VCCQ VREF (DC) min. 1.15 VREF 0.04 VREF 0.18 -0.3 -0.3 1.25 VREF max. 1.35 VREF 0.04 VCCQ VREF 0.18 VCCQ VCCQ Unit Notes
Supply voltage Input reference voltage Termination voltage Input high voltage Input voltage Input signal voltage differential input voltage Ambient illuminance
VSWING (DC) 0.36
Notes:
parameters referred VSS, when measured. VCCQ must lower than equal VCC. allowed exceed 4.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. VSWING (DC) specifies input differential voltage required switching.
Data Sheet E0089H50 (Ver. 5.0)
HB54R1G9F2-B75B/10B
Characteristics +70°C, VCC, VCCQ 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B -B75B -10B max. 2928 2559 3828 3459 1668 1479 1128 2028 1839 5088 4809 4728 4449 4818 4359 Unit Test condition Notes
VIH, min. VIH, 3.5, min. VIH, VIH, tRAS max. VIH, VIH, tRFC min., Input Input 0.2V Input 0.2V.
Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P Idle standby current Active power down standby current Active standby current ICC2N ICC3P ICC3N ICC4R ICC4W ICC5 ICC6
Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current
Notes.
These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. Data/Data mask transition twice cycle. data this table measured with regard min. general.
Characteristics +70°C, VCC, VCCQ 2.5V 0.2V,
Parameter Input leakage current Output leakage current Output high voltage Output voltage Symbol min. max. Unit Test condition VOUT (max.) -15.2mA (min.) 15.2mA Notes
Note: SDRAM component specification.
Data Sheet E0089H50 (Ver. 5.0)
1.95 0.35
HB54R1G9F2-B75B/10B
Capacitance 25°C, VCC, VCCQ 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, /WE, DQS, max. Unit Notes
Notes: These parameters measured conditions: 100MHz, VOUT VCCQ/2, VOUT 0.2V. Dout circuits disabled. This parameter sampled 100% tested. Timing Parameter Measured Clock Cycle Registered DIMM
Number clock cycle Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD min. BL/2 BL/2 BL/2 BL/2 BL/2 max. Unit.
Parameter 3.5) 3.5) 3.5) 3.5) Write recovery Power down entry minimum pulse width
Write pre-charge command delay (same bank) Read pre-charge command delay (same bank) Write read command delay input data) Burst stop command write command delay Burst stop command High-Z
Read command write command delay output data) Pre-charge command High-Z Write command data latency
Register command active register command Self refresh exit non-read command Self refresh exit read command
Power down exit command input
Data Sheet E0089H50 (Ver. 5.0)
tHZP tHZP tWCD tMRD tSNR tSRD tPDEN tPDEX tCKEPW
HB54R1G9F2-B75B/10B
Physical Outline
Unit: 133.35 0.15 128.95 4.80 (64.48) (DATUM -A-)
2.30
Component area (Front)
64.77 49.53
1.27 0.10
2.50 0.10
10.00
4.00
4.00 0.10
2.50 0.20
0.20 0.15
3.80
2.00
Component area (Back)
3.00
Detail
Detail 1.27 6.62 2.175 0.90 (DATUM -A-)
6.35
1.00 0.05
1.80 0.10
Note: Tolerance dimensions 0.13 unless otherwise specified.
ECA-TS2-0052-01
Data Sheet E0089H50 (Ver. 5.0)
43.18 0.15
17.80
HB54R1G9F2-B75B/10B
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet E0089H50 (Ver. 5.0)
CME0107
HB54R1G9F2-B75B/10B
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
Data Sheet E0089H50 (Ver. 5.0)
M01E0107
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