EBJ82HF4B1RA (1024M words bits, Ranks) Density: Organization 1024

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EBJ82HF4B1RA (1024M words bits, Ranks) Density: Organization 1024

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Registered DDR3 SDRAM DIMM
EBJ82HF4B1RA (1024M words bits, Ranks)
Density: Organization 1024M words bits, ranks Mounting pieces bits DDR3 SDRAM with (FBGA) DDP: pieces bits chips sealed package Package: 240-pin socket type dual line memory module (DIMM) height: 30.5mm (max.) Lead pitch: 1.0mm Lead-free (RoHS compliant) Power supply: 1.5V 0.075V Data rate: 1066Mbps/800Mbps (max.) Eight internal banks concurrent operation (components) Interface: SSTL_15 Burst lengths (BL): with Burst Chop (BC) /CAS Latency (CL): /CAS write latency (CWL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Posted /CAS programmable additive latency better command data efficiency On-Die-Termination (ODT) better signal quality Synchronous Dynamic Asynchronous Multi Purpose Register (MPR) temperature read calibration drive Programmable Partial Array Self-Refresh (PASR) /RESET Power-up sequence reset function range: Normal/extended Auto/manual self-refresh Programmable Output driver impedance control piece registering clock driver piece serial EEPROM (256 bytes EEPROM) Presence Detect (PD) Class temperature sensor functionality with EEPROM Note: Warranty void removed DIMM heat spreader.
Document E1306E30 (Ver. 3.0) Date Published December 2008 Japan Printed Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008
EBJ82HF4B1RA
Ordering Information
Component JEDEC speed bin* Data rate Mbps(max.) (CL-tRCD-tRP) 1066 DDR3-1066F (7-7-7) DDR3-800E (6-6-6) Contact Gold
Part number EBJ82HF4B1RA-AE-E EBJ82HF4B1RA-8C-E
Package 240-pin DIMM (lead-free)
Mounted devices bits DDR3 SDRAM*
Notes: Module /CAS latency component Please refer DDR3 datasheet (E1128E) electrical characteristics.
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Configurations
Front side
Back side
name VREFDQ /DQS0 DQS0 /DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2 DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26
name /CK1 VREFCA Par_In A10(AP) /CAS /CS1 ODT1 /CS2 DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35 DQ40 DQ41 /DQS5 DQS5 DQ42
name DQS9 /DQS9 DQ12 DQ13 DQS10 /DQS10 DQ14 DQ15 DQ20 DQ21 DQS11 /DQS11 DQ22 DQ23 DQ28 DQ29 DQS12 /DQS12 DQ30 DQ31
name /CK0 /EVENT /RAS /CS0 ODT0 /CS3 DQ36 DQ37 DQS13 /DQS13 DQ38 DQ39 DQ44 DQ45 DQS14 /DQS14 DQ46 DQ47
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
name DQ27 /DQS8 DQS8 CKE0 /Err_Out name DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 /DQS7 DQS7 DQ58 DQ59 name DQS17 /DQS17 /RESET CKE1 name DQ52 DQ53 DQS15 /DQS15 DQ54 DQ55 DQ60 DQ61 DQS16 /DQS16 DQ62 DQ63 VDDSPD
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Description
name (AP) (/BC) BA0, BA1, DQ63 /RAS /CAS /CS0, /CS1, /CS2, /CS3 CKE0, CKE1 CK0, /CK0, /CK1 DQS0 DQS17, /DQS0 /DQS17 SA0, SA1, VDDSPD VREFCA VREFDQ /RESET ODT0, ODT1 Par_In /Err_Out /Event Function Address input address Column address Auto precharge Burst chop Bank select address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Reference voltage Reference voltage Ground Termination Voltage DRAM known state control Parity Address Control Parity error found Address Control Temperature event connection
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Serial Matrix
Byte Function described Number serial bytes written/SPD device size/CRC coverage revision byte/DRAM device type byte/module type SDRAM density banks SDRAM addressing Module nominal voltage, Module organization Module memory width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) Reserved SDRAM /CAS latencies supported, SDRAM /CAS latencies supported, SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM write recovery time (tWR) SDRAM minimum /RAS /CAS delay (tRCD) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value 37.5ns 50.625ns 52.5ns 110ns Comments 176/256/0-116 Revision DDR3 SDRAM Registered bits, banks rows, columns 1.5V bits bits/ECC 1.875ns 2.5ns 13.125ns 15ns 15ns 13.125ns 15ns 7.5ns 10ns 13.125ns 15ns
SDRAM minimum active active delay (tRRD) SDRAM minimum precharge time (tRP)
SDRAM upper nibbles tRAS
SDRAM minimum active precharge time (tRAS), SDRAM minimum active active /autorefresh time (tRC), SDRAM minimum refresh recovery time delay (tRFC),
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Byte Function described SDRAM minimum refresh recovery time delay (tRFC), SDRAM minimum internal write read command delay (tWTR) SDRAM minimum internal read precharge command delay (tRTP) Upper nibble tFAW Minimum four activate window delay time (tFAW) SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments 110ns 7.5ns 7.5ns 37.5ns 37.5ns 40ns DLL-off, RZQ/6, PASR/2X refresh rate +85°C +95°C Incorporated standard height 31mm
Reserved Module nominal height Module maximum thickness Reference card used DIMM module attributes Heat spreader solution Register vender (LSB) (Inphi) (TI) Register vender (MSB) (Inphi) (TI) Register revision (Inphi) (TI) Register type Register control word function (RC0, Register control word function (RC2, Register control word function (RC4, Register control word function (RC6, Register control word function (RC8,
card 2row/2register Incorporated Naming bank=5 Naming bank=1 Actual
Rev.4 Rev. SSTE32882 Default Default Default Default Default Default Default Default
Register control word function (RC10, Register control word function (RC12, Register control word function (RC14, Module specific section
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Byte Function described Module manufacturer's JEDEC code, Module manufacturer's JEDEC code, Module manufacturing location Module manufacturing date Module manufacturing date Module module serial number Cyclical redundancy code (CRC) (Inphi) (TI) (Inphi) (TI) Cyclical redundancy code (CRC) (Inphi) (TI) (Inphi) (TI) Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module revision code Module revision code
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments Elpida Memory Elpida Memory
Year code (BCD) Week code (BCD)
(Space) Initial (Space)
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Byte Function described SDRAM manufacturer's JEDEC code, SDRAM manufacturer's JEDEC code, Manufacturer's specific data Open customer
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments Elpida Memory Elpida Memory
Data Sheet E1306E30 (Ver. 3.0)
Block Diagram
DQS1
DQS2
DQS3
/DQS1
/DQS2
/DQS3
DQS0
DQS8
DQ16 DQ19
DQ24 DQ27
DQ11
/DQS0
/DQS8
Data Sheet E1306E30 (Ver. 3.0)
Command Command Command Command /ARCS0_A
/DQS
/DQS
/DQS
/DQS
/DQS
Command
/ARcommand_A APCK0_A
Address,
Address,
/APCK0_A ARCKE0_A ARODT0_A
0.1µF
Address,
Address,
Address,
AR[Address,BA]_A
/DQS
/DQS
/DQS
/DQS
/DQS
/ARCS1_A
Block Diagram
Command Address, Command Address,
Command Address,
Command Address,
Command Address,
ARCKE1_A
Command Command Address,
Command
/BRCS2_A
/DQS
/DQS
/DQS
/DQS
/DQS
Command Address,
/BRcommand_A BPCK0_A Address,
Command
Address,
0.1µF
/BPCK0_A BRCKE0_A BRODT1
/DQS /DQS
Address,
BR[Address,BA]_A
/DQS
/DQS
/DQS
/BRCS3_A
EBJ82HF4B1RA
Command Address, Command Address,
Command Address,
Command Address,
Command Address,
BRCKE1_A
DQS17
DQS10
DQS11
DQS12
/DQS17
/DQS10
/DQS11
/DQS12
DQS9
DQ12 DQ15
DQ20 DQ23
DQ28 DQ31
/DQS9
Data Sheet E1306E30 (Ver. 3.0)
/DQS /DQS /DQS /DQS /DQS
Command /ARCS0_A
Address, Address,
Command
Command
Command
Command
/ARcommand_A APCK1_A /APCK1_A
0.1µF
Address, Address,
ARCKE0_A
Address,
ARODT0_A AR[Address,BA]_A
/DQS
/DQS
/DQS
/DQS
/DQS
/ARCS1_A
Command Command Address, Address,
Block Diagram
Address,
Command Address,
Command
Command
ARCKE1_A Address,
/DQS
/DQS
/DQS
/DQS
/DQS
Command Command Address,
Command
/BRCS2_A
Address,
Command
Command
/BRcommand_A BPCK1_A
/BPCK1_A BRCKE0_A Address,
Address,
0.1µF
Address,
BRODT1 BR[Address,BA]_A
/DQS
/DQS
/DQS
/DQS
/DQS
Command Address, Command
Command
/BRCS3_A
EBJ82HF4B1RA
Address,
Command Address,
Command Address,
BRCKE1_A Address,
DQS7 DQS4
DQS6
DQS5
/DQS7 /DQS4
/DQS6
/DQS5
DQ56 DQ59 DQ32 DQ35
DQ48 DQ51
/ARCS0_B
DQ40 DQ43
/DQS
/DQS
/DQS
/DQS
Data Sheet E1306E30 (Ver. 3.0)
Command
Command
Command Command Address,
/ARcommand_B APCK0_B /APCK0_B
Address, Address,
0.1uF
Address,
ARCKE0_B ARODT0_B
AR[Address,BA]_B
/DQS
/DQS
/DQS
/DQS
/ARCS1_B
Block Diagram
Command Address,
Command Address,
Command Address,
Command Address,
ARCKE1_B
Command
/DQS
/DQS
/DQS
/DQS
Command
Command
/BRCS2_B
Command
/BRcommand_B BPCK0_B
Address,
Address,
/BPCK0_B BRCKE0_B BRODT1
0.1µF
Address,
Address,
BR[Address,BA]_B
/DQS
/DQS
/DQS
/DQS
/BRCS3_B
EBJ82HF4B1RA
Command Address,
Command Address,
Command Address,
Command Address,
BRCKE1_B
DQS13
/DQS13
DQS16
DQS15
DQS14
/DQS16
/DQS15
/DQS14
DQ36 DQ39
DQ60 DQ63
DQ52 DQ55
/ARCS0_B
DQ44 DQ47
/DQS
/DQS
/DQS
/DQS
Data Sheet E1306E30 (Ver. 3.0)
Command
Command
Command Command Address,
/ARcommand_B APCK1_B /APCK1_B
Address, Address,
0.1µF
Address,
ARCKE0_B ARODT0_B
AR[Address,BA]_B
/DQS
/DQS
/DQS
/DQS
/ARCS1_B
Block Diagram
Command Address,
Command Address,
Command Address,
Command Address,
ARCKE1_B
Command
/DQS
/DQS
/DQS
/DQS
Command
Command
/BRCS2_B
Command
/BRcommand_B BPCK1_B
Address,
Address,
/BPCK1_B BRCKE0_B BRODT1
0.1µF
Address,
Address,
BR[Address,BA]_B
/DQS
/DQS
/DQS
/DQS
/BRCS3_B
EBJ82HF4B1RA
Command Address,
Command Address,
Command Address,
Command Address,
BRCKE1_B
EBJ82HF4B1RA
/CS0*2 /CS1*2 Address Command CKE0 CKE1 ODT0
/ARCS0_A /CS: SDRAMs D12, /ARCS0_B /CS: SDRAMs
/ARCS1_A /CS: SDRAMs D21, D30, /ARCS1_B /CS: SDRAMs D25,
ARBA_A BA2: SDRAMs D12, D21, D30, ARBA_B BA2: SDRAMs D16, D25, ARAddress_A A13: SDRAMs D12, D21, D30, ARAddress_B A13: SDRAMs D16, D25, ARCommand_A /RAS, /CAS, /WE: SDRAMs D12, D21, D30, ARCommand_B /RAS, /CAS, /WE: SDRAMs D16, D25,
ARCKE0_A CKE1: SDRAMs D12, ARCKE0_B CKE1: SDRAMs ARCKE1_A CKE0: SDRAMs D21, D30, ARCKE1_B CKE0: SDRAMs D25, ARODT0_A ODT1: SDRAMs D12, ARODT0_B ODT1: SDRAMs APCK0_A APCK0_B APCK1_A APCK1_B /APCK0_A /CK: /APCK0_B /CK: /APCK1_A /CK: /APCK1_B /CK: /Err_Out SDRAMs D21, SDRAMs SDRAMs D12, D17, D30, SDRAMs D16, SDRAMs D21, SDRAMs SDRAMs D12, D17, D30, SDRAMs D16,
/CK0
Par_In
/RESET
/RESET
/RESET: SDRAMs
Block Diagram
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
/CS2*2 /CS3*2 Address Command CKE0 CKE1 ODT0
/BRCS2_A /CS: SDRAMs D39, D48, /BRCS2_B /CS: SDRAMs D43,
/BRCS3_A /CS: SDRAMs D57, D66, /BRCS3_B /CS: SDRAMs D61,
BRBA_A BA2: SDRAMs D39, D48, D57, D66, BRBA_B BA2: SDRAMs D43, D52, D61, BRAddress_A A13: SDRAMs D39, D48, D57, D66, BRAddress_B A13: SDRAMs D43, D52, D61, BRCommand_A /RAS, /CAS, /WE: SDRAMs D39, D48, D57, D66, BRCommand_B /RAS, /CAS, /WE: SDRAMs D43, D52, D61,
BRCKE0_A CKE1: SDRAMs D39, D48, BRCKE0_B CKE1: SDRAMs D43, BRCKE1_A CKE0: SDRAMs D57, D66, BRCKE1_B CKE0: SDRAMs D61, BRODT1_A ODT1: SDRAMs D39, D48, BRODT1_B ODT1: SDRAMs D43, BPCK0_A BPCK0_B BPCK1_A BPCK1_B SDRAMs D43, SDRAMs D39, D44, D57, SDRAMs D48, D53, D66, SDRAMs D52,
/CK0
/BPCK0_A /CK: SDRAMs D43, /BPCK0_B /CK: SDRAMs D39, D44, D57, /BPCK1_A /CK: SDRAMs D48, D53, D66, /BPCK1_B /CK: SDRAMs D52,
Par_In
/Err_Out
/RESET
/RESET
/RESET: SDRAMs
Note: wiring changed within nibble.
/CK1 VDDSPD VREFCA VREFDQ
Terminated near card edge
D71: bits DDR3 SDRAM Address, A15, Command: /RAS, /CAS, bytes EEPROM Rs1: Rs2: Rs3: Rs4: Rs5: Rs6: Register: SSTE32882
SDRAMs D71) SDRAMs D71) SDRAMs D71)
SDRAMs D71),
Serial
/EVENT
/EVENT
Block Diagram
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Register
Address, command control line
Unused register inputs ODT1 Register ODT0 Register tied ground.
Block Diagram
Data Sheet E1306E30 (Ver. 3.0)
Register
EBJ82HF4B1RA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage Storage temperature Power dissipation Short circuit output current Symbol VOUT VREFCA VREFDQ Tstg IOUT Value -0.4 +1.975 -0.4 +1.975 -0.4 +1.975 -0.4 -0.4 VDDQ +100 Unit Notes
Notes: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Storage temperature case surface temperature center/top side DRAM. VDDQ must within 300mV each other times; VREF must greater than VDDQ, When VDDQ less than 500mV; VREF equal less than 300mV. DDR3 SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol Rating Unit Notes
Notes: Operating temperature case surface temperature center/top side DRAM. Normal Temperature Range specifies temperatures where DRAM specifications will supported. During operation, DRAM case temperature must maintained between +85°C under operating conditions. Some applications require operation DRAM Extended Temperature Range between +85°C +95°C case temperature. Full specifications guaranteed this range, following additional conditions apply: Refresh commands must doubled frequency, therefore reducing refresh interval tREFI 3.9µs. (This double refresh requirement apply some devices.) Self-refresh operation required Extended Temperature Range, then mandatory either Manual Self-Refresh mode with Extended Temperature Range capability (MR2 [A6, enable optional Auto Self-Refresh mode (MR2 [A6, 0]).
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Recommended Operating Conditions +85°C)
Parameter Supply voltage Symbol VDD, VDDQ VDDSPD Input reference voltage Input reference voltage Termination voltage VREFCA (DC) VREFDQ (DC) min. 1.425 0.49 VDDQ 0.49 VDDQ VDDQ/2 typ. max. 1.575 Unit Notes
0.50 VDDQ 0.51 VDDQ 0.50 VDDQ 0.51 VDDQ VDDQ/2
Notes:
DDR3 SDRAM component specification. Under conditions VDDQ must less than equal VDD. VDDQ tracks with VDD. parameters measured with VDDQ tied together. peak noise VREF allow VREF deviate from VREF(DC) more than (for reference: approx mV). reference: approx. VDD/2
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Characteristics +85°C, 1.5V 0.075V,
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Precharge power-down standby current IDD2PS Precharge quiet standby current Precharge standby current Active power-down current (Always fast exit) Active standby current Operating current (Burst read operating) Operating current (Burst write operating) Burst refresh current Self-refresh current normal temperature range bank interleave read current IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7R 1066 Symbol IDD0 IDD1 IDD2PF Data rate (Mbps) 1066 1066 1066 1066 1066 1066 1066 1066 1066 1066 1066 max. 4340 4030 4610 4310 2810 2720 2810 2720 3910 3610 3910 3610 2530 2440 3650 3340 5050 4410 5370 4690 7510 7280 2590 7020 6490 Unit Fast Exit Slow Exit Notes
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Timing Test Conditions purposes testing, following parameters utilized.
DDR3-1066 Parameter (IDD) min.(IDD) tRCD min. (IDD) min. (IDD) tRAS min.(IDD) min. (IDD) tFAW (IDD) tRRD (IDD) tRFC (IDD) 7-7-7 1.875 13.13 50.63 37.5 13.13 37.5 DDR3-800 6-6-6 52.5 37.5 Unit
Characteristics +85°C, VDD, VDDQ 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value Unit Notes VOUT
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Functions
(input pin) differential clock inputs. address control input signals sampled crossing positive edge negative edge /CK. Output (read) data referenced crossings (both directions crossing). (input pin) commands masked when registered high. provides external rank selection systems with multiple ranks. considered part command code. /RAS, /CAS, (input pins) /RAS, /CAS (along with /CS) define command being entered. (input pins) Provided address active commands column address read/write commands select location memory array respective bank. (A10(AP) A12(/BC) have additional functions, below) address inputs also provide op-code during mode register commands. [Address Pins Table]
Address A13) address (RA) AX13 Column address (CA) AY9, Notes
A10(AP) (input pin) sampled during read/write commands determine whether auto-precharge should performed accessed bank after read/write operation. (high: auto-precharge; low: auto-precharge) sampled during precharge command determine whether precharge applies bank (A10 low) banks (A10 high). only bank precharged, bank selected bank addresses (BA). (/BC) (input pin) sampled during read write commands determine burst chop (on-the-fly) will performed. (A12 high: burst chop, low: burst chopped.) (input pins) BA0, define which bank active, read, write precharge command being applied. also determine mode register accessed during cycle. [Bank Select Signal Table]
Bank Bank Bank Bank Bank Bank Bank Bank
Remark: VIH. VIL.
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
(input pin) high activates, deactivates, internal clock signals device input buffers output drivers. Taking provides precharge power-down self-refresh operation (all banks idle), active power-down (row active bank). asynchronous self-refresh exit. After VREF become stable during power-on initialization sequence, must maintained proper operation receiver. proper self-refresh entry exit, VREF must maintained this input. must maintained high throughout read write accesses. Input buffers, excluding /CK, disabled during power-down. Input buffers, excluding CKE, disabled during self-refresh. (input output pins) Bi-directional data bus. /DQS (input output pin) Output with read data, input with write data. Edge-aligned with read data, centered write data. data strobe paired with differential signals /DQS provide differential pair signaling system during READs WRITEs. (input pins) (registered high) enables termination resistance internal DDR3 SDRAM. When enabled, only applied each DQS, /DQS, will ignored mode register (MR1) programmed disable ODT. (power supply pins) 1.5V applied. (VDD internal circuit.) VDDSPD (power supply pin) 3.3V applied (For serial EEPROM). (power supply pin) Ground connected. (power supply pin) Termination supply. VREFDQ (power supply) Reference voltage VREFCA (power supply) Reference voltage (input pin) Clock input serial (input output pins) Data input/output serial (input pin) Serial address input. /RESET (input pin) /RESET negative active signal (active low) referred GND.
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Par_In (input pin) Parity Address Control bus. /Err_Out (output pin) Parity error found Address Control bus. /Event (output pin) Temperature alert output.
Detailed Operation Part, Electrical Characteristics Timing Waveforms
Refer EDJ1104BASE, EDJ1108BASE, EDJ1116BASE datasheet (E1128E). pins component device fixed level module board. DIMM /CAS latency component registered type.
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
Physical Outline
Unit:
Front side
8.50
(DATUM -A-)
(Front)
47.00
133.35
71.00
1.27 0.10
Back side
9.50
17.30
4.00
DIMM heat spreader
DIMM heat spreader
(Back)
Detail
Detail
Detail
(DATUM -A-)
2.50 0.20
1.00
0.20 0.15
(R0.65)
2.50
R0.75
0.80 0.05
3.80
5.00
1.50 0.10
ECA-TS2-0245-02
Data Sheet E1306E30 (Ver. 3.0)
3.00
2.10 0.15
30.50
EBJ82HF4B1RA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Data Sheet E1306E30 (Ver. 3.0)
EBJ82HF4B1RA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] aware that this product typical electronic equipment general-purpose applications. Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] Usage environments with special characteristics listed below considered design. Accordingly, company assumes responsibility loss customer third party when used environments with special characteristics listed below. Example: Usage liquids, including water, oils, chemicals organic solvents. Usage exposure direct sunlight outdoors, dusty places. Usage involving exposure significant amounts corrosive gas, including air, Usage environments with static electricity, strong electromagnetic waves radiation. Usage places where forms. Usage environments with mechanical vibration, impact, stress. Usage near heating elements, igniters, flammable items. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0706
Data Sheet E1306E30 (Ver. 3.0)

EBJ82HF4B1RA (1024M words bits, Ranks) Density: Organization 1024

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